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A B C D 11-20-2002_22:37
REVISIONS
REV ECO DESCRIPTION DATE APPROVED
A00-00 136999 Start Schematics 11/15/02 CJ_WANG
CLOCK VRM BATTERY CHARGER BATTERY
CK-408 VCORE A CONNECTOR B
(CK-TITAN) CONNECTOR CONNECTOR
(56 pin TSSOP) NORTHWOOD PAGE_37 PAGE_36 PAGE_37
1 PAGE_3 PAGE_36,39,40,41 1
LINE IN AUDIO MIC IN
uFCPGA OUT AC97 MODEM
CONNECTOR
478 pin DC-TO-DC CONVERTER PAGE_20 PAGE_20 PAGE_20 PAGE_22
PAGE_41
ITP PORT +3.3VALW +3.3VALW +5VRUN +1.5VRUN
+5VSUS +5VALW +12V +3.3VRUN VCCT_CORE
I2S DOCK INTERFACE
PAGE_6 PAGE_4-5
AC97 CODEC
AGTL+ PAGE_19
VCC CORE
100MHZ
400MT/S (2X ADDRESS 4X DATA) USB USB MiniPCI Revolution CARDBUS 1394a
Port 0 Port 4 Connector 3COM LAN CONNECTOR Port
CRT PAGE_18 PAGE_18 PAGE_27 PAGE_21 PAGE_25 PAGE_26
Connector USB 1.1
PAGE_12 VIDEO CARD
AGP4X (3.3V/1.5V) AGP4X
1.5V CARDBUS 1394a
180 PIN CONNECTOR AC97 INTERFACE
SVIDEO CONTROLLER PHY
PAGE_28
2 Connector PCI4451
2
SWITCH
QUICK
PAGE_12 PAGE_24 PAGE_26
PCI BUS (33MHZ)
SWITCH
QUICK
LCD
Connector BROOKDALE
CONNECTOR
PAGE_28
ICH3M
DOCKING
USB 1.1 (PORTS 3,5)
PAGE_11
PAGE_11 MCH (421 BGA)
(625 FC-BGA)
PC1600=1.6GB/S
200/266MHZ
SECONDARY IDE CHANNEL (ATA66/ATA100) CP MODULE FDD INTERFACE
SWITCH
QUICK
BATT/FDD/DVD/CD
HUBLINK
PAGE_28
(1.8V) PAGE_17
LPC INTERFACE (3.3V) (33MHZ)
(66MHZ)
(266MB/S)
DDR DDR
PRIMARY IDE CHANNEL (ATA66/ATA100)
SODIMM SODIMM
0 1
3 3
HDD MODULE FWH SMC Kahuna
OPTICAL MODULE 32PLCC Super I/O PS2/SIO
(CDROM/DVD)
LPT/IRDA
PAGE_10 PAGE_10 PAGE_7-9 PAGE_13-16 PAGE_17 PAGE_17 PAGE_23 PAGE_30-31
SMBUS/I2C
PS/2 LPT RS232 IrDA PAGE_29
PAGE_35 PAGE_34 PAGE_34 PAGE_35
A CURRENT ISSUE OF THIS DRAWING MUST
PARTS INCLUDE A COPY OF THE FOLLOWING
This design requires a font mapping of ECO'S:
M50
ECO DATE
A00
ASSY,PWA,MN,NV28,M50 (9Y422)
PWA,PLN,MN,NV28,M50 (9Y422)
Fixed to scaleable Arial with a scaling ECO
ECO
DATE
DATE
ECO DATE
ASSEMBLY BARCODE LABEL (XXXXX)
ASSEMBLY REVISION LABEL (XXXXX)
factor of 1.0 ECO
ECO
DATE
DATE
ASSY DWG,PLN,MN,NV28,M50 (XXXXX) ECO DATE
ECO DATE
PWB,PLN,MN,CABN (1Y802)
SCHEM,PLN,MN,NV28,M50 (C0370)
Please remember when copying PROPRIETARY NOTE
DRAWN COMPUTER
4 4
project files that you must THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS
DESIGNED CORPORATION
AUSTIN,TEXAS
CHECKED
include both the symbols and the schematics AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER
TITLE
CORP., EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN
ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE
APPROVED SCHEMATIC, M/B LA-1221
REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL
APPROVED
COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION
EXPORT RESTRICTION: APPROVED
OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM NOR THE DWG NO. REV.
THE EXPORT OF THE INFORMATION, SCHEMATICS AND OTHER TECHNICAL DATA CONTAINED IN THIS DOCUMENT
IS CONTROLLED BY THE U.S. GOVERNMENT. THE EXPORT, DEEMED EXPORT OR OTHER TRANSFER OF THIS DATA
INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS
APPROVED 401195 4A
NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH
TO CERTAIN COUNTRIES AND INDIVIDUALS IS RESTRICTED. ANY TRANSFER, EXPORT OR REEXPORT, MUST BE THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DATE SHEET
BOM ADDS APPEAR ON PAGE 42. IN COMPLIANCE WITH THE U.S. EXPORT ADMINISTRATION REGULATIONS. DELL COMPUTER CORPORATION. RELEASED 11/15/02 52 OF 102
@SHEET=1 A B C D
A B C D 11-20-2002_22:38
NEEDS TO BE UPDATED
PAGE INDEX POWER MODES PCI TABLE
1 1. Schematic Block Diagram Power Mode Voltage Page Source ON OFF DEVICE IDSEL IRQ REQ/GNT DREQ/DGNT
1
RBAT 7.2V 32, 36 Always
2. Index PBATT+ 17V-13V 36, 37, CB - 3 Always
SBATT+ 17V-13V 36, 37, CB - 3 Always
3. System Clock, SMBUS Selector DOCK_DC_IN 20V 29, 36 Always DOCK AD24 PIRQC* REQ0*/GNT0*
DC_IN 20V 29, 36, CB - 2, 3 Always
4-5. CPU SDC_IN 20V CB - 2, 3 Always
V_CHG 15V-17.5V CB - 2 Note 1
6. CPU Voltage ID, CPU Temperature Sensor, ITP Debug Connector PWR_SRC 7.2V-20V 8, 11, 29, 36, 38, 39, 40, 41 Always 3COM AD16 PIRQC* REQ4*/GNT4*
RTCSRC 7.2V-20V 36, 39 Always
For source power on all rails, see page 44
7-9. GMCH 3VSUS 3.3V 4, 6, 10-16, 18, 21-25, 27, 30-31, 35, 38-41 S1-S3 S4-S5
RTC_PWR 5V 36, 38, 39, 41, 42 Always
PIRQA*
10. SODIMM Connectors 5VSUS 5V 8, 11, 16, 18-19, 22, 25, 29, 33-35, 38-42 S1-S3 S4-S5 VIDEO IDSEL
PIRQB*
2.5VSUS 2.5V 8-10, 39 S1-S3 S4-S5
11-12. Video Connectors VCC_CORE 0.6V-1.75V 4,5-9, 16, 23, 38,40 S1-S2 S3-S5
12V 12V 3, 11, 25, 29, 33, 36, 38, 41 S1-S2 S3-S5
13-16. ICH DOCK_PWR_SRC 13V-20V 29 Docked ALW PCI4451 AD17 PIRQD* REQB*/GNTB* REQ1*/GNT1*
3VRUN 3.3V 3, 4, 6, 11, 13-14, 16-17, 19, 21-23, 26-28, 30-31, 33, 35, 38 S1-S2 S3-S5
17. CDROM, IDE Connectors VAUX 3.3V 27 Note 2 Note 2
1.8VSUS 1.8V 16, 38-39 S1-S3 S4-S5
18. USB Hub 1.8VRUN 1.8V 7, 8, 9, 13,16, 38 S1-S2 S3-S5 M3i AD18 PIRQA* REQA*/GNTA* REQ2*/GNT2*
5VRUN 5V 6, 11-12, 16-17, 20, 27-28, 30, 32-35, 38, 42 S1-S2 S3-S5
19. Audio Codec 5VHDD 5V 17, 38 S1-S2 S3-S5
5VMOD 5V 17, 38 S1-S2 S3-S5
MINIPCI AD19 PIRQB* REQ3*/GNT3*
20. Audio Connectors, Audio Amplifiers 1.5VRUN 1.5V 7, 9, 11, 38-39 S1-S2 S3-S5
PIRQD*
STRB-_5V 5V 29, 34, 38 S1-S2 S3-S5
21. 3COM Revolution (LAN On Motherboard) VREFCG 0.7V 11 S1-S2 S3-S5
2 V_1P25V_DDR_VTT 1.25V 8, 10, 11, 38, 39 S1-S2 S3-S5 2
22. LAN and Modem Connectors CRT_VCC 5V 12 S1-S2 S3-S5
5V_QDOCK 5V 28, 30 S1-S2 S3-S5
23. Firmware Hub 5VFDDPP 5V 17, 31, 38 S1-S2 S3-S5
5VSUS_DOCKED 5V 29 Docked S1-S3 Docked S4-S5
24. Cardbus Controller USB_PWR_0/4 5V 18 S1-S2 S3-S5
VDDA 4.65V 19, 20 S1-S2 S3-S5
25. Cardbus Connector VDDA2 2.2V 19, 20 S1-S2 S3-S5 BOM BUILD OPTIONS
1.2V_VCCVID 1.2V 4, 40 S1-S3 S4-S5 Option Description
26. IEEE1394 PHY 5VALW 5V 11, 29, 30-32, 35-37, 39, 41 Note 4 Note 4
3.3VRTC 3.3V 16, 31, 36, 39, 41 Always 0 Base Build
27. MiniPCI Connector 3VALW 3.3V 6, 17, 30-32, 35, 36, 39, 41 Note 4 Note 4 1 FDD_PP
VCC_RTC 3.3V 14, 16 Always
28. Dock Buffers ICH_VBIAS 3.3V 14, 16 S1-S2 S3-S5
3VPHYD 3.3V 26 S1-S2 S3-S5
29. Dock Connector 3VPHYA 3.3V 26 S1-S2 S3-S5
CK_VDD_MAIN 3.3V 3 S1-S2 S3-S5
30-31. Super I/O Controller (Kahuna) CK_VDD_CORE 3.3V 3 S1-S2 S3-S5
V_3P3_LAN 3.3V 21, 22 S1-S3 S4-S5
32. Keyboard/Touchpad Connectors V_3P3_LAN_VDDTX 3.3V 21 S1-S3 S4-S5
V_3P3_LAN_VDDRX 3.3V 21 S1-S3 S4-S5
33. Fan Controllers and Tachometers V_MCH_GTLREF 0.67xVCC_CORE 8 S1-S2 S3-S5
S1_VPP 0V-12V Note A 25 S1-S3 S4-S5
34. Parallel and Serial Ports S2_VPP 0V-12V Note A 25 S1-S3 S4-S5
S1_VCC 0V-5V Note A 24, 25 S1-S3 S4-S5
35. PS2 Connectors, LED Connector, Power Sequencing Logic S2_VCC 0V-5V Note A 24, 25 S1-S3 S4-S5
S1_VCCF 0V-5V Note A 24, 25 S1-S3 S4-S5
36. DC-IN Connector, Charger Board Connector S2_VCCF 0V-5V Note A 24, 25 S1-S3 S4-S5
3 HL_REF 0.9V 8, 13 S1-S2 S3-S5 3
37. Battery Connectors, NiMH Support H_VCCA 1.2V 4 S1-S3 S4-S5
H_VCCIOPLL 1.2V 4 S1-S3 S4-S5
38. Power Plane Enables H_GTLREF 0.67xVCC_CORE 4 S1-S2 S3-S5
H_VSSA 1.2V 4 S1-S3 S4-S5
39. 1.8V/1.5V Switcher and Sequencer, RTC Power Source V_DDR_MCH_REF 1.25V 8, 10, 39 S1-S3 S4-S5
40. VCORE
41. DC to DC Converter
Note A Voltage delivered to these pins is determined from the type card inserted to the PCMCIA controller.
42. Mounting Holes and EMI Clips
43. Schematic Change List
Note 1 Rail is available anytime AC and BATTERY are both present, and the BIOS is not inhibiting charge
44. Power Rail Diagram
Note 2 NB powered by AC VAUX S1-S3 S4 - S5
45. SMBUS Diagram
NB powered by BATT VAUX S1-S2 S3 - S5
46-50. REFDES Page Index
Note 3 Rail is available anytime the HEADPHONE jack is occupied
Note 4 NB powered by AC 3VALW Always
NB powered by BATT 3VALW S1-S3 S4 - S5
NB powered by AC 5VALW Always
NB powered by BATT 5VALW S1-S3 S4 - S5
COMPUTER
4 CORPORATION
4
AUSTIN,TEXAS
TITLE
SCHEMATIC, M/B LA-1221
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
DWG NO. REV.
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE