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ICS90C61A

TABLE OF CONTENTS
Section Title Page
PREFACE 9-1

1.0 INTRODUCTION 9-1
1.1 Description 9-1
1.2 Features 9-2

2.0 ICS90C61 A VGA INTERFACE 9-3
2.1 System Bus Inputs 9-4
2.2 Inputs from VGA Controller 9-4
2.3 Outputs to VGA Controller 9-4
2.4 Analog Filters 9-4
2.5 User Definable Inputs 9-4
2.6 Power Considerations 9-5

3.0 PIN DESCRIPTIONS . . . 9-8

4.0 ABSOLUTE MAXIMUM RATINGS 9-9
4.1 Standard Test Conditions 9-9
4.2 D.C. Characteristics 9-9

5.0 AC Timing Characteristics 9-10

6.0 Packaging Information 9-12

11115/91 9-i
ICS90C61A

LIST OF ILLUSTRATIONS
Figure Title Page
2-1 ICS90C61A Interface 9-3
2-2 ICS90C61 A Functional Block Diagram 9-7
5-1 ICS90C61 A Timings ...... . 9-11
6-1 ICS90C61A 20-Pin PLCC Package Dimensions 9-12
6-2 Other ICS Package Dimensions . . . . . . 9-13

LIST OF TABLES
Table Title Page
1-1 VCLK Selection 9-6
1-2 MCLK Selection 9-6
3-1 Pin Descriptions 9-8
4-1 D.C. Characteristics 9-9
5-1 AC Timing Characteristics 9-10

9-ii 11/15/91
PREFACE ICS90C61A

PREFACE
The Integrated Circuit Systems ICS90C61A dual
video/memory clock generator was designed ex- ::.:::
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clusively to work with Western Digital video () S2 ()
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graphics chips. () W
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Because you get optimum video subsystem perfor-
mance when you use this video/memory clock gen-
erator with Western Digital video graphics chips, we
have included the ICS90C61 A in our databook.
SELD

SEL1
4

5