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5 4 3 2 1
P4M800PRO-M
1 CPU P4-775(FSB)
2 CPU P4-775(PWR, GND)
3 Clock Generator
Rev : 2.0
D D
4 Power (CPU Vcore)
5 Power (DC to DC)
Schedule
6 VDIMM & DDR VTT PCB Ver.
Schematics 244*244*1.6 -2116 BOM Schematics Layout Gerber Out M/B return
7 NB P4M800pro (CPU) L2:PWR DDR Area L2:GND
A A 89-200-Q22000
8 NB P4M800pro (MEM) L3:GND DDR Area L3:PWR
B B 89-200-Q22010
9 NB P4M800pro (AGP, V-Link)
1.0 1.0 89-380-Q22100
10 NB P4M800pro (VGA)
1.0A 1.0A 89-380-Q22110
11 DDR II SLOT1
1.0A. 1.0A. 89-380-Q22110
12 DDR II SLOT2
C
13 DDR I C
Rev:A Initial version:
14 DDR Terminator 1. Base on P23G to modify placement and layout
15 AGP SLOT Rev:B
1. Schematic modify for DDR2 clock input to buffer .. etc
16 SB 8237(PCI, USB) 2. Codec change to ALC655
3. Del 1394 function
4. Add RTL8100C PCI LAN optional
17 SB 8237(IDE, GPIO, AC-Link)
Rev:1.0
18 SB 8237(V-Link, MII) 1. Modify component lib.
2. Modify LAN crystal placement
19 LAN PHY(VT6103L) Rev:1.0A
1. Modify ATX 24pin power conn. placemant
20 Super IO(ITE8705F GX) 2. Add SYS_FAN smart FAN function
21 PCI 1, 2 Rev:1.0A.
1. Support INTEL .65 nm CPU(ex. 661/940 etc.)
22 PCI 3 Rev:1.9
1. Support Intel(R) CONORE CPU
B B
23 PCI LAN(RTL8100C) 2. Modify IT8705 to IT8712 Co-Lay IT8718
24 USB, PS2, IDE Rev:2.0
25 COM, LPT, VGA 1. Change R500,R506's value & remove C229 & add R589,C404,C405 for VRD11.
2. Remove R107 & add C406 & change C87's value for HW monitor.
26 Front Panel 3. Add 0.1uF(C403) CAP for waking up by ring question.
27 AUDIO(ALC655), 6CH mute function
28 Cover Page
29 Block Diagram
A A
Elitegroup Computer Systems
Title
Cover Page
Size Document Number Rev
Custom P4M800PRO-M 2.0
Date: Thursday, June 29, 2006 Sheet 1 of 29
5 4 3 2 1
5 4 3 2 1
05A
D D
PWM CLOCK Clock Gen.
Richtech 9245A P4(SMD)
VRM10.0 LG775 RTM360-520
Clock Buffer
RTM682-800
AGP 8X P4M800pro DDR
UAGP3.0 (UniChrome Pro)
DDR II-DIMM DDR1-DIMM
(1.5V interface) Graphics DDR2-533 DDR-400
V-LINK
C P-IDE C
IN ALC655 AC97 IDE
OUT AUDIO CODEC ATA 133
MIC USB
USB2.0 X 8 VCCDUAL(VCC 5V & 5V stand-by) power
VT8237R plus
PS2
KB & MS VCCDUAL(VCC 5V & 5V stand-by) power
LANPHY MII
VT6103L S-ATA
RJ45 SATA
(TQFP48)
( ) 3.3V stand-by Impedance PCB 2116
power 8/8/8(47/87)
PCI Bus LPC Bus USB_DT0+/- (45/90) 8/5/8(47/80 allegro)
7.5/7.5/7.5(50/90 guide)
PCI Bus LPC 8/8/8(47/87)
LAN RX+/-
VCC 3.3V power (50/100) 8/12/8(47/91 guide)
TX+/-
BIOS 20/6/8/6/20(56/103)
ITE8705F S-ATA (50/100) 17/6/8/6/17(guide)
LAN group mismatch 20 mil.
B (GXS version) B
RTL8100C COM & PP R.G.B (37.5) 50/10/10/10/10/10/50
12/?/12/?/12(guide)
RTL8110S PCI*3 Put 75 ohm on CON
3.3V stand-by
power
PCI Bus Resource
PCI1 AD19 INTA,BCD REQ0
FLOOPY
PCI2 AD20 INTB,CDA REQ1
PCI3 AD21 INTC,DAB REQ2
PCI LAN AD22 INTB REQ3
22U/25DE 5*7 mm 2 D
100U/16DE 6.3*11 mm D D C 3
220U/10DE 6.3*11 mm
A 470U/16DE 8*11 mm A
1 23 E BC ECB
1000U/10DE 8*14 mm 1 3 G S G S B E 1 2
G S
1500U/16DE 10*25 mm Elitegroup Computer Systems
TO-263 TO-263 TO-252 SOT-23 SOT-23 SOT-23 T0-92 T0-92 T0-92
3300U/25DE 10*25 mm
B55QS03 2SK3296 20N03 2N7002 2N3904 BAT54C LM431 2N2222A HSD882-D Title
TM3055TL-S SI2303S 2N3906 BAT54S 78L05-D 2N2097A Block Diagram
45N03 SI2301S MMBT2907A LM432
Size Document Number Rev
Custom P4M800PRO-M 1.9
Date: Friday, May 26, 2006 Sheet 2 of 29
5 4 3 2 1
A B C D E
VCC_PLL
CPU1A CPU1D
HA3 L5 K3 -A20M VCORE VCC_PLL
9 HA[3:33] A#3 A20M -A20M 20
HA4 P6 R3 -FERR C367 Y7 A20
A#4 FERR -FERR 20 GND RSVD
HA5 M5 P3 -CPUINIT C368 .1u-16VY Y5 AC4
A#5 INIT -CPUINIT 20 GND RSVD
HA6 L4 K1 INTR Y2 AE4
A#6 LINT0 INTR 20 GND RSVD
HA7 M4 L1 NMI_SB 10u-10V-08 W7 AE6
AN8
AN9
M23
M24
M25
M26
M27
M28
M29
M30
N23
N24
N25
NMI_SB 20
K23
K24
K25
K26
K27
K28
K29
K30
A#7 LINT1 GND RSVD
J10
J11
J12
J13
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
M8
-IGNNE 24.9-1-04
K8
HA8
L8
J8
J9
R4 A#8 IGNNE N2 -IGNNE 20 W4 GND RSVD AH2
HA9 T5 P2 -SMI CPU1C V7 B13 R479
A#9 SMI -SMI 20 GND RSVD
HA10 U6 L2 HTEST13 0 R268 J4 V6 C9
VCC_CPU182
VCC_CPU183
VCC_CPU184
VCC_CPU185
VCC_CPU186
VCC_CPU187
VCC_CPU188
VCC_CPU189
VCC_CPU190
VCC_CPU191
VCC_CPU192
VCC_CPU193
VCC_CPU194
VCC_CPU195
VCC_CPU196
VCC_CPU197
VCC_CPU198
VCC_CPU199
VCC_CPU200
VCC_CPU201
VCC_CPU202
VCC_CPU203
VCC_CPU204
VCC_CPU205
VCC_CPU206
VCC_CPU207
VCC_CPU208
VCC_CPU209
VCC_CPU210
VCC_CPU211
VCC_CPU212
VCC_CPU213
VCC_CPU214
VCC_CPU215
VCC_CPU216
VCC_CPU217
VCC_CPU218
VCC_CPU219
VCC_CPU220
VCC_CPU221
VCC_CPU222
VCC_CPU223
VCC_CPU224
VCC_CPU225
VCC_CPU226
A#10 SLP/TESTH13 -SLP 20 GND GND RSVD
HA11 T4 M3 -STPCLK J7 B5 V30 D1 BPM1_2
A#11 STPCLK -STPCLK 20 GND GND GND RSVD
HA12 U5 K2 B8 V3 D14
HA13
A#12 GND GND GND RSVD
U4 A#13 ADS D2 -ADS 9 K5 GND GND C10 V29 GND RSVD D16
HA14 V5 R6 K7 C13 V28 D23 VCC_PLL
A#14 ADSTB0 -HA_STB0 9 GND GND GND RSVD
4 HA15 V4 AD5 L23 C16 V27 E23 4
A#15 ADSTB1 -HA_STB1 9 GND GND GND RSVD
HA16 W5 C2 L24 C19 H28 E5 1K-04
A#16 BNR -BNR 9 GND GND GND RSVD
HA17 AB6 B2 L25 C22 AF30 E6 R480
A#17 DBSY -DBSY 9 GND GND GND RSVD
HA18 W6 G7 L26 C24 V26 E7
A#18 DEFER -DEFER 9 GND GND GND RSVD
HA19 Y6 C1 L27 C4 V25 F23
A#19 DRDY -DRDY 9 GND GND GND RSVD
HA20 Y4 A#20 HIT D4 -HIT 9 L28 GND GND C7 V24 GND RSVD G10 GTLVREF4_CPU
HA21 AA4 E4 L29 D12 V23 J3 1K-04
A#21 HITM -HITM 9 GND GND GND RSVD
HA22 AD6 E3 L3 D15 U7 N4 R481
A#22 TRDY -HTRDY 9 GND GND GND RSVD
HA23 AA5 G8 L30 D18 HTEST12 U1 N5 1K-04
A#23 BPRI -BPRI 9 GND GND GND RSVD
HA24 AB5 F3 L6 D21 T7 P5 R482
A#24 BR0 -BREQ0 9 GND GND GND RSVD
HA25 AC5 C3 L7 D24 T6
A#25 LOCK -HLOCK 9 GND GND GND
HA26 AB4 G5 M1 D3 T3
A#26 PCREQ PECI 22 GND GND GND
HA27 AF5 F2 GTLVREF3_CPU M7 D5 R7
HA28 A#27 EDRDY GND GND GND
AF4 A#28 N3 GND GND D6 R5 GNDRSVD(VID6) AM5 VID6 6
HA29 AG6 K4 N6 D9 R30 F6 51-04
A#29 REQ0 -HREQ0 9 GND GND GND IMPSEL
HA30 AG4 J5 N7 E11 R29 R188
A#30 REQ1 -HREQ1 9 GND GND GND
HA31 AG5 M6 P23 E14
A#31 REQ2 -HREQ2 9 GND GND
HA32 AH4 K6 P24 E17 LGA-775PS-AMP
A#32 REQ3 -HREQ3 9 GND GND
HA33 AH5 J6 P25 E2 VCC12
CONROE
A#33 REQ4 -HREQ4 9 GND GND
AJ5 A#34 P26 GND GND E20
AJ6 B3 P27 E25 -CPURST R287 62
A#35 RS0 -RS0 9 GND GND
F5 P28 E26 -FERR R234 62
5/24
RS1 -RS1 9 GND GND
A3 P29 E27 -IERR R235 62
RS2 -RS2 9 GND GND
HD0 B4 P30 E28 -TRIP R236 62
9 HD[0:63] D#0 GND GND
HD1 C5 B9 P4 E29 1 HTEST0 R155 62
D#1 DSTBP0 -HD_STBP0 9 GND GND
HD2 A4 C8 P7 E8 HTEST2 R163 62
D#2 DSTBN0 -HD_STBN0 9 GND GND
HD3 C6 E12 R2 F10 STP5 VTT_LEFT
D#3 DSTBP1 -HD_STBP1 9 GND GND
HD4 A5 G12 R23 F13
D#4 DSTBN1 -HD_STBN1 9 GND GND
3 HD5 B6 G19 R24 F16 HTEST1 R259 62 3
D#5 DSTBP2 -HD_STBP2 9 GND GND
HD6 B7 G20 R25 F19 HTEST8 R247 62
D#6 DSTBN2 -HD_STBN2 9 GND GND
HD7 A7 C17 R26 F22 HTEST9 R245 62
D#7 DSTBP3 -HD_STBP3 9 GND GND
HD8 A10 A16 R27 F4 HTEST10 R249 62
D#8 DSTBN3 -HD_STBN3 9 GND GND
HD9 A11 R28 F7
D#9 GND GND R483 0-O
HD10 B10 D#10 BCLK0 F28 CPU_CLK 5 AM24 GND GND G1 BPM0_2 BPM0 4
HD11 C11 G28 AM27 H10
D#11 BCLK1 -CPU_CLK 5 GND GND
HD12 D8 AJ3 AM28 H11
CONROE 5/24
HD13 D#12 ITP_CLK1 GND GND HTEST11 R271 62
B12 D#13 ITP_CLK0 AK3 AM4 GND GND H12
HD14 C12 AM7 H13 HTEST12 R258 62
HD15
D#14 PWRGD_CPU
6 VID7 GND(VID7) GND
D11 D#15 PWRGOOD N1 PWRGD_CPU 28 AN1 GND GND H14
HD16 G9 AM6 VTT_PWRGD AN10 H17 -BREQ0 R244 62
D#16 VTTPWRGD VTT_PWRGD 6,8 GND GND
HD17 F8 G23 -CPURST AN13 H18
D#17 RESET -CPURST 9 GND GND
HD18 F9 AN16 H19
HD19 D#18 R135 0 GND GND
E9 D#19 CS_GTLREF E24 GTLVREF_NB 9 AN17 GND GND H20
HD20 D7 AB2 -IERR AN2