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MS-6593 ATX Title Page
AMD PGA 462 Processor Cover S heet 1 HISTORY 47
VIA KT333 / VT8235 Chipset
D D
Block Diagram 2
Winbond 83697HF-VF LPC I/O GPIO SPEC 3
AMD 462 PGA Socket 4,5
Clock Synthesizer 6
KT333 7,8 ,9
System M emory 10,11,12
DDR Termi nations 13,14
A GP PRO SLOT 15
VT8235 16,17,18
PCI C onnectors 19,20,21
C C
CNR RISER / DLED 22
AC'9 7 Codec & AUDIO PORT 23,24
A T A 6 6 /100 Connectors 25
Front USB Port 26
Rear USB Port 27
LP C I/O 28
Hardware monitor 29
System ROM 30
Keyboard/Mouse Connectors 31
LPT/COM Port 32
B
Game P ort 33 B
HIP6301 / 6302 34
CPU Ratio / Vcore / LED Setting 35
AMD CPU Thermal Protection 36
MS-5 ACPI POWER 37
Power Mangement 38
PowerOK C ircuit 39
Front Panel 40
Pull-up R esistors 41
BULK / Decoupling 42
A A
Micro Star Restricted Secret
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Block Diagram
AMD Socket 462
D D
FSB
A DDR
AGP 4X /Fast Write
G
C
P
KT333 C
P
5 PCI Slots
R
O
VLINK
Dual ATA
PCI-33 100/133
B B
VT8235
LPC BUS
P IEEE 802.3MAC( MII)
LAN CONN H
Y
IEEE 802.3MAC( MII)
SUPER I/O ROM
C
USB
N
R
AC-LINK
X BUS
A
AC'97 Codec A
Dual USB 1.1 O HCI
/2.0 EHCI 6 Ports
Micro Star Restricted Secret
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GPIO FUNCTION
VT8233 GPIO Function Define
PIN NAME Function define PIN NAME Function define
D D
GPO0 (VSUS33) GPO0 GPI0 GPI0
GPO1/SUSA#(VSUS33) SUSA# GPI1 ATADET0=>Detect IDE1 ATA100/66
GPO2/SUSB#(VSUS33) SUSB# GPI2/EXTSMI# EXTSMI#
GPO3/SUSST1#(VSUS33) SUSST1# GPI3/RING# RING#
GPO4/SUSCLK(VSUS33) SUSCLK GPI4/LID# ATADET1=>Detect IDE2 ATA100/66
GPO5/CPUSTP# CPUSTP# GPI5/BATLOW# Exteranl Pull up to 3VDUAL
GPO6/PCISTP# PCISTP# GPI6/PME# PME#
GPO7/SLP# SLP# GPI7/SMBALRT# Exteranl Pull up to 3VDUAL PCI
GPO8/GPI8/IPBIN0 Exteranl Pull up to VCC3 GPI16/INTRUDER# Exteranl Pull down DEVICES INT# IDSEL REQ#/GNT# CLOCK
GPO9/GPI9/IPBIN1 Exteranl Pull up to VCC3 GPI17/CPUMISS Exteranl Pull up to 3VDUAL INT#A PREQ#0
C PCI SLOT 1 INT#B AD16 PCICLK1 C
INT#C PGNT#0
GPO10/GPI10/IPBRDFR GPI10(PRI_DOWN) GPI18/AOLGP1/THRM# THRM# INT#D
GPO11/GPI11/IPBRDCK GPI19/IORDY Exteranl Pull up to VCC3 INT#B PREQ#1
PCI SLOT 2 INT#C AD17 PCICLK2
INT#D PGNT#1
GPO12/GPI12/IPBOUT0 GPO12 INT#A
DDR Voltage SET1 SET2
GPO13/GPI13/IPBOUT1 GPO13 INT#C PREQ#2
PCI SLOT 3 INT#D AD18 PCICLK3
2.5V 1 1 INT#A PGNT#2
GPO14/GPI14/IPBTDFR GPO14 INT#B
2.6V 0 1
GPO15/GPI15/IPBTDCK GPO15 2.7V 1 0 INT#D PCIREQ#3
PCI SLOT 4 INT#A AD19 PCICLK4
2.8V 0 0 INT#B PCIGNT#3
GPO16/SA16/STRAP CPU FID0 Strapping INT#C
GPO17/SA17/STRAP CPU FID1 Strapping INT#B PCIREQ#4
PCI SLOT 5 INT#C AD21 PCICLK5
INT#D PCIGNT#4
GPO18/SA18/STRAP CPU FID2 Strapping INT#A
B GPO19/SA19/STRAP CPU FID3 Strapping INT#C PCIREQ#5 B
PCI SLOT 6 INT#D
GPO20/GPI20 INT#A AD23 PCIGNT#5 PCICLK6
/ACSDIN2/PCS0#/EI GPO20 INT#B
GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN# GPO21
GPO22/GPI22/IOR# GPO22
GPO23/GPI23/IOW# GPO23
GPO24/GPI24/GPIOA
GPO25/GPI25/GPIOC
GPO26/GPI26/SMBDT2
(VSUS33) SMBDATA2/Slave SMBUS
GPO27/GPI27/SMBCK2
(VSUS33) SMBCLK2/Slave SMBUS
GPO28/GPI28/
APICD0/APICCS#
GPO29/GPI29/
A APICD1/APICACK# A
GPO30/GPI30/GPIOD
M icro Star Restricted Secret
GPO31/GPI31/GPIOE Title Rev
GPIO Spec.
Document Number 100
MS-6593
MICRO-STAR INT'L Last Revision Date:
CO.,LTD. Tuesday, May 14, 2002
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 3 of 44
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SOCKET 462 Part 1
**All CPU interface are 2.5V tolerant**
VCORE
VCC3
CPU1A
SDATA#[0..63] SDATA#0 AA35 AE1 A20M# CPURST# VCORE DBREQ# R17 510
7 SDATA#[0..63] SDATA0 A20M A20M# 16
SDATA#1 W37 AG1 FERR
SDATA#2 W35 SDATA1 FERR AJ3 CPUINIT#
SDATA2 INIT CPUINIT# 16 R38
SDATA#3 Y35 AL1 INTR
SDATA3 INTR INTR 16 C6 4.7K
SDATA#4 U35 AJ1 IGNNE# X_0.1u PLLTEST# R14 510
SDATA4 IGNNE IGNNE# 16 R40
SDATA#5 U33 AN3 NMI
SDATA5 NMI NMI 16 680
SDATA#6 S37 AG3 CPURST# RN3
SDATA#7 S33 SDATA6 RESET AN5 SMI# CPURST# 37 FERR# CPU_TCK 1 2
D SDATA#8 SDATA7 SMI SMI# 16 FERR# 16 D
AA33 AC1 STPCLK# CPU_TMS 3 4
SDATA#9 AE37 SDATA8 STPCLK STPCLK# 16 Q4 CPU_TRST# 5 6
SDATA#10 AC33 SDATA9 AE3 FERR CPU_TDI 7 8
SDATA#11 SDATA10 PWROK K7PWRGD 37
AC37 NPN-MBT3904LT1-S-SOT23
SDATA#12 Y37 SDATA11 510
SDATA#13 AA37 SDATA12 N1 APICCLK_CPU
SDATA#14 SDATA13 PICCLK APICCLK_CPU 6 VCORE
AC35 N3 APICD0#
SDATA#15 SDATA14 PICD0/BYPASSCLK APICD1# APICD0# 16
S35 N5
SDATA#16 SDATA15 PICD1/BYPASSCLK APICD1# 16
Q37
SDATA#17 Q35 SDATA16 AG13 COREFB#
SDATA#18 SDATA17 COREFB- COREFB# 34
N37 AG11 COREFB R55
SDATA#19 SDATA18 COREFB+ COREFB 34
J33 100
SDATA#20 G33 SDATA19 AN17 CPUCLK_R for test only 0.6 * VCORE
SDATA#21 G37 SDATA20 CLKIN AL17 CPUCLK#_R VCC2_5
SDATA#22 E37 SDATA21 CLKIN VREF_SYS
SDATA#23 G35 SDATA22 AN19
Pull to 2.5V
SDATA#24 Q33 SDATA23 RSTCLK AL19
SDATA#25 N33 SDATA24 RSTCLK APICD0# R50 330
SDATA25 C40 C39 R54
SDATA#26 L33 AL21 CLKOUT APICD1# R51 330 0.01u 0.1u
SDATA26 K7CLKOUT 100
SDATA#27 N35 AN21 CLKOUT#
SDATA#28 L37 SDATA27 K7CLKOUT
SDATA#29 J37 SDATA28 VCORE
SDATA29 C34
SDATA#30 A37 AJ13 X_39p
SDATA#31 E35 SDATA30 ANALOG
SDATA#32 E31 SDATA31 AA5 VREFMODE
SDATA#33 E29 SDATA32 SYSVREFMODE W5 VREF_SYS
SDATA#34 A27 SDATA33 VREF_SYS VCORE
SDATA34 R64 R66 6 CPUCLK
SDATA#35 A25 AC5 ZN 100 100
SDATA#36 E21 SDATA35 ZN AE5 ZP C66
C SDATA#37 C23 SDATA36 ZP CPUCLK_R R72 60.4 C
SDATA#38 C27 SDATA37 AJ25 PLLBP#
SDATA#39 A23 SDATA38 PLLBYPASS AN15 680p
SDATA#40 A35 SDATA39 PLLBYPASSCLK AL15
SDATA#41 C35 SDATA40 PLLBYPASSCLK
SDATA41 R73
SDATA#42 C33 AN13 PLLMON1 VCORE
SDATA42 PLLMON1 301
SDATA#43 C31 AL13 PLLMON2
SDATA#44 A29 SDATA43 PLLMON2 AC3 PLLTEST#
SDATA44 PLLTEST R63 R65
SDATA#45 C29 VCORE C71
SDATA45 100 100 C32
SDATA#46 E23 CPUCLK#_R R74 60.4
SDATA#47 C25 SDATA46 S1 SCANCLK1 X_2.2u
SDATA#48 E17 SDATA47 SCANCLK1 S5 SCANCLK2 COREFB R48 10K 680p
SDATA#49 E13 SDATA48 SCANCLK2 S3 SINTVAL
close Socket 462
SDATA#50 SDATA49 SCANINTEVAL 6 CPUCLK#
E11 Q5 SSHIFTEN C36
SDATA#51 C15 SDATA50 SCANSHIFTEN
SDATA#52 E9 SDATA51 AA1 X_10u_0805
SDATA#53 A13 SDATA52 DBRDY AA3 DBREQ# COREFB# R52 10K VCORE
SDATA#54 C9 SDATA53 DBREQ AL3 FLUSH#
SDATA#55 A9 SDATA54 FLUSH
SDATA55 C35
SDATA#56 C21 Q1 CPU_TCK
SDATA#57 A21 SDATA56 TCK U1 CPU_TDI X_1u
SDATA57 TDI R15
SDATA#58 E19 U5 for internal
SDATA#59 C19 SDATA58 TDO Q3 CPU_TMS X_1K
SDATA#60 C17 SDATA59 TMS U3 CPU_TRST#
VREFSYS
SDATA#61 A11 SDATA60 TRST VREFMODE
SDATA#62 A17 SDATA61
SDATA#63 A15 SDATA62 L1 VID0 VCORE
SDATA63 VID0 VID0 35
L3 VID1 RN8 R13
VID1 VID1 35
L5 VID2 CPUINIT# 1 2 270
VID2 VID2 35
DICLK#[0..3] DICLK#0 W33 L7 VID3 IGNNE# 3 4
B 7 DICLK#[0..3] DICLK#1 SDATAINCLK0 VID3 VID3 35 B
J35 J7 VID4 CPURST# 5 6
DICLK#2 SDATAINCLK1 VID4 VID4 35
E27 A20M# 7 8
DICLK#3 E15 SDATAINCLK2
SDATAINCLK3 W1 FID0 680
DIVAL# AN33 FID0 W3 FID1 FID0 35 VREFMODE=Low=No voltage scaling
7 DIVAL# SDATAINVAL FID1 FID1 35
Y1 FID2 RN11
DOCLK#0 FID2 FID2 35
7 DOCLK#[0..3] DOCLK#[0..3] AE35 Y3 FID3 STPCLK# 1 2
DOCLK#1 SDATAOUTCLK0 FID3 FID3 35 VCORE
C37 NMI 3 4
DOCLK#2 A33 SDATAOUTCLK1 SMI# 5 6
DOCLK#3 C11 SDATAOUTCLK2 U37 INTR 7 8 ZN R12 40.2
SDATAOUTCLK3 SCHECK0 Y33
DOVAL# AL31 SCHECK1 L35 680 ZP R16 56.2
SDTATOUTVAL SCHECK2 E33
AIN#0 AJ29 SCHECK3 E25 FLUSH# R39 680
AIN#1 AL29 SADDIN0 SCHECK4 A31 PLLBP# R84 680
SADDIN1 SCHECK5
m atch the transmission line
7 AIN#[2..14] AIN#[2..14] AIN#2 AG33 C13 Push-pull compensation circuit
AIN#3 AJ37 SADDIN2 SCHECK6 A19 PLLMON1 R53 56
AIN#4 AL35 SADDIN3 SCHECK7 PLLMON2 R57 56
AIN#5 AE33 SADDIN4 J1
AIN#6 AJ35 SADDIN5 SADDOUT0 J3 VCORE
AIN#7 AG37 SADDIN6 SADDOUT1 C7 AOUT#2 AOUT#[2..14] RN28
SADDIN7 SADDOUT2 AOUT#[2..14] 7
AIN#8 AL33 A7 AOUT#3 1 2
AIN#9 AN37 SADDIN8 SADDOUT3 E5 AOUT#4 RN32 CLKOUT 3 4
AIN#10 AL37 SADDIN9 SADDOUT4 A5 AOUT#5 AIN#0 1 2 CLKOUT# 5 6
AIN#11 AG35 SADDIN10 SADDOUT5 E7 AOUT#6 AIN#1 3 4 7 8
AIN#12 AN29 SADDIN11 SADDOUT6 C1 AOUT#7 DOVAL# 5 6
AIN#13 AN35 SADDIN12 SADDOUT7 C5 AOUT#8 FILVAL# 7 8 100
AIN#14 AN31 SADDIN13 SADDOUT8 C3 AOUT#9
SADDIN14 SADDOUT9 G1 AOUT#10 270
A AJ33 SADDOUT10 E1 AOUT#11
* Trace lengths of CLKOUT A
7 AICLK# SADDINCLK SADDOUT11 A3 AOUT#12 and -CLKOUT are between
SADDOUT12
7 CFWDRST
CFWDRST AJ21
CLKFWDRST SADDOUT13
G5 AOUT#13 2" and 3"
CONNECT AL23 G3 AOUT#14
7 CONNECT CONNECT SADDOUT14
7 PROCDRY
PROCDRY
FILVAL#
AN23
AJ31 PROCRDY E3 RN4
M icro Star Restricted Secret
SFILLVAL SADDOUTCLK AOCLK# 7
SSHIFTEN 1 2 Title Rev
PGA-D462 SCANCLK1 3 4 SOCKET 462 Part 1
SINTVAL 5 6 Document Number 100
SCANCLK2 7 8 MS-6593
MICRO-STAR INT'L Last Revision Date:
10K CO.,LTD. Monday, June 17, 2002
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 4 of 44
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A
B
C
D
5
5
AK8
Y7
K8
N7
H8
H6
H32
H30
H28
H10
G9
G17
G25
AH30
AD30
AN7
AJ7
F30
AJ9
AH8
AD8
AG29
AG15
F8
AG7
AL7
K30
AL9
AF32
AF30
AF28
AF10
AM8
AF8
AF6
H14 H12
H18 VSS1 VCC_CORE1 H16
KEY8
KEY6
KEY4
VCC_CORE2
KEY18
KEY16
KEY14
KEY12
KEY10
H22 VSS2 H20
H26 VSS3 VCC_CORE3 H24
M30 VSS4 VCC_CORE4 M8
VCC_SRAM9
VCC_SRAM8
VCC_SRAM7
VCC_SRAM6
VCC_SRAM5
VCC_SRAM4
VCC_SRAM3
VCC_SRAM2