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5 4 3 2 1
PCB STACK UP
LAYER 1 : TOP
ZM2 BlOCK DIAGRAM
CLOCK GEN
LAYER 2 : SGND
SLG8SP513VTR 14
Page
DB LAYER 3 : IN1
D D
QP/N LAYER 4 : IN2 Intel
32ZM2PB0000
LAYER 5 : SVCC PineView-M N470 VGA
33ZM1MA0010 CRT
34ZM2TB0000 Page 16
LAYER 6 : BOT 559 Micro-BGA
35ZM2LB0000
3BZM2BB0000 FAN & THERMAL
DDRII-SODIMM CHA 22mm X 22mm LVDS
10.1" LCD EMC1423 Page 26
Page 12 Page 15
USB&PCIE PORT 667 MHZ Page 3,4,5,6
USB Port# Destination
0 Right top
1 Right bottom Note:
2 Left side Half-size Mini-card for WLAN
3 Bluetooth
DMI x2
C
4 Camera WLAN Page 20 Note: C
5 Touch Screen Full size Mini-card for WWAN
6 Mini-WLAN PCI-E
7 Mini-WWAN SIM Card
SATA Intel USB2.0 WWANPage 21 Page 21
PCI-E Port# Destination
SATA - HDD NM10
PCIE-1 Mini-WWAN Page 22
PCIE-2 Mini-WLAN PCI-E LAN
PCIE-3 Card reader BCM57760 RJ-45 Page 25
PCIE-4 LAN
PCI-E
SD/SDHC/MMC card reader
Page 24,25
(RTS5208) Page 19 360 BGA
17mm X 17mm
DMic
Power Page 28
+3.3V_ALW/+5V_ALW(MAX17020) USB CNN x3 Page 27
PAGE 36
USB 2.0 MIC-In Jack
B
CCD Page 15 Audio Codec Page 28
B
Bluetooth Page 20 HD Audio ALC269
+1.8VSUS(RT8207)/ HP Jack Page 28
+VTT_MEM PAGE 35 Page 7,8,9,10,11
Page 28 INT Speaker
+VCC_CORE (MAX8796) LPC 1W x2 Page 28
PAGE 33 SPI ROM
Page 18
EC
CHARGER (MAX8731A) MEC5035
PAGE 32 17X8 ECE1077 Keyboard
Page 17 PG 23 PG 23
A +VCC_GFX_CORE(RT8209A) A
PAGE 31 PS/2
Touchpad QUANTA
+VCCP(RT8209A)/
Connector
Title
COMPUTER
+VCC1.5(RT9018B) PG 23 BLOCK DIAGRAM
PAGE 34
Size Document Number Rev
ZM2 D
Date: Monday, March 01, 2010 Sheet 1 of 43
5 4 3 2 1
5 4 3 2 1
Table of Contents Power States
CONTROL
PAGE DESCRIPTION POWER PLANE VOLTAGE PAGE DESCRIPTION ACTIVE IN
SIGNAL
1 Schematic Block Diagram
2 Front Page +PWR_SRC 10V~+19V 15,18,,32,33,35,36,40 MAIN POWER S0~S5
3-6 Prineview
+VCCRTC +3.0V~+3.3V 10,11,17,18 RTC S0~S5
7-11 TGP
D D
12 DDRII SO-DIMM(200P) +3.3V_ALW +3.3V 17,18,24,25,29,31,32,34,35,36,37,38,40 8051 POWER ALWON S0~S5
13 XDP Debug Port
+5V_ALW +5V 23,24,29,34,35,36,37,38 LCD/CHARGE POWER ALWON S0~S5
14 Clock Generator
15 LCD Conn. ,CCD,TouchScr +15V_ALW +15V 15,24,36,37 LARGE POWER +5V_ALW S0~S5
16 CRT Conn
+3.3V_LAN +3.3V 24,25,40 LAN POWER LAN_PWR_ON
17 SIO(MEC_5035)
18 FLASH/RTC +5V_SUS +5V 24,27,29,33,37,40 SLP_S5# CTRLD POWER SUS_ON
19 Card Reader-RTS5208
+3.3V_SUS +3.3V 15,24,29,30,33,34,37 SLP_S5# CTRLD POWER SUS_ON
20 Mini Card(WLAN)
21 MINI-WWAN +1.8VSUS +1.8V 4,5,12,13,34,35,37 SODIMM POWER SUS_ON
22 SATA (HDD)
+VTT_MEM +0.9V 12,13,35,37 SODIMM POWER RUN_ON
23 KB/TP
24 LAN POWER +VCC1.8 +1.8V 5,37 RUN_ON
25 LAN(BCM57760)
+VCC5 +5V 11,15,16,22,23,26,28,29,37,40 SLP_S3# CTRLD POWER RUN_ON
26 FAN & Thermal
C C
27 USB +VCC3 +3.3V 3,5,6,8,9,10,11,12,13,14,15,16,17,19,20, SLP_S3# CTRLD POWER RUN_ON
28 Audio CODEC(ALC269) 21,22,24,25,26,28,29,33,37,40
29 LED &SWITCH
30 System Reset Circuit +VCC1.5 +1.5V 5,7,11,20,21,34,37,40 CALISTOGA/ICH8 POWER RUN_ON
31 VGA Power
+VCCP +1.05V 3,5,8,11,34,40 CPU/CALISTOGA/ICH8 POWER RUN_ON
32 Charger (MAX8731A)
33 CPU(MAX8796) +VCC_CORE +0.7V~+1.77V 5,33,40 CPU CORE POWER IMVP_VR_ON
34 1.05VCCP & VCC1.5 LCDVCC_TST_EN
+LCDVCC +3.3V 15 LCD Power & ENVDD
35 1.8VSUS & 0.9VTT (TPS51116)
36 3.3V/5V_ALWPower +VCHGR +10V~+17V 32,38 MAIN BATTERY CHG_PBATT
37 RUN Power Switch
38 DCIN&Batt
39 PAD& SCREW
40 EMI CAP
41 SMBUS BLOCK
B B
42 Power Block Dianram
43 Port Mapping GND PLANE PAGE DESCRIPTION
GNDA_CHG
35
GND_1.05V
36
AGND_DC/DC
38
GND POWER
33
AGND_DDR
PM6686TR
GND ALL
A A
QUANTA
Title
COMPUTER
FRONTPAGE
Size Document Number Rev
ZM2 D
Date: Monday, March 01, 2010 Sheet 2 of 43
5 4 3 2 1
5 4 3 2 1
PINEVIEW_M
U8002D
REV = 1.1
15 INT_TXLCLKN U25 LVD_A_CLKM SMI_B E7 H_SMI# 8 PINEVIEW_M
15 INT_TXLCLKP U26 LVD_A_CLKP A20M_B H7 H_A20M# 8
15 INT_TXLOUTN0 R23 H6 U8002A
LVD_A_DATAM_0 FERR_B H_FERR# 8
15 INT_TXLOUTP0 R24 LVD_A_DATAP_0 LINT00 F10 H_INTR 8
ICH
15 INT_TXLOUTN1 N26 F11 REV = 1.1
LVD_A_DATAM_1 LINT10 H_NMI 8
15 INT_TXLOUTP1 N27 LVD_A_DATAP_1 IGNNE_B E5 H_IGNNE# 8 7 DMI_TXP0 F3 DMI_RXP_0 DMI_TXP_0 G2 DMI_RXP0 7
15 INT_TXLOUTN2 R26 F8 H_STPCLK# 8 7 DMI_TXN0 F2 G1
DMI
LVD_A_DATAM_2 STPCLK_B DMI_RXN_0 DMI_TXN_0 DMI_RXN0 7
15 INT_TXLOUTP2 R27 LVD_A_DATAP_2 7 DMI_TXP1 H4 DMI_RXP_1 DMI_TXP_1 H3 DMI_RXP1 7
7 DMI_TXN1 G3 DMI_RXN_1 DMI_TXN_1 J2 DMI_RXN1 7
D D
DPRSTP_B G6 ICH_DPRSTP# 10,33
R8085 2.37K/F_4 LIBG R22 G10
LVD_IBG DPSLP_B H_DPSLP# 10
LVDS
T45 J28 G8 H_INIT# 8 DPRSTP# daisy-chain
LVD_VBG INIT_B
1 2 N22 LVD_VREFH PRDY_B E11 XDP_PRDY# 13 TigerPoint--> MVP-->PineView
R318 100K N23 LVD_VREFL PREQ_B F15 H_PREQ# H_PREQ# 13
L27 N7 L10 EXP_COMP
17 L_BKLT_EN LBKLT_EN 14 CLK_PCIE_DMIN EXP_CLKINN EXP_RCOMPO
15 L_BKLTCTL L26 LBKLT_CTL 14 CLK_PCIE_DMIP N6 EXP_CLKINP EXP_ICOMPI L9
LCTLA_CLK L23 E13 H_THERMTRIP# H_THERMTRIP# 8 L8 EXP_RBIAS
LCTLB_DATA LCTLA_CLK THERMTRIP_B EXP_RBIAS
K25 LCTLB_DATA R10 RSVD
LVDS_CLK K23 THERMTRIP#/FERR# OD PU on tiger point side R9 N11
15 LVDS_CLK LDDC_CLK RSVD RSVD_TP
LVDS_DATA K24 mini 1.5:1 ratio is ok if GND reference all the way N10 P11
15 LVDS_DATA LDDC_DATA RSVD RSVD_TP
15 L_VDD_EN H26 LVDD_EN N9 RSVD
1
PROCHOT_B C18 H_PROCHOT# R395 68_4 +VCCP R8088 R8082
R293 W1 750/F_4 49.9/F_4
CPUPW RGOOD H_PWRGD 10,13
100K K2 RSVD_K2 RSVD_K3 K3
CPUPWRGOOD 1K series-resistor if ITP/XDP implemented J1 L2
RSVD_J1 RSVD_L2
M4 M2
2
H_GTLREF RSVD_M4 RSVD_M2
GTLREF A13 L3 RSVD_L3 RSVD_N2 N2
1 OF 6
H27
Pull-down must be
VSS
Pineview
placed within 500
RSVD L6 T68
mils from
E17
13 OBSDATA_3 G11
RSVD T67 Pineview-M pins
BPM_1B_0
13 OBSDATA_2 E15 BPM_1B_1 BCLKN H10 HCLK_CPUN 14
G13 J10 +VCCP
13 OBSDATA_1 BPM_1B_2 BCLKP HCLK_CPUP 14
13 OBSDATA_0 F13 BPM_1B_3
K5 CPU_BSEL0 CPU_BSEL0 R8081 470/J_4
CPU
BSEL_0 CPU_BSEL0 14
B18 H5 CPU_BSEL1 CPU_BSEL1 R8079 470/J_4
BPM_2_0#/RSVD BSEL_1 CPU_BSEL1 14
B20 K6 CPU_BSEL2 CPU_BSEL2 R8080 470/J_4
BPM_2_1#/RSVD BSEL_2 CPU_BSEL2 14
C C20 BPM_2_2#/RSVD C
B21 BPM_2_3#/RSVD VID_0 H30 CPU_VID0 33
H29 +VCCP
VID_1 CPU_VID1 33
VID_2 H28 CPU_VID2 33
VID_3 G30 CPU_VID3 33
T46 G5 RSVD VID_4 G29 CPU_VID4 33
XDP_TDI D14 F29 R8010
13 XDP_TDI TDI VID_5 CPU_VID5 33
D13 E29 1K/F_4
13 XDP_TDO TDO VID_6 CPU_VID6 33
XDP_TCK B14
13 XDP_TCK TCK +VCCP
XDP_TMS C14 L7
13 XDP_TMS TMS RSVD
XDP_TRST# C16 D20 H_GTLREF
13 XDP_TRST# TRST_B RSVD
RSVD H13 T66
RSVD D18 T65
D30 R8083
26 H_THERMDA THRMDA_1
E30 K9 976/F_4 R8005 C8008 C8007
26 H_THERMDC THRMDC_1 RSVD_TP T64
D19 2K/F_4 1U/6.3V_4 *220P/50V_4_NC
RSVD_TP T55
K7 H_EXBGREF
EXTBGREF
THERMDA THERMDC routed on same layer
Width/Space :10/10 mil
C8070 R8084 voltage divider within 0.5" of processor pin
1U/6.3V_4 3.32K/F_4
T47 C30 RSVD_C30
D31 4 OF 6
T48 RSVD_D31
Pineview debug feature.voltage divider within 0.5" of processor pin
? CPU THERMTRIP
B
+VCC3 B
PM_THRMTRIP# 36
+VCC3
LCTLA_CLK R8087 2.2K/J_4
LCTLB_DATA R8086 2.2K/J_4 R199
3
LVDS_CLK R8013 2.2K/J_4 *10M_NC Q27
LVDS_DATA R8012 2.2K/J_4 2 *2N7002W-7-F_NC
3
1
H_THERMTRIP# 2
1
C275
Q12 *0.1U_NC
1
2
*MMST3904-7-F_NC 16
XDP PU
+VCCP
XDP_TMS R8072 51/J_4
XDP_TDI R8076 51/J_4 10/26 Reserve CPU thermtrip Function
H_PREQ# R8077 51/J_4
XDP_TCK R8004 51/J_4
XDP_TRST# R8073 51/J_4
XDP_BPM#5 : Length<200mil
A A
QUANTA
Title
COMPUTER
PINEVIEW 1/4(DMI,LVDS)
Size Document Number Rev
ZM2 D
Date: Wednesday, March 10, 2010 Sheet 3 of 43
5 4 3 2 1
5 4 3 2 1
PINEVIEW_M
U8002B
REV = 1.1
12 M_A_A[14..0]
M_A_A0 AH19 AD3 M_A_DQS0
M_A_A1 DDR_A_MA_0 DDR_A_DQS_0 M_A_DQS#0
AJ18 DDR_A_MA_1 DDR_A_DQSB_0 AD2
M_A_A2 AK18 AD4 M_A_DM0
M_A_A3 DDR_A_MA_2 DDR_A_DM_0
AK16 DDR_A_MA_3
M_A_A4 AJ14 AC4 M_A_DQ0
M_A_A5 DDR_A_MA_4 DDR_A_DQ_0 M_A_DQ1
AH14 DDR_A_MA_5 DDR_A_DQ_1 AC1
M_A_A6 AK14 AF4 M_A_DQ2
M_A_A7 DDR_A_MA_6 DDR_A_DQ_2 M_A_DQ3
D AJ12 DDR_A_MA_7 DDR_A_DQ_3 AG2 D
M_A_A8 AH13 AB2 M_A_DQ4
M_A_A9 DDR_A_MA_8 DDR_A_DQ_4 M_A_DQ5
AK12 DDR_A_MA_9 DDR_A_DQ_5 AB3
M_A_A10 AK20 AE2 M_A_DQ6
DDR_A_MA_10 DDR_A_DQ_6 M_A_DQ[63..0] 12
M_A_A11 AH12 AE3 M_A_DQ7
M_A_A12 DDR_A_MA_11 DDR_A_DQ_7
AJ11 DDR_A_MA_12
M_A_A13 AJ24 AB8 M_A_DQS1
M_A_A14 DDR_A_MA_13 DDR_A_DQS_1 M_A_DQS#1
AJ10 DDR_A_MA_14 DDR_A_DQSB_1 AD7 M_A_DM[7..0] 12
AA9 M_A_DM1
DDR_A_DM_1
M_A_W E# AK22 AB6 M_A_DQ8
12 M_A_W E# DDR_A_WEB DDR_A_DQ_8 M_A_DQS[7..0] 12
M_A_CAS# AJ22 AB7 M_A_DQ9
12 M_A_CAS# DDR_A_CASB DDR_A_DQ_9 M_A_DQS#[7..0] 12
M_A_RAS# AK21 AE5 M_A_DQ10
12 M_A_RAS# DDR_A_RASB DDR_A_DQ_10
AG5 M_A_DQ11
M_A_BS0 DDR_A_DQ_11 M_A_DQ12
12 M_A_BS0 AJ20 DDR_A_BS_0 DDR_A_DQ_12 AA5
M_A_BS1 AH20 AB5 M_A_DQ13
12 M_A_BS1 DDR_A_BS_1 DDR_A_DQ_13 +VTT_MEM
M_A_BS2 AK11 AB9 M_A_DQ14
12 M_A_BS2 DDR_A_BS_2 DDR_A_DQ_14
AD6 M_A_DQ15
DDR_A_DQ_15
AD8 M_A_DQS2 M_A_BS1 RN8003 1 2 47X4
M_CS#0 DDR_A_DQS_2 M_A_DQS#2 M_A_A0
12 M_CS#0 AH22 DDR_A_CSB_0 DDR_A_DQSB_2 AD10 3 4
M_CS#1 AK25 AE8 M_A_DM2 M_A_A2 5 6
12 M_CS#1 DDR_A_CSB_1 DDR_A_DM_2
AJ21 M_A_A4 7 8
DDR_A_CSB_2 M_A_DQ16
AJ25 DDR_A_CSB_3 DDR_A_DQ_16 AG8
AG7 M_A_DQ17
M_CKE0 DDR_A_DQ_17 M_A_DQ18 M_CKE0 RN8005 1
12 M_CKE0 AH10 DDR_A_CKE_0 DDR_A_DQ_18 AF10 2 47X4
M_CKE1 AH9 AG11 M_A_DQ19 M_A_A14 3 4
12 M_CKE1 DDR_A_CKE_1 DDR_A_DQ_19
AK10 AF7 M_A_DQ20 M_CKE1 5 6
DDR_A_CKE_2 DDR_A_DQ_20 M_A_DQ21
AJ8 DDR_A_CKE_3 DDR_A_DQ_21 AF8 7 8
C AD11 M_A_DQ22 C
M_ODT0 DDR_A_DQ_22 M_A_DQ23
12 M_ODT0 AK24 DDR_A_ODT_0 DDR_A_DQ_23 AE10
M_ODT1 AH26 M_A_BS2 RN8004 1 2 47X4
12 M_ODT1 DDR_A_ODT_1
AH24 AK5 M_A_DQS3 M_A_A12 3 4
DDR_A_ODT_2 DDR_A_DQS_3 M_A_DQS#3 M