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2
Compal Confidential 2

QIWG5/QIWG6 DIS M/B Schematics Document
Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
nVIDIA N13X

2012-02-01
3 3

LA-7981P
REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7981P
Date: Wednesday, February 15, 2012 Sheet 1 of 60
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A B C D E

Compal confidential ZZZ ZZZ1 ZZZ2 ZZZ3 ZZZ4 QIWG5
File Name : QIWG5/QIWG6 LA7981 LS7981P CardReader/B
G5_DAZ@ G5_DA@ G5_DA@ G5_DA@ G5_DA@
LS7982P USB/B
DAZ_PCB
DAZ0N100101
DA_PCB
DA80000Q010
DA_PCB
DA400016P10
DA_PCB
DA400016Q10
DA_PCB
DA400018T10
LS7983P PWR/B
Page23-32
ZZZ5 ZZZ7 ZZZ6 ZZZ8 ZZZ9 ZZZ10 ZZZ11

1
nVIDIA N13M-GE LA7981 QIWG6 1

nVIDIA N13P-GL
G6_DAZ@ G6_DA@ G6_DA@ G6_DA@ G6_DA@ G6_DA@ G6_DA@ LS7981P CardReader/B
DAZ_PCB DA_PCB DA_PCB DA_PCB DA_PCB DA_PCB DA_PCB
Intel DAZ0N200101 DA80000Q010 DA400016P10 DA400016Q10 DA400016R10 DA400016S10 DA400018T10 LS7982P USB/B
LS7983P PWR/B
Ivy Bridge LS7984P LED/B
VRAM 128*16 PCI-E x16 DDR3 SO-DIMM *2 LS7985P ODD/B
DDR3*8 Socket-rPGA988B BANK 0, 1, 2, 3 Page12-13
37.5mm*37.5mm
Dual Channel Up to 8GB
HDMI Page35 Page5-11DDR3 1066MHz(1.5V)
DDR3 1333MHz(1.5V)
Connector DDR3 1600MHz(1.5V)
100MHz
Page34 2.7GT/s FDI *8 DMI *4
CRT
2 Connector Intel Audio Codec 2 channel speaker
Page41
2

AZALIA Conexant
LVDS Page33 Panther Point CX20671-21Z
Int. MIC x1 Page41
Connector HM75 / HM76
Page41
Audio Jacks Page43
FCBGA 989
USB3.0 *2(Left) 25mm*25mm USB2.0 *14
Camera Conn.
Page33
PCI-E x1 *6
Option Page45
SATA *6 BlueTooth Conn.
Page40
USB3.0 Page14-22
Renesas
SPIROM Mini Card Slot *1
Page36
uPD720202
BIOS Page14
3 LPC BUS Card Reader Page43 3

Arthros
Page42 Reltek
AR8161(GLAN) EC RTS5178 for SDR50
SDXC/MMC
AR8162(10/100) ENE KB9012
Page37
USB2.0 *2(Right)
Page38 Page 43;44
RJ-45
Connector Touch Pad Int. KBD USB2.0 *2(Left)
Page43 Page45
Page43
PCI Express PCI-E(WLAN) SATA HDD Page40
Mini Card Slot *1 Thermal Sensor (Port 0/Port 1 support SATA3)
EMC1403 Page39
SATA ODD
WLAN Page36 Page40
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7981P
Date: Wednesday, February 15, 2012 Sheet 2 of 60
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A B C D E

SIGNAL
Voltage Rails BOARD ID Table STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Board ID PCB Revision Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+5VS
0 0.1 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+3VS
1
power 2 S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane +1.5VS
+V1.05S_VCCP
3 S4 (Suspend to Disk)
1
LOW LOW LOW HIGH ON OFF OFF OFF 1

+5VALW +1.5V +VCC_CORE
4
5 S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +VGA_CORE
+3VALW +VCC_GFXCORE_AXG
6
+1.8VS
7 Vcc 3.3V +/- 5% Board ID / SKU ID Table for AD channel
State +0.75VS
Ra/Rc/Re 100K +/- 5%
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max Porject Phase
+1.05VS
G-series
0 0 0 V 0 V 0 V MP
G-series
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V PVT
G-series
2 18K +/- 5% 0.436 V 0.503 V 0.538 V DVT
G-series
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
Y-series
4 56K +/- 5% 1.036 V 1.185 V 1.264 V EVT
Y-series
S0
5 100K +/- 5% 1.453 V 1.650 V 1.759 V DVT
O O O O 6 200K +/- 5% 1.935 V 2.200 V 2.341 V Y-series
PVT
Y-series
7 NC 2.500 V 3.300 V 3.300 V MP
USB Port Table
S3
O O O X 3 External
2 USB 2.0 Port BOM Structure Table 2
USB Port
S5 S4/AC BTO Item BOM Structure
O O X X 0
UHCI0
1 USB Port (Right Side CR-BD)
S5 S4/ Battery only
O X X X 2 USB Port (Left Side) USB3.0
UHCI1 GPU:N13P-GL N13P@
S5 S4/AC & Battery
3 USB Port (Left Side) USB3.0
X X X X EHCI1 GPU:N13M-GE N13M@
don't exist USB3.0
4
UHCI2 HDMI HDMI@
Address 5 Camera
EC SM Bus1 address EC SM Bus2 address Interna-Intel-USB3.0 IU3@
6
UHCI3 External-NEC-USB3.0 EU3@
7
Device Device Address Blue Tooth BT@
Smart Battery 0001 011X b Thermal Sensor F75303M 1001_101xb
8
UHCI4 Connector ME@
9 USB/B (Right Side USB-BD)
45 LEVEL 45@
10 Mini Card(WLAN)
PCH SM Bus address EHCI2 UHCI5 10/100 LAN 8162@
11 Card Reader
GIGA LAN GIGA@
12
Device Address UHCI6 LAN LDO Mode LDO@
DDR DIMM0 1001 000Xb
13 Blue Tooth
LAN Switch mode SWR@
DDR DIMM2 1001 010Xb Cameara CMOS@
3 3

For QIWG5 (14") 14@
NV-GPU SM Bus address For QIWG6 (15") 15@
Unpop @
Device Address G5/G6/G9(Low/Mid END) nonBBH@
Internal thermal sensor 1001 111Xb (0x9E)
G9 High-END BBH@
G9 G9 @
G5/G6/G9(Low/Mid END) 15_nonBBH@

SMBUS Control Table
Thermal
WLAN Sensor
SOURCE VGA BATT KB9012 SODIMM WWAN PCH

SMB_EC_CK1
SMB_EC_DA1
KB9012 X V
+3VALW
X X X X X
+3VALW
SMB_EC_CK2
SMB_EC_DA2
KB9012 X X X X X X V
+3VS
+3VALW
SMBCLK
X X X V V X X
4 4

PCH
SMBDATA +3VALW +3VS +3VS
SML0CLK
SML0DATA
PCH
+3VALW
X X X X X X X
Security Classification Compal Secret Data Compal Electronics, Inc.
SML1CLK
SML1DATA
PCH
+3VALW +3VS
V X V
+3VS
X X V
+3VS
X Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7981P
Date: Wednesday, February 15, 2012 Sheet 3 of 60
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5 4 3 2 1

Hot plug detect for IFP link C

VGA and GDDR3 Voltage Rails (N13x GPIO) Performance Mode P0 TDP at Tj = 102 C* (GDDR3)
FBVDDQ PCI Express I/O and I/O and Other
GPIO I/O ACTIVE Function Description GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.8V) (1.05V) (3.3V)
GPIO0 OUT - GPU VID4 Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)

D D
GPIO1 OUT - GPU VID3 N13P-GL
64bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
1GB
GPIO2 OUT H Panel Back-Light brightness(PWM capable) GDDR3

GPIO3 OUT H Panel Power Enable
Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
GPIO4 OUT H Panel Back-Light On/Off (PWM)
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
GPIO5 OUT - GPU VID1 ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
GPIO6 OUT - GPU VID2
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
GPIO7 OUT N/A STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
GPIO8 I/O - Thermal Catastrophic Over Temperature
STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO9 OUT - Thermal Alert STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
CHANGE_GEN3
GPIO10 OUT - Memory VREF Control

GPIO11 OUT - GPU VID0 Device ID
C C
N13P-GL
GPIO12 IN AC Power Detect Input (10K pull low) (28nm) ??

GPIO13 OUT - GPU VID5 N13M-GE
(28nm) ???
GPIO14 OUT N/A

GPIO15 IN Hot plug detect for IFP link C
GPU FB Memory (GDDR3) ROM_SO ROM_SCLK ROM_SI STRAP2 STRAP1 STRAP0
GPIO16 OUT N/A
Samsung K4G10325FG-HC04
GPIO17 IN N/A 2500MHz
32Mx32 PD 10K PD 15K PD 20K PU 20K PD 35K PU 45K
GPIO18 IN Hot Plug Detect for IFPE
Hynix H5GQ1H24BFR-T2C
GPIO19 IN N/A 2500MHz
N13P-GL 32Mx32 PD 10K PD 15K PD 15K PU 20K PD 35K PU 45K
N13M-GE
Samsung K4G20325FG-HC04
2500MHz
64Mx32 PD 10K PD 15K PD 20K PU 20K PD 35K PU 45K
B
+3VS_VGA B

Hynix H5GQ2H24MFR-T2C
+VGA_CORE 2500MHz
64Mx32 PD 10K PD 15K PD 20K PU 20K PD 35K PU 45K
tNVVDD >0
+1.5VS_VGA
X76
tFBVDDQ >0

+1.05VS_VGA
tPEX_VDD >0

1. all power rail ramp up time should be larger than 40us

2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

A A

Tpower-off <10ms

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
1.all GPU power rails should be turned off within 10ms
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7981P
Date: Tuesday, February 14, 2012 Sheet 4 of 60
5 4 3 2 1
5 4 3 2 1

PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
+V1.05S_VCCP impedance = 43 mohms
PEG_ICOMPO signals should be routed with -

1
max length = 500 mils
R1
D
24.9_0402_1% - typical impedance = 14.5 mohms D

JCPU1A

2
J22 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO J21
<16> DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22