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Data Sheet
28-Pin, 8-Bit CMOS FLASH
Microcontroller with 10-Bit A/D
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PIC16F872 Data Sheet
28-Pin, 8-Bit CMOS FLASH Microcontroller with 10-Bit A/D
2002 Microchip Technology Inc.
DS30221B
Note the following details of the code protection feature on PICmicro® MCUs. · · · The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product.
· · ·
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microID, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Term Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
DS30221B - page ii
2002 Microchip Technology Inc.
M
PIC16F872
Pin Diagram
DIP, SOIC, SSOP
28-Pin, 8-Bit CMOS FLASH Microcontroller with 10-bit A/D
High Performance RISC CPU:
· Only 35 single word instructions to learn · All single cycle instructions except for program branches, which are two-cycle · Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle · 2K x 14 words of FLASH Program Memory · 128 bytes of Data Memory (RAM) · 64 bytes of EEPROM Data Memory · Pinout compatible to the PIC16C72A · Interrupt capability (up to 10 sources) · Eight level deep hardware stack · Direct, Indirect and Relative Addressing modes
Peripheral Features:
· High Sink/Source Current: 25 mA · Timer0: 8-bit timer/counter with 8-bit prescaler · Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP via external crystal/clock · Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler · One Capture, Compare, PWM module - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit · 10-bit, 5-channel Analog-to-Digital converter (A/D) · Synchronous Serial Port (SSP) with SPI (Master mode) and I2C (Master/Slave) · Brown-out detection circuitry for Brown-out Reset (BOR)
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA
Special Microcontroller Features:
· Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) · Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation · Programmable code protection · Power saving SLEEP mode · Selectable oscillator options · In-Circuit Serial Programming (ICSP) via two pins · Single 5V In-Circuit Serial Programming capability · In-Circuit Debugging via two pins · Processor read/write access to program memory
CMOS Technology:
· Low power, high speed CMOS FLASH/EEPROM technology · Wide operating voltage range: 2.0V to 5.5V · Fully static design · Commercial, Industrial and Extended temperature ranges · Low power consumption: - < 2 mA typical @ 5V, 4 MHz - 20 µA typical @ 3V, 32 kHz - < 1 µA typical standby current
2002 Microchip Technology Inc.
PIC16F872
DS30221B-page 1
PIC16F872
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 3 2.0 Memory Organization.................................................................................................................................................................. 7 3.0 Data EEPROM and FLASH Program Memory ......................................................................................................................... 23 4.0 I/O Ports.................................................................................................................................................................................... 29 5.0 Timer0 Module .......................................................................................................................................................................... 35 6.0 Timer1 Module .......................................................................................................................................................................... 39 7.0 Timer2 Module .......................................................................................................................................................................... 43 8.0 Capture/Compare/PWM Module............................................................................................................................................... 45 9.0 Master Synchronous Serial Port (MSSP) Module..................................................................................................................... 51 10.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................ 79 11.0 Special Features of the CPU .................................................................................................................................................... 87 12.0 Instruction Set Summary......................................................................................................................................................... 103 13.0 Development Support ............................................................................................................................................................. 111 14.0 Electrical Characteristics......................................................................................................................................................... 117 15.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 139 16.0 Packaging Information ............................................................................................................................................................ 151 Appendix A: Revision History ........................................................................................................................................................... 155 Appendix B: Conversion Considerations........................................................................................................................................... 155 Index ................................................................................................................................................................................................. 157 On-Line Support................................................................................................................................................................................ 163 Reader Response ............................................................................................................................................................................. 164 PIC16F872 Product Identification System ........................................................................................................................................ 165
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Most Current Data Sheet
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: · Microchip's Worldwide Web site; http://www.microchip.com · Your local Microchip sales office (see last page) · The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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DS30221B-page 2
2002 Microchip Technology Inc.
PIC16F872
1.0 DEVICE OVERVIEW
This document contains device specific information about the PIC16F872 microcontroller. Additional information may be found in the PICmicroTM Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The block diagram of the PIC16F872 architecture is shown in Figure 1-1. A pinout description is provided in Table 1-2.
TABLE 1-1:
KEY FEATURES OF THE PIC16F872
DC - 20 MHz POR, BOR (PWRT, OST) 2K 128 64 10 Ports A, B, C 3 1 MSSP 5 input channels 35 Instructions 28-lead PDIP 28-lead SOIC 28-lead SSOP
Operating Frequency RESETS (and Delays) FLASH Program Memory (14-bit words) Data Memory (bytes) EEPROM Data Memory (bytes) Interrupts I/O Ports Timers Capture/Compare/PWM module Serial Communications 10-bit Analog-to-Digital Module Instruction Set Packaging
2002 Microchip Technology Inc.
DS30221B-page 3
PIC16F872
FIGURE 1-1: PIC16F872 BLOCK DIAGRAM
13 Program Counter FLASH Program Memory
Data Bus
8
PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS
8 Level Stack (13-bit)
RAM File Registers RAM Addr (1) 9 PORTB Indirect Addr
Program Bus
14 Instruction reg Direct Addr 7
Addr MUX 8
FSR reg STATUS reg 8 3
RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD
Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low Voltage Programming 8
MUX
PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7
ALU
W reg
MCLR
VDD, VSS
Timer0
Timer1
Timer2
Data EEPROM
CCP
Synchronous Serial Port
10-bit A/D
Note 1:
Higher order bits are from the STATUS register.
DS30221B-page 4
2002 Microchip Technology Inc.
PIC16F872
TABLE 1-2:
Pin Name OSC1/CLKI OSC1 CLKI OSC2/CLKO OSC2 10 O
PIC16F872 PINOUT DESCRIPTION
Pin# 9 I/O/P Type I Buffer Type Description
ST/CMOS Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode. Otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC2/CLKO pin). -- Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Master Clear (input) or programming voltage (output). Master Clear (Reset) input. This pin is an active low RESET to the device. Programming voltage input. PORTA is a bi-directional I/O port.
CLKO MCLR/VPP MCLR VPP RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREFRA2 AN2 VREFRA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI RA4 T0CKI RA5/SS/AN4 RA5 SS AN4 Legend: 2 I/O TTL 1 I/P ST
Digital I/O. Analog input 0. 3 I/O TTL Digital I/O. Analog input 1. 4 I/O TTL Digital I/O. Analog input 2. Negative analog reference voltage. 5 I/O TTL Digital I/O. Analog input 3. Positive analog reference voltage. 6 I/O ST Digital I/O; open drain when configured as output. Timer0 clock input. 7 I/O TTL Digital I/O. Slave Select for the Synchronous Serial Port. Analog input 4.
I = input O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
2002 Microchip Technology Inc.
DS30221B-page 5
PIC16F872
TABLE 1-2:
Pin Name
PIC16F872 PINOUT DESCRIPTION (CONTINUED)
Pin# I/O/P Type Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT RB0 INT RB1 RB2 RB3/PGM RB3 PGM RB4 RB5 RB6/PGC RB6 PGC RB7/PGD RB7 PGD RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI RC1 T1OSI RC2/CCP1 RC2 CCP1 RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6 RC7 VSS VDD Legend:
21
I/O
TTL/ST(1) Digital I/O. External interrupt pin.
22 23 24
I/O I/O I/O
TTL TTL TTL
Digital I/O. Digital I/O. Digital I/O. Low voltage ICSP programming enable pin.
25 26 27
I/O I/O I/O
TTL TTL TTL/ST(2)
Digital I/O. Digital I/O. Digital I/O. In-Circuit Debugger and ICSP programming clock.
28
I/O
TTL/ST(2) Digital I/O. In-Circuit Debugger and ICSP programming data. PORTC is a bi-directional I/O port.
11
I/O
ST Digital I/O. Timer1 oscillator output. Timer1 clock input.
12
I/O
ST Digital I/O. Timer1 oscillator input.
13
I/O
ST Digital I/O. Capture1 input/Compare1 output/PWM1 output.
14
I/O
ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode.
15
I/O
ST Digital I/O. SPI Data In pin (SPI mode). SPI Data I/O pin (I2C mode).
16
I/O
ST Digital I/O. SPI Data Out pin (SPI mode).
17 18 8, 19 20
I/O I/O P P
ST ST -- --
Digital I/O. Digital I/O. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
I = input O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
DS30221B-page 6
2002 Microchip Technology Inc.
PIC16F872
2.0 MEMORY ORGANIZATION
2.2 Data Memory Organization
There are three memory blocks in the PIC16F872. The Program Memory and Data Memory have separate buses so that concurrent access can occur. Data memory is covered in this section; the EEPROM data memory and FLASH program memory blocks are detailed in Section 3.0. Additional information on device memory may be found in the PICmicro Mid-Range Reference Manual (DS33023). The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits. RP1:RP0 00 01 10 11 Bank 0 1 2 3
2.1
Program Memory Organization
The PIC16F872 has a 13-bit program counter capable of addressing an 8K word x 14 bit program memory space. The PIC16F872 device actually has 2K words of FLASH program memory. Accessing a location above the physically implemented address will cause a wraparound. The RESET vector is at 0000h and the interrupt vector is at 0004h.
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access. Note: EEPROM Data Memory description can be found in Section 4.0 of this data sheet.
FIGURE 2-1:
PIC16F872 PROGRAM MEMORY MAP AND STACK
PC<12:0>
2.2.1
GENERAL PURPOSE REGISTER FILE
CALL, RETURN RETFIE, RETLW
13
The register file can be accessed either directly, or indirectly through the File Select Register (FSR).
Stack Level 1 Stack Level 2
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h 0005h
On-Chip Program Memory
Page 0
07FFh
1FFFh
2002 Microchip Technology Inc.
DS30221B-page 7
PIC16F872
FIGURE 2-2: PIC16F872 REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h accesses 20h-7Fh BFh C0h EFh F0h FFh Bank 2
File Address Indirect addr.(*) 100h 101h TMR0 102h PCL 103h STATUS 104h FSR 105h 106h PORTB 107h 108h 109h 10Ah PCLATH 10Bh INTCON 10Ch EEDATA EEADR 10Dh 10Eh EEDATH 10Fh EEADRH 110h
File Address Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h
PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON
PCLATH INTCON PIE1 PIE2 PCON
PCLATH INTCON EECON1 EECON2 Reserved(1) Reserved(1)
SSPCON2 PR2 SSPADD SSPSTAT
ADRESH ADCON0
ADRESL ADCON1 General Purpose Register 32 Bytes
120h accesses A0h - BFh
1A0h
General Purpose Register 96 Bytes
1BFh 1C0h 16Fh 170h 17Fh 1EFh 1F0h 1FFh
7Fh Bank 0
accesses 70h-7Fh Bank 1
accesses 70h-7Fh
accesses 70h-7Fh Bank 3
Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: These registers are reserved; maintain these registers clear.
DS30221B-page 8
2002 Microchip Technology Inc.
PIC16F872
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral feature section.
TABLE 2-1:
Address Bank 0 00h(2) 01h 02h(2) 03h 05h 06h 07h 08h 09h 0Ah(1,2) 0Bh(2) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note
(2)
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page:
Name
INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC -- -- PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON -- -- -- -- -- -- ADRESH ADCON0
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter (PC) Least Significant Byte IRP -- RP1 -- RP0 TO PD Z DC C Indirect Data Memory Address Pointer PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read Unimplemented Unimplemented -- GIE (3) -- -- PEIE ADIF (3) -- TMR0IE (3) -- INTE (3) EEIF RBIE SSPIF BCLIF TMR0IF CCP1IF -- INTF TMR2IF -- RBIF (3)
0000 0000 21, 93 xxxx xxxx 35, 93 0000 0000 20, 93 0001 1xxx 12, 93 xxxx xxxx 21, 93 --0x 0000 29, 93 xxxx xxxx 31, 93 xxxx xxxx 33, 93
04h(2)
-- --
-- --
Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93
0000 000x 14, 93 -r-0 0--r 18, 93 xxxx xxxx 40, 94 xxxx xxxx 40, 94 0000 0000 43, 94 xxxx xxxx 55, 94
TMR1IF r0rr 0000 16, 93
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- -- WCOL -- Timer2 Module Register Synchronous Serial Port Receive Buffer/Transmit Register SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- -- CCP1X CCP1Y Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented A/D Result Register High Byte ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/ DONE -- ADON
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 39, 94
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 43, 94
0000 0000 53, 94 xxxx xxxx 45, 94 xxxx xxxx 45, 94
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 45, 94 -- -- -- -- -- -- -- -- -- -- -- --
xxxx xxxx 84, 94 0000 00-0 79, 94
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These bits are reserved; always maintain these bits clear.
2002 Microchip Technology Inc.
DS30221B-page 9
PIC16F872
TABLE 2-1:
Address Bank 1 80h(2) 81h 82h(2) 83h(2) 84h 85h 86h 87h 88h 89h 8Ah(1,2) 8Bh(2) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 95h 95h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Legend: Note PR2 SSPADD SSPSTAT -- -- -- -- -- -- -- -- -- ADRESL ADCON1
(2)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page:
Name
INDF OPTION_REG PCL STATUS FSR TRISA TRISB TRISC -- -- PCLATH INTCON PIE1 PIE2 PCON -- -- SSPCON2
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU IRP -- INTEDG RP1 -- T0CS RP0 T0SE TO PSA PD PS2 Z PS1 DC PS0 C Program Counter (PC) Least Significant Byte Indirect data memory address pointer PORTA Data Direction Register PORTB Data Direction Register PORTC Data Direction Register Unimplemented Unimplemented -- GIE (3) -- -- -- PEIE ADIE (3) -- -- TMR0IE (3) -- -- Write Buffer for the upper 5 bits of the Program Counter INTE (3) EEIE -- RBIE SSPIE BCLIE -- TMR0IF CCP1IE -- -- INTF TMR2IE -- POR RBIF (3) BOR
0000 0000 21, 93 1111 1111 13, 94 0000 0000 20, 93 0001 1xxx 12, 93 xxxx xxxx 21, 93 --11 1111 29, 94 1111 1111 31, 94 1111 1111 33, 94
-- --
-- --
---0 0000 20, 93 0000 000x 14, 93 -r-0 0--r 17, 94 ---- --qq 19, 94
TMR1IE r0rr 0000 15, 94
Unimplemented Unimplemented GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register SMP CKE D/A P S R/W UA BF Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented A/D Result Register Low Byte ADFM -- -- -- PCFG3 PCFG2 PCFG1 PCFG0
-- --
-- --
0000 0000 54, 94 1111 1111 43, 94 0000 0000 58, 94 0000 0000 52, 94
-- -- -- -- -- -- -- -- --
0--- 0000
-- -- -- -- -- -- -- -- -- 80, 94
xxxx xxxx 84, 94
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These bits are reserved; always maintain these bits clear.
DS30221B-page 10
2002 Microchip Technology Inc.
PIC16F872
TABLE 2-1:
Address Bank 2 100h(2) 101h 102h
(2)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page:
Name
INDF TMR0 PCL STATUS FSR -- PORTB -- -- -- INTCON EEDATA EEADR EEDATH EEADRH INDF OPTION_REG PCL STATUS FSR -- TRISB -- -- -- INTCON EECON1 EECON2 -- --
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect Data Memory Address Pointer Unimplemented PORTB Data Latch when written: PORTB pins when read Unimplemented Unimplemented Unimplemented -- GIE -- PEIE -- TMR0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE TMR0IF INTF RBIF
0000 0000 21, 93 xxxx xxxx 35, 93 0000 0000 20, 93 0001 1xxx 12, 93 xxxx xxxx 21, 93
103h(2) 104h(2) 105h 106h 107h 108h 109h 10Bh(2) 10Ch 10Dh 10Eh 10Fh Bank 3 180h(2) 181h 182h(2) 183h(2) 184h(2) 185h 186h 187h 188h 189h 18Bh(2) 18Ch 18Dh 18Eh 18Fh Legend: Note
-- -- -- --
-- -- -- --
xxxx xxxx 31, 93
10Ah(1,2) PCLATH
---0 0000 20, 93 0000 000x 14, 93 xxxx xxxx 23, 94 xxxx xxxx 23, 94 xxxx xxxx 23, 94 xxxx xxxx 23, 94 0000 0000 21, 93
EEPROM Data Register Low Byte EEPROM Address Register Low Byte -- -- -- -- EEPROM Data Register High Byte -- EEPROM Address Register High Byte
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU IRP INTEDG RP1 T0CS RP0 T0SE TO PSA PD PS2 Z PS1 DC PS0 C Program Counter (PC) Least Significant Byte Indirect Data Memory Address Pointer Unimplemented PORTB Data Direction Register Unimplemented Unimplemented Unimplemented -- GIE EEPGD -- PEIE -- -- TMR0IE -- INTE -- RBIE WRERR TMR0IF WREN INTF WR RBIF RD
1111 1111 13, 94 0000 0000 20, 93 0001 1xxx 12, 93 xxxx xxxx 21, 93
-- -- -- --
-- -- -- --
1111 1111 31, 94
18Ah(1,2) PCLATH
Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93
0000 000x 14, 93 x--- x000 24, 94 ---- ---- 23, 94 0000 0000 0000 0000
EEPROM Control Register2 (not a physical register) Reserved; maintain clear Reserved; maintain clear
-- --
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These bits are reserved; always maintain these bits clear.
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2.2.2.1 STATUS Register
The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable, therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions not affecting any status bits, see the "Instruction Set Summary." Note: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1:
STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)
R/W-0 IRP bit 7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 6:5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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PIC16F872
2.2.2.2 OPTION_REG Register
Note: The OPTION_REG Register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
REGISTER 2-2:
OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1 RBPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Legend: R = Readable bit - n = Value at POR Note: W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device
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2.2.2.3 INTCON Register
Note: The INTCON Register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-3:
INTCON REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 GIE bit 7 R/W-0 PEIE R/W-0 TMR0IE R/W-0 INTE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INTF R/W-x RBIF bit 0
bit 7
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared (must be cleared in software). 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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2.2.2.4 PIE1 Register
Note: The PIE1 register contains the individual enable bits for the peripheral interrupts. Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
REGISTER 2-4:
PIE1 REGISTER (ADDRESS: 8Ch)
R/W-0 reserved bit 7 R/W-0 ADIE R/W-0 reserved R/W-0 reserved R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0
bit 7 bit 6
Reserved: Always maintain these bits clear ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt Reserved: Always maintain these bits clear SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 5-4 bit 3
bit 2
bit 1
bit 0
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2.2.2.5 PIR1 Register
Note: The PIR1 register contains the individual flag bits for the peripheral interrupts. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt.
REGISTER 2-5:
PIR1 REGISTER (ADDRESS: 0Ch)
R/W-0 reserved bit 7 R/W-0 ADIF R/W-0 reserved R/W-0 reserved R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
bit 7 bit 6
Reserved: Always maintain these bits clear ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete Reserved: Always maintain these bits clear SSPIF: Synchronous Serial Port (SSP) Interrupt Flag 1 = The SSP interrupt condition has occurred, and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are: · SPI - A transmission/reception has taken place · I2C Slave - A transmission/reception has taken place · I2C Master - A transmission/reception has taken place - The initiated START condition was completed by the SSP module - The initiated STOP condition was completed by the SSP module - The initiated Restart condition was completed by the SSP module - The initiated Acknowledge condition was completed by the SSP module - A START condition occurred while the SSP module was idle (multi-master system) - A STOP condition occurred while the SSP module was idle (multi-master system) 0 = No SSP interrupt condition has occurred CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 5-4 bit 3
bit 2
bit 1
bit 0
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PIC16F872
2.2.2.6 PIE2 Register
The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision interrupt, and the EEPROM write operation interrupt.
REGISTER 2-6:
PIE2 REGISTER (ADDRESS: 8Dh)
U-0 -- bit 7 R/W-0 reserved U-0 -- R/W-0 EEIE R/W-0 BCLIE U-0 -- U-0 -- R/W-0 reserved bit 0
bit 7 bit 6 bit 5 bit 4
Unimplemented: Read as '0' Reserved: Always maintain this bit clear Unimplemented: Read as '0' EEIE: EEPROM Write Operation Interrupt Enable bit 1 = Enable EEPROM write interrupt 0 = Disable EEPROM write interrupt BCLIE: Bus Collision Interrupt Enable bit 1 = Enable bus collision interrupt 0 = Disable bus collision interrupt Unimplemented: Read as '0' Reserved: Always maintain this bit clear Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 3
bit 2-1 bit 0
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2.2.2.7 PIR2 Register
Note: The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt and the EEPROM write operation interrupt.
.
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-7:
PIR2 REGISTER (ADDRESS: 0Dh)
U-0 -- bit 7 R/W-0 reserved U-0 -- R/W-0 EEIF R/W-0 BCLIF U-0 -- U-0 -- R/W-0 reserved bit 0
bit 7 bit 6 bit 5 bit 4
Unimplemented: Read as '0' Reserved: Always maintain this bit clear Unimplemented: Read as '0' EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision has occurred in the SSP, when configured for I2C Master mode 0 = No bus collision has occurred Unimplemented: Read as '0' Reserved: Always maintain this bit clear Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 3
bit 2-1 bit 0
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PIC16F872
2.2.2.8 PCON Register
Note: The Power Control (PCON) Register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR Reset. BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a don't care and is not predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the Configuration Word).
REGISTER 2-8:
PCON REGISTER (ADDRESS: 8Eh)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-1 BOR bit 0
bit 7-2 bit 1
Unimplemented: Read as '0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 0
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2.3 PCL and PCLATH
2.3.2 STACK
The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The PIC16FXXX family has an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no status bits to indicate stack overflow or stack underflow conditions.
Instruction with PCL as Destination ALU
FIGURE 2-3:
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 8 7 0
PCH 12 PC 5
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0
GOTO,CALL
2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address.
2.4
Program Memory Paging
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the Application Note, "Implementing a Table Read" (AN556).
All PIC16FXXX devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. Since the PIC16F872 has only 2K words of program memory or one page, additional code is not required to ensure that the correct page is selected before a CALL or GOTO instruction is executed. The PCLATH<4:3> bits should always be maintained as zeros. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (which POPs the address from the stack). Note: The contents of the PCLATH register are unchanged after a RETURN or RETFIE instruction is executed. The user must rewrite the contents of the PCLATH register for any subsequent subroutine calls or GOTO instructions.
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PIC16F872
2.5 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-1.
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = '0'), will read 00h. Writing to the INDF register indirectly results in a no operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-4.
EXAMPLE 2-1:
MOVLW MOVWF CLRF INCF BTFSS GOTO :
INDIRECT ADDRESSING
0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
NEXT
CONTINUE
FIGURE 2-4:
DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing 0 IRP 7 FSR Register 0
RP1:RP0
6
From Opcode
Bank Select
Location Select 00 00h 01 80h 10 100h 11 180h
Bank Select
Location Select
Data Memory(1)
7Fh Bank 0
FFh Bank 1
17Fh Bank 2
1FFh Bank 3
Note 1: For register file map detail, see Figure 2-2.
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NOTES:
DS30221B-page 22
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PIC16F872
3.0 DATA EEPROM AND FLASH PROGRAM MEMORY
The EEPROM Data memory allows byte read and write operations without interfering with the normal operation of the microcontroller. When interfacing to EEPROM Data memory, the EEADR register holds the address to be accessed. Depending on the operation, the EEDATA register holds the data to be written or the data read at the address in EEADR. The PIC16F872 has 64 bytes of EEPROM Data memory and therefore, requires that the two Most Significant bits of EEADR remain clear. EEPROM Data memory on these devices wraps around to 0 (i.e., 40h in the EEADR maps to 00h). The FLASH Program memory allows non-intrusive read access, but write operations cause the device to stop executing instructions until the write completes. When interfacing to the Program memory, the EEADRH:EEADR registers pair forms a two-byte word which holds the 13-bit address of the memory location being accessed. The EEDATH:EEDATA register pair holds the 14-bit data for writes or reflects the value of program memory after a read operation. Just as in EEPROM Data memory accesses, the value of the EEADRH:EEADR registers must be within the valid range of program memory, depending on the device (0000h to 07FFh). Addresses outside of this range wrap around to 0000h (i.e., 0800h maps to 0000h).
The Data EEPROM and FLASH Program Memory are readable and writable during normal operation over the entire VDD range. These operations take place on a single byte for Data EEPROM memory and a single word for Program memory. A write operation causes an erase-then-write operation to take place on the specified byte or word. A bulk erase operation may not be issued from user code (which includes removing code protection). Access to program memory allows for checksum calculation. The values written to Program memory do not need to be valid instructions. Therefore, numbers of up to 14 bits can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ASCII, etc. Executing a program memory location, containing data that forms an invalid instruction, results in the execution of a NOP instruction. The EEPROM Data memory is rated for high erase/ write cycles (specification #D120). The FLASH Program memory is rated much lower (specification #D130) because EEPROM Data memory can be used to store frequently updated values. An on-chip timer controls the write time and it will vary with voltage and temperature, as well as from chip to chip. Please refer to the specifications for exact limits (specifications #D122 and #D133). A byte or word write automatically erases the location and writes the new value (erase before write). Writing to EEPROM Data memory does not impact the operation of the device. Writing to Program memory will cease the execution of instructions until the write is complete. The program memory cannot be accessed during the write. During the write operation, the oscillator continues to run, the peripherals continue to function and interrupt events will be detected and essentially "queued" until the write is complete. When the write completes, the next instruction in the pipeline is executed and the branch to the interrupt vector will take place if the interrupt is enabled and occurred during the write. Read and write access to both memories take place indirectly through a set of Special Function Registers (SFR). The six SFRs used are: · · · · · · EEDATA EEDATH EEADR EEADRH EECON1 EECON2
3.1
EECON1 and EECON2 Registers
The EECON1 register is the control register for configuring and initiating the access. The EECON2 register is not a physically implemented register, but is used exclusively in the memory write sequence to prevent inadvertent writes. There are many bits used to control the read and write operations to EEPROM Data and FLASH Program memory. The EEPGD bit determines if the access will be a program or data memory access. When clear, any subsequent operations will work on the EEPROM Data memory. When set, all subsequent operations will operate in the Program memory. Read operations only use one additional bit, RD, which initiates the read operation from the desired memory location. Once this bit is set, the value of the desired memory location will be available in the data registers. This bit cannot be cleared by firmware. It is automatically cleared at the end of the read operation. For EEPROM Data memory reads, the data will be available in the EEDATA register in the very next instruction cycle after the RD bit is set. For program memory reads, the data will be loaded into the EEDATH:EEDATA registers, following the second instruction after the RD bit is set.
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Write operations have two control bits, WR and WREN, and two status bits, WRERR and EEIF. The WREN bit is used to enable or disable the write operation. When WREN is clear, the write operation will be disabled. Therefore, the WREN bit must be set before executing a write operation. The WR bit is used to initiate the write operation. It also is automatically cleared at the end of the write operation. The interrupt flag EEIF (located in register PIR2) is used to determine when the memory write completes. This flag must be cleared in software before setting the WR bit. For EEPROM Data memory, once the WREN bit and the WR bit have been set, the desired memory address in EEADR will be erased followed by a write of the data in EEDATA. This operation takes place in parallel with the microcontroller continuing to execute normally. When the write is complete, the EEIF flag bit will be set. For program memory, once the WREN bit and the WR bit have been set, the microcontroller will cease to execute instructions. The desired memory location pointed to by EEADRH:EEADR will be erased. Then the data value in EEDATH:EEDATA will be programmed. When complete, the EEIF flag bit will be set and the microcontroller will continue to execute code. The WRERR bit is used to indicate when the device has been RESET during a write operation. WRERR should be cleared after Power-on Reset. Thereafter, it should be checked on any other RESET. The WRERR bit is set when a write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation. In these situations, following a RESET, the user should check the WRERR bit and rewrite the memory location if set. The contents of the data registers, address registers and EEPGD bit are not affected by either MCLR Reset or WDT Time-out Reset during normal operation.
REGISTER 3-1:
EECON1 REGISTER (ADDRESS 18Ch)
R/W-x EEPGD bit 7 U-0 -- U-0 -- U-0 -- R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 7
EEPGD: Program/Data EEPROM Select bit 1 = Accesses Program memory 0 = Accesses data memory (This bit cannot be changed while a read or write operation is in progress.) Unimplemented: Read as '0' WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset or any WDT Reset during normal operation) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM WR: Write Control bit 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate an EEPROM read Legend: S = Settable bit '1' = Bit is set R = Readable bit '0' = Bit is cleared W = Writable bit - n = Value at POR x = Bit is unknown U = Unimplemented bit, read as `0'
bit 6-4 bit 3
bit 2
bit 1
bit 0
DS30221B-page 24
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PIC16F872
3.2 Reading the EEPROM Data Memory
Reading EEPROM Data memory only requires that the desired address to access be written to the EEADR register and clear the EEPGD bit. After the RD bit is set, data will be available in the EEDATA register on the very next instruction cycle. EEDATA will hold this value until another read operation is initiated or until it is written by firmware. The steps to reading the EEPROM Data Memory are: 1. Write the address to EEDATA. Make sure that the address is not larger than the memory size of the device. Clear the EEPGD bit to point to EEPROM Data memory. Set the RD bit to start the read operation. Read the data from the EEDATA register. should be kept clear at all times, except when writing to the EEPROM Data. The WR bit can only be set if the WREN bit was set in a previous operation, i.e., they both cannot be set in the same operation. The WREN bit should then be cleared by firmware after the write. Clearing the WREN bit before the write actually completes will not terminate the write in progress. Writes to EEPROM Data memory must also be prefaced with a special sequence of instructions that prevent inadvertent write operations. This is a sequence of five instructions that must be executed without interruption for each byte written. The steps to write to program memory are: 1. Write the address to EEADR. Make sure that the address is not larger than the memory size of the device. Write the 8-bit data value to be programmed in the EEDATA registers. Clear the EEPGD bit to point to EEPROM Data memory. Set the WREN bit to enable program operations. Disable interrupts (if enabled). Execute the special five instruction sequence: · Write 55h to EECON2 in two steps (first to W, then to EECON2) · Write AAh to EECON2 in two steps (first to W, then to EECON2) · Set the WR bit Enable interrupts (if using interrupts). Clear the WREN bit to disable program operations. At the completion of the write cycle, the WR bit is cleared and the EEIF interrupt flag bit is set. (EEIF must be cleared by firmware). Firmware may check for EEIF to be set or WR to clear to indicate end of program cycle.
2. 3. 4.
2. 3.
EXAMPLE 3-1:
BSF BCF MOVF MOVWF BSF BCF BSF BCF MOVF STATUS, STATUS, ADDR, W EEADR STATUS, EECON1, EECON1, STATUS, EEDATA, RP1 RP0
EEPROM DATA READ
; ;Bank 2 ;Write address ;to read from ;Bank 3 ;Point to Data memory ;Start read operation ;Bank 2 ;W = EEDATA
4. 5. 6.
RP0 EEPGD RD RP0 W
3.3
Writing to the EEPROM Data Memory
7. 8. 9.
There are many steps in writing to the EEPROM Data memory. Both address and data values must be written to the SFRs. The EEPGD bit must be cleared and the WREN bit must be set to enable writes. The WREN bit
EXAMPLE 3-2:
BSF BCF MOVF MOVWF MOVF MOVWF BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF
EEPROM DATA WRITE
STATUS, RP1 STATUS, RP0 ADDR, W EEADR VALUE, W EEDATA STATUS, RP0 EECON1, EEPGD EECON1, WREN INTCON, GIE 0x55 EECON2 0xAA EECON2 EECON1, WR INTCON, GIE EECON1, WREN ; ;Bank 2 ;Address to ;write to ;Data to ;write ;Bank 3 ;Point to Data memory ;Enable writes ;Only disable interrupts ;if already enabled, ;otherwise discard ;Write 55h to ;EECON2 ;Write AAh to ;EECON2 ;Start write operation ;Only enable interrupts ;if using interrupts, ;otherwise discard ;Disable writes
2002 Microchip Technology Inc.
Required Sequence
DS30221B-page 25
PIC16F872
3.4 Reading the FLASH Program Memory
The steps to reading the FLASH Program Memory are: 1. Write the address to EEADRH:EEADR. Make sure that the address is not larger than the memory size of the device. Set the EEPGD bit to point to FLASH Program memory. Set the RD bit to start the read operation. Execute two NOP instructions to allow the microcontroller to read out of program memory. Read the data from the EEDATH:EEDATA registers. Reading FLASH Program memory is much like that of EEPROM Data memory, only two NOP instructions must be inserted after the RD bit is set. These two instruction cycles that the NOP instructions execute will be used by the microcontroller to read the data out of program memory and insert the value into the EEDATH:EEDATA registers. Data will be available following the second NOP instruction. EEDATH and EEDATA will hold their value until another read operation is initiated, or until they are written by firmware.
2. 3. 4. 5.
EXAMPLE 3-3:
BSF BCF MOVF MOVWF MOVF MOVWF BSF BSF
Required Sequence
FLASH PROGRAM READ
STATUS, RP1 STATUS, RP0 ADDRL, W EEADR ADDRH,W EEADRH STATUS, RP0 EECON1, EEPGD EECON1, RD ; ;Bank 2 ;Write the ;address bytes ;for the desired ;address to read ;Bank 3 ;Point to Program memory ;Start read operation ;Required two NOPs ; STATUS, RP0 EEDATA, W DATAL EEDATH,W DATAH ;Bank 2 ;DATAL = EEDATA ; ;DATAH = EEDATH ;
BSF NOP NOP BCF MOVF MOVWF MOVF MOVWF
3.5
Writing to the FLASH Program Memory
Writing to FLASH Program memory is unique in that the microcontroller does not execute instructions while programming is taking place. The oscillator continues to run and all peripherals continue to operate and queue interrupts, if enabled. Once the write operation completes (specification #D133), the processor begins executing code from where it left off. The other important difference when writing to FLASH Program memory is that the WRT configuration bit, when clear, prevents any writes to program memory (see Table 3-1). Just like EEPROM Data memory, there are many steps in writing to the FLASH Program memory. Both address and data values must be written to the SFRs. The EEPGD bit must be set and the WREN bit must be set to enable writes. The WREN bit should be kept
clear at all times, except when writing to the FLASH Program memory. The WR bit can only be set if the WREN bit was set in a previous operation, i.e., they both cannot be set in the same operation. The WREN bit should then be cleared by firmware after the write. Clearing the WREN bit before the write actually completes will not terminate the write in progress. Writes to program memory must also be prefaced with a special sequence of instructions that prevent inadvertent write operations. This is a sequence of five instructions that must be executed without interruption for each byte written. These instructions must then be followed by two NOP instructions to allow the microcontroller to setup for the write operation. Once the write is complete, the execution of instructions starts with the instruction after the second NOP.
DS30221B-page 26
2002 Microchip Technology Inc.
PIC16F872
The steps to write to program memory are: 1. Write the address to EEADRH:EEADR. Make sure that the address is not larger than the memory size of the device. Write the 14-bit data value to be programmed in the EEDATH:EEDATA registers. Set the EEPGD bit to point to FLASH Program memory. Set the WREN bit to enable program operations. Disable interrupts (if enabled). Execute the special five instruction sequence: · Write 55h to EECON2 in two steps (first to W, then to EECON2) · Write AAh to EECON2 in two steps (first to W, then to EECON2) · Set the WR bit Execute two NOP instructions to allow the microcontroller to setup for write operation. Enable interrupts (if using interrupts). Clear the WREN bit to disable program operations.
7. 8. 9.
2. 3. 4. 5. 6.
At the completion of the write cycle, the WR bit is cleared and the EEIF interrupt flag bit is set. (EEIF must be cleared by firmware). Since the microcontroller does not execute instructions during the write cycle, the firmware does not necessarily have to check either EEIF or WR to determine if the write had finished.
EXAMPLE 3-4:
BSF BCF MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF BSF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP BSF BCF
FLASH PROGRAM WRITE
STATUS, RP1 STATUS, RP0 ADDRL, W EEADR ADDRH, W EEADRH VALUEL, W EEDATA VALUEH, W EEDATH STATUS, RP0 EECON1, EEPGD EECON1, WREN INTCON, GIE 0x55 EECON2 0xAA EECON2 EECON1, WR ; ;Bank 2 ;Write address ;of desired ;program memory ;location ;Write value to ;program at ;desired memory ;location ;Bank 3 ;Point to Program memory ;Enable writes ;Only disable interrupts ;if already enabled, ;otherwise discard ;Write 55h to ;EECON2 ;Write AAh to ;EECON2 ;Start write operation ;Two NOPs to allow micro ;to setup for write ;Only enable interrupts ;if using interrupts, ;otherwise discard ;Disable writes
Required Sequence
INTCON, GIE EECON1, WREN
3.6
Write Verify
3.7
Protection Against Spurious Writes
The PIC16F87X devices do not automatically verify the value written during a write operation. Depending on the application, good programming practice may dictate that the value written to memory be verified against the original value. This should be used in applications where excessive writes can stress bits near the specified endurance limits.
There are conditions when the device may not want to write to the EEPROM Data memory or FLASH program memory. To protect against these spurious write conditions various mechanisms have been built into the device. On power-up, the WREN bit is cleared and the Power-up Timer (if enabled) prevents writes. The write initiate sequence and the WREN bit together help prevent any accidental writes during brown-out, power glitches or firmware malfunction.
2002 Microchip Technology Inc.
DS30221B-page 27
PIC16F872
3.8 Operation While Code Protected
The PIC16F872 has two code protect mechanisms, one bit for EEPROM Data memory and two bits for FLASH Program memory. Data can be read and written to the EEPROM Data memor