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PIC16F870/871
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
Devices Included in this Data Sheet:
· PIC16F870 · PIC16F871
Pin Diagram PDIP
MCLR/VPP/THV RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3 RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5 RC4 RD3/PSP3 RD2/PSP2
Microcontroller Core Features:
· High-performance RISC CPU · Only 35 single word instructions to learn · All single cycle instructions except for program branches which are two cycle · Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle · 2K x 14 words of FLASH Program Memory 128 x 8 bytes of Data Memory (RAM) 64 x 8 bytes of EEPROM Data Memory · Pinout compatible to the PIC16CXXX 28 and 40pin devices · Interrupt capability (up to 11 sources) · Eight level deep hardware stack · Direct, indirect and relative addressing modes · Power-on Reset (POR) · Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) · Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation · Programmable code-protection · Power saving SLEEP mode · Selectable oscillator options · Low-power, high-speed CMOS FLASH/EEPROM technology · Fully static design · In-Circuit Serial ProgrammingTM (ICSP) via two pins · Single 5V In-Circuit Serial Programming capability · In-Circuit Debugging via two pins · Processor read/write access to program memory · Wide operating voltage range: 2.0V to 5.5V · High Sink/Source Current: 25 mA · Commercial and Industrial temperature ranges · Low-power consumption: - < 1.6 mA typical @ 5V, 4 MHz - 20 µA typical @ 3V, 32 kHz - < 1 µA typical standby current
Peripheral Features:
· Timer0: 8-bit timer/counter with 8-bit prescaler · Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock · Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler · One Capture, Compare, PWM module - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit · 10-bit multi-channel Analog-to-Digital converter · Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection · Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (40/44-pin only) · Brown-out detection circuitry for Brown-out Reset (BOR)
© 1999 Microchip Technology Inc.
Preliminary
PIC16F871
DS30569A-page 1
PIC16F870/871
Pin Diagrams DIP, SOIC, SSOP
MCLR/VPP/THV RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4 VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5 RC4 RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 MCLR/VPP/THV NC RB7/PGD RB6/PGC RB5 RB4 NC 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 9
PIC16F870
PLCC
TQFP
44 43 42 41 40 39 38 37 36 35 34
RC6/TX/CK RC5 RC4 RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3 RC2/CCP1 RC1/T1OSI NC
NC NC RB4 RB5 RB6/PGC RB7/PGD MCLR/VPP/THV RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3/PGM
1 2 3 4 5 6 7 8 9 10 11
PIC16F871
33 32 31 30 29 28 27 26 25 24 23
NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4 RA4/T0CKI
DS30569A-page 2
Preliminary
RC1/T1OSI RC2/CCP1 RC3 RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4 RC5 RC6/TX/CK NC
18 19 20 21 22 23 24 25 26 27 282
RA4/T0CKI RA5/AN4 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CK1 NC
7 8 9 10 11 12 13 14 15 16 17
PIC16F871
RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT
© 1999 Microchip Technology Inc.
PIC16F870/871
Key Features PICmicroTM Mid-Range Reference Manual (DS33023) Operating Frequency Resets (and Delays) FLASH Program Memory (14-bit words) Data Memory (bytes) EEPROM Data Memory Interrupts I/O Ports Timers Capture/Compare/PWM modules Serial Communications Parallel Communications 10-bit Analog-to-Digital Module Instruction Set PIC16F870 DC - 20 MHz POR, BOR (PWRT, OST) 2K 128 64 10 Ports A,B,C 3 1 USART -- 5 input channels 35 Instructions PIC16F871 DC - 20 MHz POR, BOR (PWRT, OST) 2K 128 64 11 Ports A,B,C,D,E 3 1 USART PSP 8 input channels 35 Instructions
© 1999 Microchip Technology Inc.
Preliminary
DS30569A-page 3
PIC16F870/871
Table of Contents
1.0 Device Overview ................................................................................................................................................... 5 2.0 Memory Organization.......................................................................................................................................... 11 3.0 I/O Ports .............................................................................................................................................................. 27 4.0 Data EEPROM and FLASH Program Memory.................................................................................................... 39 5.0 Timer0 Module .................................................................................................................................................... 47 6.0 Timer1 Module .................................................................................................................................................... 51 7.0 Timer2 Module .................................................................................................................................................... 55 8.0 Capture/Compare/PWM Module ......................................................................................................................... 57 9.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ........................................ 63 10.0 Analog-to-Digital Converter (A/D) Module........................................................................................................... 79 11.0 Special Features of the CPU............................................................................................................................... 89 12.0 Instruction Set Summary ................................................................................................................................... 105 13.0 Development Support ....................................................................................................................................... 113 14.0 Electrical Characteristics ................................................................................................................................... 119 15.0 DC and AC Characteristics Graphs and Tables................................................................................................ 135 16.0 Packaging Information ...................................................................................................................................... 137 Index .......................................................................................................................................................................... 145 On-Line Support .......................................................................................................................................................... 151 Reader Response ....................................................................................................................................................... 152 Product Identification System...................................................................................................................................... 153
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An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: · Microchip's Worldwide Web site; http://www.microchip.com · Your local Microchip sales office (see last page) · The Microchip Corporate Literature Center; U.S. FAX: (480) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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DS30569A-page 4
Preliminary
© 1999 Microchip Technology Inc.
PIC16F870/871
1.0 DEVICE OVERVIEW
This document contains device-specific information. Additional information may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. There are two devices (PIC16F870 and PIC16F871) covered by this data sheet. The PIC16F870 device comes in a 28-pin package and the PIC16F871 device comes in a 40-pin package. The 28-pin device does not have a Parallel Slave Port implemented. The following two figures are device block diagrams sorted by pin number; 28-pin for Figure 1-1 and 40-pin for Figure 1-2. The 28-pin and 40-pin pinouts are listed in Table 1-1 and Table 1-2, respectively.
FIGURE 1-1:
Device PIC16F870
PIC16F870 BLOCK DIAGRAM
Program FLASH 2K Data Memory 128 Bytes Data EEPROM 64 Bytes
13 Program Counter FLASH Program Memory 8 Level Stack (13-bit) Program Bus 14 Instruction reg Direct Addr 7
Data Bus
8
PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4 PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3 RC4 RC5 RC6/TX/CK RC7/RX/DT
RAM File Registers
RAM Addr (1)
9
Addr MUX 8 Indirect Addr
FSR reg STATUS reg 8 3 PORTC
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low-Voltage Programming 8
MUX
ALU
W reg
MCLR
VDD, VSS
Timer0
Timer1
Timer2
10-bit A/D
Data EEPROM
CCP1
USART
Note 1: Higher order bits are from the STATUS register.
© 1999 Microchip Technology Inc.
Preliminary
DS30569A-page 5
PIC16F870/871
FIGURE 1-2:
Device PIC16F871
PIC16F871 BLOCK DIAGRAM
Program FLASH 2K Data Memory 128 Bytes Data EEPROM 64 Bytes
13 FLASH Program Memory 8 Level Stack (13-bit) Program Bus 14 Instruction reg Direct Addr 7 Program Counter
Data Bus
8
PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4 PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3 RC4 RC5 RC6/TX/CK RC7/RX/DT PORTD
RAM File Registers
RAM Addr (1)
9
Addr MUX 8 Indirect Addr
FSR reg STATUS reg 8 3 PORTC
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low-Voltage Programming 8
MUX
ALU
W reg RD7/PSP7:RD0/PSP0
PORTE RE0/AN5/RD RE1/AN6/WR
MCLR
VDD, VSS
RE2/AN7/CS
Timer0
Timer1
Timer2
10-bit A/D
Data EEPROM
CCP1
Parallel Slave Port
USART
Note 1: Higher order bits are from the STATUS register.
DS30569A-page 6
Preliminary
© 1999 Microchip Technology Inc.
PIC16F870/871
TABLE 1-1:
Pin Name
OSC1/CLKIN OSC2/CLKOUT
PIC16F870 PINOUT DESCRIPTION
DIP Pin#
9 10
SOIC Pin#
9 10
I/O/P Type
I O
Buffer Type
Description
ST/CMOS(3) Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input or programming voltage input or high voltage test mode control. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0 can also be analog input0 RA1 can also be analog input1 RA2 can also be analog input2 or negative analog reference voltage RA3 can also be analog input3 or positive analog reference voltage RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5 can also be analog input4 PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
MCLR/VPP/THV
1
1
I/P
ST
RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4
2 3 4 5 6 7
2 3 4 5 6 7
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST TTL
RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD
21 22 23 24 25 26 27 28
21 22 23 24 25 26 27 28
I/O I/O I/O I/O I/O I/O I/O I/O
TTL/ST(1) TTL TTL TTL/ST(1) TTL TTL TTL/ST
(2)
RB0 can also be the external interrupt pin.
RB3 can also be the low voltage programming input Interrupt on change pin. Interrupt on change pin. Interrupt on change pin or In-Circuit Debugger pin. Serial programming clock. Interrupt on change pin or In-Circuit Debugger pin. Serial programming data. PORTC is a bi-directional I/O port. RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1 can also be the Timer1 oscillator input RC2 can also be the Capture1 input/Compare1 output/PWM1 output.
TTL/ST(2)
RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3 RC4 RC5 RC6/TX/CK RC7/RX/DT VSS VDD Legend: I = input
11 12 13 14 15 16 17 18 8, 19 20
11 12 13 14 15 16 17 18 8, 19 20
I/O I/O I/O I/O I/O I/O I/O I/O P P
ST ST ST ST ST ST ST ST -- --
RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7 can also be the USART Asynchronous Receive or Synchronous Data. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or LVP mode. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
© 1999 Microchip Technology Inc.
Preliminary
DS30569A-page 7
PIC16F870/871
TABLE 1-2:
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16F871 PINOUT DESCRIPTION
DIP Pin# 13 14 PLCC Pin# 14 15 QFP Pin# 30 31 I/O/P Type I O Buffer Type ST/CMOS(4) -- Description Oscillator crystal input/external clock source input. Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input or programming voltage input or high voltage test mode control. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0 can also be analog input0 RA1 can also be analog input1 RA2 can also be analog input2 or negative analog reference voltage RA3 can also be analog input3 or positive analog reference voltage RA4 can also be the clock input to the Timer0 timer/ counter. Output is open drain type. RA5 can also be analog input4 PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
MCLR/VPP/THV
1
2
18
I/P
ST
RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4
2 3 4 5 6 7
3 4 5 6 7 8
19 20 21 22 23 24
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST TTL
RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD
33 34 35 36 37 38 39 40
36 37 38 39 41 42 43 44
8 9 10 11 14 15 16 17
I/O I/O I/O I/O I/O I/O I/O I/O
TTL/ST(1) TTL TTL TTL/ST(1) TTL TTL TTL/ST(2) TTL/ST(2)
RB0 can also be the external interrupt pin.
RB3 can also be the low voltage programming input Interrupt on change pin. Interrupt on change pin. Interrupt on change pin or In-Circuit Debugger pin. Serial programming clock. Interrupt on change pin or In-Circuit Debugger pin. Serial programming data. PORTC is a bi-directional I/O port. RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1 can also be the Timer1 oscillator input RC2 can also be the Capture1 input/Compare1 output/ PWM1 output.
RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3 RC4 RC5 RC6/TX/CK RC7/RX/DT Legend: Note 1: 2: 3: 4: I = input
15 16 17 18 23 24 25 26
16 18 19 20 25 26 27 29
32 35 36 37 42 43 44 1
I/O I/O I/O I/O I/O I/O I/O I/O
ST ST ST ST ST ST ST ST
RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7 can also be the USART Asynchronous Receive or Synchronous Data.
O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt or LVP mode. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS30569A-page 8
Preliminary
© 1999 Microchip Technology Inc.
PIC16F870/871
TABLE 1-2:
Pin Name
PIC16F871 PINOUT DESCRIPTION (CONTINUED)
DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus.
RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7
19 20 21 22 27 28 29 30
21 22 23 24 30 31 32 33
38 39 40 41 2 3 4 5
I/O I/O I/O I/O I/O I/O I/O I/O
ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) PORTE is a bi-directional I/O port.
(3)
RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VSS VDD NC Legend: Note 1: 2: 3: 4: I = input
8 9 10 12,31 11,32 --
9 10 11 13,34 12,35 1,17,28, 40
25 26 27 6,29 7,28 12,13, 33,34
I/O I/O I/O P P
ST/TTL
RE0 can also be read control for the parallel slave port, or analog input5. RE1 can also be write control for the parallel slave port, or analog input6. RE2 can also be select control for the parallel slave port, or analog input7. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. These pins are not internally connected. These pins should be left unconnected.
ST/TTL(3) ST/TTL(3) -- -- --
O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt or LVP mode. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
© 1999 Microchip Technology Inc.
Preliminary
DS30569A-page 9
PIC16F870/871
NOTES:
DS30569A-page 10
Preliminary
© 1999 Microchip Technology Inc.
PIC16F870/871
2.0 MEMORY ORGANIZATION
2.2 Data Memory Organization
There are three memory blocks in each of these PICmicro ® MCUs. The Program Memory and Data Memory have separate buses, so that concurrent access can occur, and is detailed in this section. The EEPROM data memory block is detailed in Section 4.0. Additional information on device memory may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023). The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1(STATUS<6>) and RP0 (STATUS<5>) are the bank select bits. RP<1:0> 00 01 10 11 Bank 0 1 2 3
2.1
Program Memory Organization
The PIC16F870/871 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. The PIC16F870/871 devices have 2K x 14 words of FLASH program memory. Accessing a location above the physically implemented address will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h.
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some "high use" Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access. Note: 2.2.1 EEPROM Data Memory description can be found in Section 4.0 of this Data Sheet GENERAL PURPOSE REGISTER FILE
FIGURE 2-1:
PIC16F870/871 PROGRAM MEMORY MAP AND STACK
PC<12:0>
The register file can be accessed either directly, or indirectly through the File Select Register FSR.
13
CALL, RETURN RETFIE, RETLW
Stack Level 1 Stack Level 2
Stack Level 8
Reset Vector
0000h
Interrupt Vector On-Chip Program Memory
0004h 0005h
Page 0 07FFh 0800h
1FFFh
© 1999 Microchip Technology Inc.
Preliminary
DS30569A-page 11
PIC16F870/871
FIGURE 2-2: PIC16F870/871 REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(2) PORTE(2) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.(*) File Address 80h OPTION_REG 81h PCL 82h STATUS 83h FSR 84h TRISA 85h TRISB 86h TRISC 87h TRISD(2) 88h TRISE(2) 89h PCLATH 8Ah INTCON 8Bh PIE1 8Ch PIE2 8Dh PCON 8Eh 8Fh 90h 91h PR2 92h 93h 94h 95h 96h 97h TXSTA 98h SPBRG 99h 9Ah 9Bh 9Ch 9Dh ADRESL 9Eh 9Fh ADCON1 General Purpose Register 32 Bytes A0h accesses 20h-7Fh BFh C0h EFh F0h FFh Bank 2 16Fh 170h 17Fh accesses A0h - BFh 1BFh 1C0h 1EFh 1F0h 1FFh File Address Indirect addr.(*) 100h 101h TMR0 102h PCL 103h STATUS 104h FSR 105h 106h PORTB 107h 108h 109h 10Ah PCLATH 10Bh INTCON 10Ch EEDATA EEADR 10Dh 10Eh EEDATH 10Fh EEADRH 110h File Address Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h
PCLATH INTCON EECON1 EECON2 Reserved(1) Reserved(1)
CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG
ADRESH ADCON0
120h
1A0h
General Purpose Register 96 Bytes
7Fh Bank 0
accesses 70h-7Fh Bank 1
accesses 70h-7Fh
accesses 70h-7Fh Bank 3
Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: These registers are reserved; maintain these registers clear. 2: These registers are not implemented on the PIC16F870.
DS30569A-page 12
Preliminary
© 1999 Microchip Technology Inc.
PIC16F870/871
2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. The Special Function Registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral feature section.
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2)
Bank 0 00h(4) 01h 02h(4) 03h
(4)
INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --0x 0000 --0u 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
04h(4) 05h 06h 07h 08h(5) 09h
(5)
Indirect data memory address pointer -- -- PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read -- -- GIE PSPIF(3) -- -- -- PEIE ADIF -- -- -- T0IE RCIF -- -- -- RE2 RE1 RE0
---- -xxx ---- -uuu ---0 0000 ---0 0000 0000 000x 0000 000u 0000 -000 0000 -000 ---0 ---- ---0 ---xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
0Ah(1,4) 0Bh(4) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
Write Buffer for the upper 5 bits of the Program Counter INTE TXIF EEIF RBIE -- -- T0IF CCP1IF -- INTF TMR2IF -- RBIF TMR1IF --
Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register -- -- -- T1CKPS1 T1CKPS0 TOUTPS1 T1OSCEN TOUTPS0 T1SYNC TMR1CS TMR1ON Timer2 module's register TOUTPS3 TOUTPS2
--00 0000 --uu uuuu 0000 0000 0000 0000
TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG
Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- SPEN -- RX9 CCP1X SREN CCP1Y CREN CCP1M3 ADDEN CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --00 0000 0000 000x 0000 000x 0000 0000 0000 0000 0000 0000 0000 0000
USART Transmit Data Register USART Receive Data Register
ADRESH ADCON0
A/D Result Register High Byte ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/ DONE -- ADON
xxxx xxxx uuuu uuuu 0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as `0'.
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Preliminary
DS30569A-page 13
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TABLE 2-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2)
Bank 1 80h(4) 81h 82h(4) 83h(4) 84h(4) 85h 86h 87h 88h(5) 89h(5) 8Ah(1,4) 8Bh(4) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh -- -- -- TXSTA SPBRG -- -- -- -- ADRESL ADCON1 Unimplemented Unimplemented Unimplemented CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D Baud Rate Generator Register Unimplemented Unimplemented Unimplemented Unimplemented A/D Result Register Low Byte ADFM -- -- -- PCFG3 PCFG2 PCFG1 PCFG0 -- -- -- -- -- -- PR2 Timer2 Period Register 1111 1111 1111 1111 INDF OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2 PCON -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 PD Z DC C 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --11 1111 --11 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 PSPMODE -- PORTE Data Direction Bits 0000 -111 0000 -111 ---0 0000 ---0 0000 0000 000x 0000 000u 0000 -000 0000 -000 ---0 ---- ---0 ------- --qq ---- --uu -- -- -- --
Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO
Indirect data memory address pointer -- -- PORTA Data Direction Register PORTB Data Direction Register PORTC Data Direction Register PORTD Data Direction Register IBF -- GIE PSPIE -- -- Unimplemented Unimplemented
(3)
OBF -- PEIE ADIE -- --
IBOV -- T0IE RCIE -- --
Write Buffer for the upper 5 bits of the Program Counter INTE TXIE EEIE -- RBIE -- -- -- T0IF CCP1IE -- -- INTF TMR2IE -- POR RBIF TMR1IE -- BOR
0000 -010 0000 -010 0000 0000 0000 0000 -- -- -- -- 0--- 0000 -- -- -- -- 0--- 0000
xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as `0'.
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TABLE 2-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2)
0000 0000
Bank 2 100h(4) 101h 102h(4) 103h(4) 104h(4) 105h 106h 107h 108h 109h 10Ah(1,4) 10Bh(4) 10Ch 10Dh 10Eh 10Fh Bank 3 180h(4) 181h 182h(4) 183h(4) 184h(4) 185h 186h 187h 188h 189h 18Ah(1,4) 18Bh(4) 18Ch 18Dh 18Eh 18Fh INDF OPTION_REG PCL STATUS FSR -- TRISB -- -- -- PCLATH INTCON EECON1 EECON2 -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 PD Z DC C 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu -- -- -- -- -- PEIE -- -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE WRERR T0IF WREN INTF WR RBIF RD -- -- -- -- INDF TMR0 PCL STATUS FSR -- PORTB -- -- -- PCLATH INTCON EEDATA EEADR EEDATH EEADRH Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C 0000 0000
xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu -- -- -- -- -- -- -- --
Indirect data memory address pointer Unimplemented PORTB Data Latch when written: PORTB pins when read Unimplemented Unimplemented Unimplemented -- GIE -- PEIE -- T0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE T0IF INTF RBIF
xxxx xxxx uuuu uuuu
---0 0000 ---0 0000 0000 000x 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
EEPROM data register EEPROM address register -- -- -- -- EEPROM data register high byte -- EEPROM address register high byte
Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO
Indirect data memory address pointer Unimplemented PORTB Data Direction Register Unimplemented Unimplemented Unimplemented -- GIE EEPGD
1111 1111 1111 1111
---0 0000 ---0 0000 0000 000x 0000 000u x--- x000 x--- u000 ---- ---- ---- ---0000 0000 0000 0000 0000 0000 0000 0000
EEPROM control register2 (not a physical register) Reserved maintain clear Reserved maintain clear
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as `0'.
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Preliminary
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2.2.2.1 STATUS REGISTER The STATUS Register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS Register can be the destination for any instruction, as with any other register. If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable, therefore, the result of an instruction with the STATUS Register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the STATUS Register. For other instructions not affecting any status bits, see the "Instruction Set Summary." Note 1: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 IRP bit7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n= Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
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2.2.2.2 OPTION_REG REGISTER Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. The OPTION_REG Register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1 RBPU bit7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n= Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
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2.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON Register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 GIE bit7 R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n= Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
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2.2.2.4 PIE1 REGISTER Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. The PIE1 Register contains the individual enable bits for the peripheral interrupts.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0 PSPIE bit7
(1)
R/W-0 ADIE
R/W-0 RCIE
R/W-0 TXIE
U-0
R/W-0 CCP1IE
R/W-0
R/W-0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n= Value at POR reset
TMR2IE TMR1IE
bit 7:
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt Unimplemented: Read as `0' CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt
bit 6:
bit 5:
bit 4:
bit 3: bit 2:
bit 1:
bit 0:
Note 1: PSPIE is reserved on the PIC16F870; always maintain this bit clear.
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Preliminary
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2.2.2.5 PIR1 REGISTER Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt. The PIR1 Register contains the individual flag bits for the peripheral interrupts.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
R/W-0 PSPIF(1) bit7
bit 7:
R/W-0 ADIF
R-0 RCIF
R-0 TXIF
U-0
R/W-0 CCP1IF
R/W-0
R/W-0 bit0 R = Readable bit W = Writable bit - n= Value at POR reset
TMR2IF TMR1IF
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full 0 = The USART receive buffer is empty TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty 0 = The USART transmit buffer is full Unimplemented: Read as `0' CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred
bit 6:
bit 5:
bit 4:
bit 7: bit 2:
bit 1:
TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: PSPIF is reserved on the PIC16F870; always maintain this bit clear.
bit 0:
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2.2.2.6 PIE2 REGISTER The PIE2 Register contains the individual enable bit for the EEPROM write operation interrupt.
REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)
U-0 -- bit7 U-0 -- U-0 -- R/W-0 EEIE U-0 -- U-0 -- U-0 -- U-0 -- bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n= Value at POR reset
bit 7-5: Unimplemented: Read as '0' bit 4: EEIE: EEPROM Write Operation Interrupt Enable 1 = Enable EE Write Interrupt 0 = Disable EE Write Interrupt
bit 3-0: Unimplemented: Read as '0'
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Preliminary
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2.2.2.7 PIR2 REGISTER
.
The PIR2 Register contains the flag bit for the EEPROM write operation interrupt.
Note:
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
U-0 -- bit7 U-0 -- U-0 -- R/W-0 EEIF U-0 -- U-0 -- U-0 -- U-0 -- bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n= Value at POR reset
bit 7-5: Unimplemented: Read as '0' bit 4: EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started
bit 3-0: Unimplemented: Read as '0'
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2.2.2.8 PCON REGISTER Note: The Power Control (PCON) Register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watch-dog Reset (WDT) and an external MCLR Reset. BOR is unknown on POR. It must be set by the user and checked on subsequent rests to see if BOR is clear, indicating a brownout has occurred. The BOR status bit is a don't care and is not predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the configuration word).
REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)
U-0 -- bit7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-1 BOR bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n= Value at POR reset
bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
bit 0:
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Preliminary
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2.3 PCL and PCLATH
The Program Counter (PC) is 13-bits wide. The low byte comes from the PCL Register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any reset, the upper bits of the PC will be cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.
2.4
Program Memory Paging
FIGURE 2-3:
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 8 7 0 Instruction with PCL as Destination ALU
PCH 12 PC 5
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO,CALL
The PIC16FXXX architecture is capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide 11 bits of the address, which allows branches within any 2K program memory page. Therefore, the 8K words of program memory are broken into four pages. Since the PIC16F872 has only 2K words of program memory or one page, additional code is not required to ensure that the correct page is selected before a CALL or GOTO instruction is executed. The PCLATH<4:3> bits should always be maintained as zeros. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack. Manipulation of the PCLATH is not required for the return instructions.
2.5
Indirect Addressing, INDF and FSR Registers
The INDF Register is not a physical register. Addressing the INDF Register will cause indirect addressing. Indirect addressing is possible by using the INDF Register. Any instruction using the INDF Register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF Register itself indirectly (FSR = '0') will read 00h. Writing to the INDF Register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR Register and the IRP bit (STATUS<7>), as shown in Figure 2-4. A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-1.
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note, "Implementing a Table Read" (AN556). 2.3.2 STACK
EXAMPLE 2-1:
movlw movwf clrf incf btfss goto :
INDIRECT ADDRESSING
0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
The PIC16FXXX family has an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN,RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).
NEXT
CONTINUE
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FIGURE 2-4: DIRECT/INDIRECT ADDRESSING
Direct Addressing RP1:RP0 6 from opcode 0 IRP Indirect Addressing 7 FSR register 0
bank select
location select 00 00h 01 80h 10 100h 11 180h
bank select
location select
Data Memory(1)
7Fh Bank 0 Note 1:
FFh Bank 1
17Fh Bank 2
1FFh Bank 3
For register file map detail see Figure 2-2.
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NOTES:
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3.0 I/O PORTS
FIGURE 3-1:
Data Bus
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023).
BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS
Q VDD
D
WR Port
CK
Q
P
Data Latch
3.1
PORTA and the TRISA Register
WR TRIS
D
Q
N
I/O pin(1)
PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA Register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other PORTA pins have TTL input levels and full CMOS output drivers. Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 Register (A/D Control Register1). Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
CK
Q
TRIS Latch
VSS Analog Input Mode
RD TRIS
TTL Input Buffer D
Q
EN
RD PORT
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 3-2:
Data Bus WR PORT
BLOCK DIAGRAM OF RA4/ T0CKI PIN
D Q Q N
The TRISA Register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA Register are maintained set when using them as analog inputs.
CK
I/O pin(1)
Data Latch D Q Q VSS Schmitt Trigger Input Buffer
EXAMPLE 3-1:
BCF BCF CLRF
INITIALIZING PORTA
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Bank0 Initialize PORTA by clearing output data latches Select Bank 1 Configure all pins as digital inputs Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs TRISA<7:6> are always read as '0'.
STATUS, RP0 STATUS, RP1 PORTA
WR TRIS
CK
TRIS Latch
BSF MOVLW MOVWF MOVLW
STATUS, RP0 0x06 ADCON1 0xCF
RD TRIS Q D EN EN RD PORT
MOVWF
TRISA
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
© 1999 Microchip Technology Inc.
Preliminary
DS30569A-page 27
PIC16F870/871
TABLE 3-1:
Name RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4
PORTA FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 Buffer TTL TTL TTL TTL ST TTL Input/output or analog input Input/output or analog input Input/output or analog input Input/output or analog input or VREF Input/output or external clock input for Timer0 Output is open drain type Input/output or analog input Function
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets
05h 85h 9Fh
PORTA TRISA
-- --
-- -- --
RA5 --
RA4 --
RA3
RA2
RA1
RA0
--0x 0000 --0u 0000 --11 1111 --11 1111
PORTA Data Direction Register
ADCON1 ADFM
PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
DS30569A-page 28
Preliminary
© 1999 Microchip Technology Inc.
PIC16F870/871
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Three pins of PORTB are multiplexed with the Low Voltage Programming function; RB3/PGM, RB6/PGC and RB7/PGD. The alternate functions of these pins are described in the Special Features Section. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature. This interrupt on mismatch feature, together with software configurable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key-depression. Refer to the Embedded Control Handbook, "Implementing Wake-Up on Key Stroke" (AN552). RB0/INT is an external interrupt input pin and is configured using the INTEDG bit (OPTION_REG<6>). RB0/INT is discussed in detail in Section 11.10.1.
FIGURE 3-3:
RBPU(2)
BLOCK DIAGRAM OF RB3:RB0 PINS
VDD weak P pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1)
Data Bus WR Port
FIGURE 3-4:
BLOCK DIAGRAM OF RB7:RB4 PINS
VDD weak P pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1)
RBPU(2) TTL Input Buffer
WR TRIS
CK
Data Bus WR Port
RD TRIS Q RD Port D WR TRIS EN
CK
TTL Input Buffer
ST Buffer
RB0/INT RB3/PGM Schmitt Trigger Buffer Note 1: 2: RD Port
RD TRIS Q RD Port Set RBIF
Latch D EN Q1
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).
From other RB7:RB4 pins
Q
D RD Port EN Q3
RB7:RB6 in serial programming mode Note 1: 2: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
© 1999 Microchip Technology Inc.
Preliminary
DS30569A-page 29
PIC16F870/871
TABLE 3-3:
Name RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD
PORTB FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer TTL/ST(1) TTL TTL TTL/ST TTL TTL TTL/ST(2) TTL/ST(2)
(1)
Function Input/output pin or external interrupt input. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin or programming pin in LVP mode. Internal software programmable weak pull-up. Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Input/output pin (with interrupt on change) or In-Circuit Debugger pin. Internal software programmable weak pull-up. Serial programming clock. Input/output pin (with interrupt on change) or In-Circuit Debugger pin. Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or LVP mode. 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 3-4:
Address 06h, 106h 86h, 186h 81h, 181h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 RB7 RBPU Bit 6 RB6 INTEDG Bit 5 RB5 T0CS Bit 4 RB4 T0SE Bit 3 RB3 PSA Bit 2 RB2 PS2 Bit 1 RB1 PS1 Bit 0 RB0 PS0 Value on: POR, BOR Value on all other resets
PORTB TRISB OPTION_REG
xxxx xxxx uuuu uuuu 1111 1111 1111 1111 1111 1111 1111 1111
PORTB Data Direction Register
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS30569A-page 30
Preliminary
© 1999 Microchip Technology Inc.
PIC16F870/871
3.3 PORTC and the TRISC Register
PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions (Table 3-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.
FIGURE 3-5:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
PORT/PERIPHERAL Select(2) Peripheral Data Out Data Bus WR PORT 0 D CK Q 1 Q VDD P
Data Latch WR TRIS D CK Q Q N VSS RD TRIS Peripheral OE(3) RD PORT Peripheral Input Q D EN Schmitt Trigger I/O pin(1)
TRIS Latch
Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active.
© 1999 Microchip Technology Inc.
Preliminary
DS30569A-page 31
PIC16F870/871
TABLE 3-5:
Name RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3 RC4 RC5 RC6/TX/CK RC7/RX/DT
PORTC FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output port pin or Timer1 oscillator output/Timer1 clock input Input/output port pin or Timer1 oscillator input Input/output port pin or Capture1 input/Compare1 output/PWM1 output Input/output port pin Input/output port pin Input/output port pin Input/output port pin or USART Asynchronous Transmit or Synchronous Clock Input/output port pin or USART Asynchronous Receive or Synchronous Data
Legend: ST = Schmitt Trigger input
TABLE 3-6:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR
xxxx xxxx 1111 1111
Name
Value on all other resets
uuuu uuuu 1111 1111
07h 87h
PORTC TRISC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
PORTC Data Direction Register
Legend: x = unknown, u = unchanged.
DS30569A-page 32
Preliminary
© 1999 Microchip Technology Inc.
PIC16F870/871
3.4 PORTD and TRISD Registers FIGURE 3-6:
Data Bus WR PORT
This section is not applicable to the PIC16F870. PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
D
PORTD BLOCK DIAGRAM (IN I/O PORT MODE)
Q I/O pin(1) CK
Data Latch D WR TRIS Q Schmitt Trigger Input Buffer
CK TRIS Latch
RD TRIS Q D EN EN RD PORT Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 3-7:
Name RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7
PORTD FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL
(1)
Function Input/output port pin or parallel slave port bit0 Input/output port pin or parallel slave port bit1 Input/output port pin or parallel slave port bit2 Input/output port pin or parallel slave port bit3 Input/output port pin or parallel slave port bit4 Input/output port pin or parallel slave port bit5 Input/output port pin or parallel slave port bit6 Input/output port pin or parallel slave port bit7
ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1)
Legend: ST = Schmitt Trigger input TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.
TABLE 3-8:
Address 08h 88h 89h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name Bit 7 RD7 IBF Bit 6 RD6 OBF Bit 5 RD5 IBOV Bit 4 RD4 PSPMODE Bit 3 RD3 -- Bit 2 RD2 Bit 1 RD1 Bit 0 RD0 Value on: POR, BOR xxxx xxxx 1111 1111 PORTE Data Direction Bits 0000 -111 Value on all other resets uuuu uuuu 1111 1111 0000 -111
PORTD TRISD TRISE
PORTD Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
© 1999 Microchip Technology Inc.
Preliminary
DS30569A-page 33
PIC16F870/871
3.5 PORTE and TRISE Register FIGURE 3-7:
Data Bus WR PORT
This section is not applicable to the PIC16F870. PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs). Ensure ADCON1 is configured for digital I/O. In this mode, the input buffers are TTL. Register 3-1 shows the TRISE Register, which also controls the parallel slave port operation. PORTE pins are multiplexed with analog inputs. When selected as an analog input, these pins will read as '0's. TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a Power-on Reset, these pins are configured as analog inputs.
PORTE BLOCK DIAGRAM (IN I/O PORT MODE)
D Q I/O pin(1) CK
Data Latch D WR TRIS Q Schmitt Trigger input buffer
CK TRIS Latch
RD TRIS Q D EN RD PORT Note 1: I/O pins have protection diodes to VDD and VSS.
REGISTER 3-1: TRISE REGISTER (ADDRESS 89h)
R-0 IBF bit7 R-0 OBF R/W-0 IBOV R/W-0 PSPMODE U-0 -- R/W-1 bit2 R/W-1 bit1 R/W-1 bit0 bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n= Value at POR reset
Parallel Slave Port Status/Control Bits
bit 7 : IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read IBOV: Input Buffer Overflow Detect bit (in microproces