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PIC16F62X
FLASH-Based 8-Bit CMOS Microcontrollers
Devices included in this data sheet:
· PIC16F627 · PIC16F628 Referred to collectively as PIC16F62X .
Special Microcontroller Features:
· Power-on Reset (POR) · Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) · Brown-out Detect (BOD) · Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation · Multiplexed MCLR-pin · Programmable weak pull-ups on PORTB · Programmable code protection · Low voltage programming · Power saving SLEEP mode · Selectable oscillator options - FLASH configuration bits for oscillator options - ER (External Resistor) oscillator - Reduced part count - Dual speed INTRC - Lower current consumption - EC External Clock input - XT oscillator mode - HS oscillator mode - LP oscillator mode · Serial in-circuit programming (via two pins) · Four user programmable ID locations
High Performance RISC CPU:
· Only 35 instructions to learn · All single-cycle instructions (200 ns), except for program branches which are two-cycle · Operating speed: - DC - 20 MHz clock input - DC - 200 ns instruction cycle
Memory Device PIC16F627 PIC16F628 FLASH Program 1024 x 14 2048 x 14 RAM Data 224 x 8 224 x 8 EEPROM Data 128 x 8 128 x 8
· · · ·
Interrupt capability 16 special function hardware registers 8-level deep hardware stack Direct, Indirect and Relative addressing modes
Peripheral Features:
· 15 I/O pins with individual direction control · High current sink/source for direct LED drive · Analog comparator module with: - Two analog comparators - Programmable on-chip voltage reference (VREF) module - Programmable input multiplexing from device inputs and internal voltage reference - Comparator outputs are externally accessible · Timer0: 8-bit timer/counter with 8-bit programmable prescaler · Timer1: 16-bit timer/counter with external crystal/ clock capability · Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler · Capture, Compare, PWM (CCP) module - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit · Universal Synchronous/Asynchronous Receiver/ Transmitter USART/SCI · 16 Bytes of common RAM
CMOS Technology:
· Low-power, high-speed CMOS FLASH technology · Fully static design · Wide operating voltage range - PIC16F627 - 3.0V to 5.5V - PIC16F628 - 3.0V to 5.5V - PIC16LF627 - 2.0V to 5.5V - PIC16LF628 - 2.0V to 5.5V · Commercial, industrial and extended temperature range · Low power consumption - < 2.0 mA @ 5.0V, 4.0 MHz - 15 µA typical @ 3.0V, 32 kHz - < 1.0 µA typical standby current @ 3.0V
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 1
PIC16F62X
Pin Diagrams
PDIP, SOIC
RA2/AN2/VREF RA3/AN3/CMP1 RA4/TOCKI/CMP2 RA5/MCLR/THV VSS RB0/INT RB1/RX/DT RB2/TX/CK RB3/CCP1
·1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
RA1/AN1 RA0/AN0 RA7/OSC1/CLKIN RA6/OSC2/CLKOUT VDD RB7/T1OSI RB6/T1OSO/T1CKI RB5 RB4/PGM
PIC16F62X
SSOP
RA2/AN2/VREF RA3/AN3/CMP1 RA4/TOCKI/CMP2 RA5/MCLR/THV VSS VSS RB0/INT RB1/RX/DT RB2/TX/CK RB3/CCP1
·1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
RA1/AN1 RA0/AN0 RA7/OSC1/CLKIN RA6/OSC2/CLKOUT VDD VDD RB7/T1OSI RB6/T1OSO/T1CKI RB5 RB4/PGM
PIC16F62X
Device Differences
Device PIC16F627 PIC16F628 PIC16LF627 PIC16LF628 Voltage Range 3.0 - 5.5 3.0 - 5.5 2.0 - 5.5 2.0 - 5.5 Oscillator See Note 1 See Note 1 See Note 1 See Note 1 Process Technology (Microns) 0.7 0.7 0.7 0.7
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
DS40300B-page 2
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
Table of Contents
1.0 General Description..................................................................................................................................................................... 5 2.0 PIC16F62X Device Varieties...................................................................................................................................................... 7 3.0 Architectural Overview ................................................................................................................................................................ 9 4.0 Memory Organization ................................................................................................................................................................ 13 5.0 I/O Ports .................................................................................................................................................................................... 27 6.0 Timer0 Module .......................................................................................................................................................................... 45 7.0 Timer1 Module .......................................................................................................................................................................... 50 8.0 Timer2 Module .......................................................................................................................................................................... 54 9.0 Comparator Module................................................................................................................................................................... 57 10.0 Capture/Compare/PWM (CCP) Module .................................................................................................................................... 63 11.0 Voltage Reference Module........................................................................................................................................................ 69 12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART).................................................................................... 71 13.0 Data EEPROM Memory ............................................................................................................................................................ 91 14.0 Special Features of the CPU..................................................................................................................................................... 95 15.0 Instruction Set Summary ......................................................................................................................................................... 113 16.0 Development Support.............................................................................................................................................................. 125 17.0 Electrical Specifications........................................................................................................................................................... 131 18.0 Device Characterization Information ....................................................................................................................................... 145 19.0 Packaging Information............................................................................................................................................................. 147 Index .................................................................................................................................................................................................. 151 On-Line Support................................................................................................................................................................................. 155 Reader Response .............................................................................................................................................................................. 156 PIC16F62X Product Identification System ........................................................................................................................................ 157
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Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: · Microchip's Worldwide Web site; http://www.microchip.com · Your local Microchip sales office (see last page) · The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: · Fill out and mail in the reader response form in the back of this data sheet. · E-mail us at [email protected]. We appreciate your assistance in making this a better document.
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 3
PIC16F62X
NOTES:
DS40300B-page 4
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
1.0 GENERAL DESCRIPTION
1.1 Development Support
The PIC16F62X are 18-Pin FLASH-based members of the versatile PIC16CXX family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers. All PICmicro® microcontrollers employ an advanced RISC architecture. The PIC16F62X have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two-stage instruction pipeline allows all instructions to execute in a single-cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16F62X microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. PIC16F62X devices have special features to reduce external components, thus reducing system cost, enhancing system reliability and reducing power consumption. There are eight oscillator configurations, of which the single pin ER oscillator provides a low-cost solution. The LP oscillator minimizes power consumption, XT is a standard crystal, INTRC is a self-contained internal oscillator and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power savings. The user can wake up the chip from SLEEP through several external and internal interrupts and reset. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lock- up. Table 1-1 shows the features of the PIC16F62X mid-range microcontroller families. A simplified block diagram of the PIC16F62X is shown in Figure 3-1. The PIC16F62X series fits in applications ranging from battery chargers to low-power remote sensors. The FLASH technology makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series ideal for all applications with space limitations. Low-cost, low-power, high-performance, ease of use and I/O flexibility make the PIC16F62X very versatile. The PIC16F62X family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. A Third Party "C" compiler support tool is also available.
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 5
PIC16F62X
TABLE 1-1: PIC16F62X FAMILY OF DEVICES
PIC16F627 Clock Maximum Frequency of Operation (MHz) 20 20 2048 224 128
PIC16F628 20 1024 224 128
PIC16LF627 20
PIC16LF628
FLASH Program Memory (words) 1024 Memory RAM Data Memory (bytes) EEPROM Data Memory (bytes) Timer Module(s) Comparators(s) Peripherals 224 128
2048 224 128 TMR0, TMR1, TMR2 2 1 USART Yes 10 16 2.0-5.5 Yes 18-pin DIP, SOIC; 20-pin SSOP
TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 2 2 1 USART Yes 10 16 3.0-5.5 Yes 18-pin DIP, SOIC; 20-pin SSOP
TMR0, TMR1, TMR2 2 1 USART Yes 10 16 2.0-5.5 Yes 18-pin DIP, SOIC; 20-pin SSOP
Capture/Compare/PWM modules 1 Serial Communications Internal Voltage Reference Interrupt Sources I/O Pins Voltage Range (Volts) USART Yes 10 16 3.0-5.5 Yes 18-pin DIP, SOIC; 20-pin SSOP
Features
Brown-out Detect Packages
All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16F62X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS40300B-page 6
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
2.0 PIC16F62X DEVICE VARIETIES
A variety of frequency ranges and packaging options are available. Depending on application and production requirements the proper device option can be selected using the information in the PIC16F62X Product Identification System section at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number.
2.1
Flash Devices
These devices are offered in the lower cost plastic package, even though the device can be erased and reprogrammed. This allows the same device to be used for prototype development and pilot programs as well as production. A further advantage of the electrically-erasable Flash version is that it can be erased and reprogrammed in-circuit, or by device programmers, such as Microchip's PICSTART® Plus or PRO MATE® II programmers.
2.2
Quick-Turnaround-Production (QTP) Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who chose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are standard FLASH devices but with all program locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your Microchip Technology sales office for more details.
2.3
Serialized Quick-Turnaround-Production (SQTPSM) Devices
Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 7
PIC16F62X
NOTES:
DS40300B-page 8
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16F62X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16F62X uses a Harvard architecture, in which, program and data are accessed from separate memories using separate busses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory. Separating program and data memory further allows instructions to be sized differently than 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (35) execute in a single-cycle (200 ns @ 20 MHz) except for program branches. The Table below lists program memory (Flash, Data and EEPROM).
Memory Device PIC16F627 PIC16F628 PIC16LF627 PIC16LF628 FLASH Program 1024 x 14 2048 x 14 1024 x 14 2048 x 14 RAM Data 224 x 8 224 x 8 224 x 8 224 x 8 EEPROM Data 128 x 8 128 x 8 128 x 8 128 x 8
The PIC16F62X devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bit wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, bit in subtraction. See the SUBLW and SUBWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with a description of the device pins in Table 3-1. Two types of data memory are provided on the PIC16F62X devices. Non-volatile EEPROM data memory is provided for long term storage of data such as calibration values, look up table data, and any other data which may require periodic updating in the field. This data is not lost when power is removed. The other data memory provided is regular RAM data memory. Regular RAM data memory is provided for temporary storage of data during normal operation. It is lost when power is removed.
The PIC16F62X can directly or indirectly address its register files or data memory. All special function registers including the program counter are mapped in the data memory. The PIC16F62X have an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16F62X simple yet efficient. In addition, the learning curve is reduced significantly.
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 9
PIC16F62X
FIGURE 3-1: BLOCK DIAGRAM
13 FLASH Program Memory 8 Level Stack (13-bit) Program Bus 14 Instruction reg Direct Addr 7 Program Counter
Data Bus
8
RAM File Registers
Data EEPROM
RAM Addr (1)
9
PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3/CMP1 RA4/T0CK1/CMP2 RA5/MCLR/THV RA6/OSC2/CLKOUT RA7/OSC1/CLKIN
Addr MUX 8 Indirect Addr
FSR reg STATUS reg 8 3 PORTB
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Detect Low-Voltage Programming 8
MUX
ALU
W reg
RB0/INT RB1/RX/DT RB2/TX/CK RB3/CCP1 RB4/PGM RB5 RB6/T1OSO/T1CKI RB7/T1OSI
MCLR
VDD, VSS
Comparator
Timer0
Timer1
Timer2
VREF
CCP1
USART
Memory Device
PIC16F627 PIC16F628 PIC16LF627 PIC16LF628
FLASH Program
1024 x 14 2048 x 14 1024 x 14 2048 x 14
RAM Data
224 x 8 224 x 8 224 x 8 224 x 8
EEPROM Data
128 x 8 128 x 8 128 x 8 128 x 8
Note 1: Higher order bits are from the STATUS register.
DS40300B-page 10
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
TABLE 3-1:
Name
RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3/CMP1 RA4/T0CKI/CMP2 RA5/MCLR/THV
PIC16F62X PINOUT DESCRIPTION
DIP/ SOIC Pin # 17 18 1 2 3 4 SSOP Pin # 19 20 1 2 3 4 I/O/P Type I/O I/O I/O I/O I/O I Buffer Type ST ST ST ST ST ST
Description
Bi-directional I/O port/Analog comparator input Bi-directional I/O port/Analog comparator input Bi-directional I/O port/Analog comparator input/VREF output Bi-directional I/O port/Analog comparator input/comparator output Bi-directional I/O port/Can be configured as T0CKI/comparator output Input port/master clear (reset input/programming voltage input. When configured as MCLR, this pin is an active low reset to the device. Voltage on MCLR/THV must not exceed VDD during normal device operation. Bi-directional I/O port/Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In ER mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Bi-directional I/O port/Oscillator crystal input/external clock source input. ER biasing pin. Bi-directional I/O port/external interrupt. Can be software programmed for internal weak pull-up. Bi-directional I/O port/ USART receive pin/synchronous data I/O. Can be software programmed for internal weak pull-up. Bi-directional I/O port/ USART transmit pin/synchronous clock I/O. Can be software programmed for internal weak pull-up. Bi-directional I/O port/Capture/Compare/PWM I/O. Can be software programmed for internal weak pull-up. Bi-directional I/O port/Low voltage programming input pin. Wake-up from SLEEP on pin change. Can be software programmed for internal weak pull-up. When low voltage programming is enabled, the interrupt on pin change and weak pull-up resistor are disabled. Bi-directional I/O port/Wake-up from SLEEP on pin change. Can be software programmed for internal weak pull-up. Bi-directional I/O port/Timer1 oscillator output/Timer1 clock input. Wake up from SLEEP on pin change. Can be software programmed for internal weak pull-up. Bi-directional I/O port/Timer1 oscillator input. Wake up from SLEEP on pin change. Can be software programmed for internal weak pull-up. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
RA6/OSC2/CLKOUT
15
17
I/O
ST
RA7/OSC1/CLKIN RB0/INT RB1/RX/DT
16 6 7
18 7 8
I/O I/O I/O
ST TTL/ST(1) TTL/ST(3)
RB2/TX/CK
8
9
I/O
TTL/ST(3)
RB3/CCP1 RB4/PGM
9 10
10 11
I/O I/O
TTL/ST(4) TTL/ST(5)
RB5
11
12
I/O
TTL
RB6/T1OSO/T1CKI
12
13
I/O
TTL/ST(2)
RB7/T1OSI
13
14
I/O
TTL/ST(2)
VSS VDD
5 14
5,6 15,16
P P
-- --
Legend:
Note 1: Note 2: Note 3: Note 4: Note 5:
O = output I/O = input/output P = power -- = Not used I = Input ST = Schmitt Trigger input TTL = TTL input I/OD =input/open drain output This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger I/O when used in USART/Synchronous mode. This buffer is a Schmitt Trigger I/O when used in CCP mode. This buffer is a Schmitt Trigger input when used in low voltage program mode.
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 11
PIC16F62X
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (OSC1/CLKIN/RA7 pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2. An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register (IR)" in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1 OSC1 Q1 Q2 Q3 Q4 PC
PC PC+1 PC+2 Internal phase clock
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC2/CLKOUT (ER mode)
Fetch INST (PC) Execute INST (PC-1)
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
1. MOVLW 55h 2. MOVWF PORTB 3. CALL 4. BSF SUB_1
INSTRUCTION PIPELINE FLOW
Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1
PORTA, BIT3
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
DS40300B-page 12
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
4.0
4.1
MEMORY ORGANIZATION
Program Memory Organization
FIGURE 4-2: PROGRAM MEMORY MAP AND STACK FOR THE PIC16F628
PC<12:0>
CALL, RETURN RETFIE, RETLW
The PIC16F62X has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h - 03FFh) for the PIC16F627 and 2K x 14 (0000h - 07FFh) for the PIC16F628 are physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 1K x 14 space (PIC16F627) or 2K x 14 space (PIC16F628). The reset vector is at 0000h and the interrupt vector is at 0004h (Figure 4-1 and Figure 4-2).
13
Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 000h
FIGURE 4-1:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16F627
PC<12:0>
Interrupt Vector
CALL, RETURN RETFIE, RETLW
13 On-chip Program Memory
0004 0005
Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector
07FFh 0800h
1FFFh 000h
4.2
Interrupt Vector 0004 0005
Data Memory Organization
On-chip Program Memory 03FFh 0400h
The data memory (Figure 4-3) is partitioned into four Banks which contain the general purpose registers and the special function registers. The Special Function Registers are located in the first 32 locations of each Bank. Register locations 20-7Fh, A0h-FFh, 120h-14Fh, 170h-17Fh and 1F0h-1FFh are general purpose registers implemented as static RAM. The Table below lists how to access the four banks of registers:
RP1 Bank0 Bank1 Bank2 Bank3 0 0 1 1 RP0 0 1 0 1
1FFFh
Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are implemented as common RAM and mapped back to addresses 70h-7Fh. 4.2.1 GENERAL PURPOSE REGISTER FILE
The register file is organized as 224 x 8 in the PIC16F62X. Each is accessed either directly or indirectly through the File Select Register FSR (Section 4.4).
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 13
PIC16F62X
FIGURE 4-3: DATA MEMORY MAP OF THE PIC16F627 AND PIC16F628
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh CMCON 1Fh 20h VRCON General Purpose Register 80 Bytes TXSTA SPBRG EEDATA EEADR EECON1 EECON2* PR2 PCON PCLATH INTCON PIE1 Indirect addr.(*) OPTION PCL STATUS FSR TRISA TRISB 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 48 Bytes 11Fh 120h 14Fh 150h 1EFh 1F0h accesses 70h - 7Fh 1FFh Bank 3 PCLATH INTCON PORTB Indirect addr.(*) TMR0 PCL STATUS FSR 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh PCLATH INTCON TRISB Indirect addr.(*) OPTION PCL STATUS FSR 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh
General Purpose Register 96 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 EFh F0h
accesses 70h-7Fh Bank 2
16Fh 170h
FFh
17Fh
Unimplemented data memory locations, read as '0'. * Not a physical register.
DS40300B-page 14
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
4.2.2 SPECIAL FUNCTION REGISTERS The special function registers are registers used by the CPU and Peripheral functions for controlling the desired operation of the device (Table 4-1). These registers are static RAM. The special registers can be classified into two sets (core and peripheral). The special function registers associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
TABLE 4-1:
Address Bank 0
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh INDF TMR0 PCL STATUS FSR PORTA
SPECIAL REGISTERS SUMMARY BANK0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset
xxxx xxxx xxxx xxxx 0000 0000 PD RA3 RB3 Z RA2 RB2 DC RA1 RB1 C RA0 RB0 0001 1xxx xxxx xxxx xxxx 0000 xxxx xxxx -- -- -- -- GIE EEIF -- PEIE CMIF -- T0IE RCIF Write buffer for upper 5 bits of program counter INTE TXIF RBIE -- T0IF CCP1IF INTF TMR2IF RBIF TMR1IF ---0 0000 0000 000x 0000 -000 -- xxxx xxxx xxxx xxxx TMR1CS TMR1ON --00 0000 0000 0000 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -- -- Capture/Compare/PWM register (LSB) Capture/Compare/PWM register (MSB) -- -- CCP1X CCP1Y SPEN RX9 SREN CREN USART Transmit data register USART Receive data register CCP1M3 ADEN CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D xxxx xxxx xxxx xxxx --00 0000 0000 -00x 0000 0000 0000 0000 -- -- -- C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 -- 0000 0000 TO
Value on all other Resets(1)
xxxx xxxx uuuu uuuu 0000 0000 000q quuu uuuu uuuu xxxx 0000 uuuu uuuu -- -- -- ---0 0000 0000 000u 0000 -000 -- uuuu uuuu uuuu uuuu --uu uuuu 0000 0000 -uuu uuuu -- -- uuuu uuuu uuuu uuuu --00 0000 0000 -00x 0000 0000 0000 0000 -- -- -- -- 0000 0000
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 Indirect data memory address pointer RA7 RA6 RA5 RA4 RB7 RB6 RB5 RB4
PORTB Unimplemented Unimplemented Unimplemented PCLATH INTCON PIR1 Unimplemented TMR1L TMR1H T1CON TMR2 T2CON Unimplemented Unimplemented CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG Unimplemented Unimplemented Unimplemented Unimplemented CMCON
Holding register for the least significant byte of the 16-bit TMR1 Holding register for the most significant byte of the 16-bit TMR1 -- -- -- TOUTPS3 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR2 module's register
Legend: -- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 15
PIC16F62X
TABLE 4-2:
Address
Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh INDF OPTION PCL STATUS FSR TRISA TRISB Unimplemented Unimplemented Unimplemented PCLATH INTCON PIE1 Unimplemented PCON Unimplemented Unimplemented Unimplemented PR2 Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented TXSTA SPBRG EEDATA EEADR EECON1 EECON2 Unimplemented VRCON CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D Baud Rate Generator Register EEPROM data register -- -- EEPROM address register -- -- -- WRERR WREN WR RD Timer2 Period Register -- -- -- -- OSCF -- POR BOD -- GIE EEIE -- PEIE CMIE -- T0IE RCIE Write buffer for upper 5 bits of program counter INTE TXIE RBIE -- T0IF CCP1IE INTF TMR2IE RBIF TMR1IE Addressing this location uses contents of FSR to address data memory (not a physical reg- xxxx xxxx ister) INTEDG T0CS T0SE PSA RBPU Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO Indirect data memory address pointer TRISA7 TRISB7 TRISA6 TRISB6 -- TRISB5 TRISA4 TRISB4 PD TRISA3 TRISB3 PS2 Z TRISA2 TRISB2 PS1 DC TRISA1 TRISB1 PS0 C TRISA0 TRISB0 1111 1111 0000 0000 0001 1xxx xxxx xxxx 11-1 1111 1111 1111 -- -- -- ---0 0000 0000 000x 0000 -000 -- ---- 1-0x -- -- 11111111 -- -- -- -- -- 0000 -010 0000 0000 xxxx xxxx xxxx xxxx ---- x000 --------- VR2 VR1 VR0 000- 0000 xxxx xxxx 1111 1111 0000 0000 000q quuu uuuu uuuu 11-1 1111 1111 1111 -- -- -- ---0 0000 0000 000u 0000 -000 -- ---- 1-uq -- -- 11111111 -- -- -- -- -- 0000 -010 0000 0000 uuuu uuuu uuuu uuuu ---- q000 --------- 000- 0000
SPECIAL FUNCTION REGISTERS SUMMARY BANK1
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other resets(1)
EEPROM control register 2 (not a physical register) VREN VROE VRR -- VR3
Legend: : -- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
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Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
TABLE 4-3:
Address
Bank 1 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh Unimplemented INDF TMR0 PCL STATUS FSR Unimplemented PORTB Unimplemented Unimplemented Unimplemented PCLATH INTCON Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- GIE -- PEIE -- T0IE Write buffer for upper 5 bits of program counter INTE RBIE T0IF INTF RBIF TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 Addressing this location uses contents of FSR to address data memory (not a physical reg- xxxx xxxx ister) INTEDG T0CS T0SE PSA RBPU Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO Indirect data memory address pointer PD PS2 Z PS1 DC PS0 C 1111 1111 0000 0000 0001 1xxx xxxx xxxx -- 1111 1111 -- -- -- ---0 0000 0000 000x -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- xxxx xxxx 1111 1111 0000 0000 000q quuu uuuu uuuu -- 1111 1111 -- -- -- ---0 0000 0000 000u -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
SPECIAL FUNCTION REGISTERS SUMMARY BANK2
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other resets(1)
Legend: -- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 17
PIC16F62X
TABLE 4-4:
Address
Bank 1 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh INDF OPTION PCL STATUS FSR Unimplemented TRISB Unimplemented Unimplemented Unimplemented PCLATH INTCON -- GIE -- PEIE -- T0IE Write buffer for upper 5 bits of program counter INTE RBIE T0IF INTF RBIF TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 Addressing this location uses contents of FSR to address data memory (not a physical reg- xxxx xxxx ister) INTEDG T0CS T0SE PSA RBPU Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO Indirect data memory address pointer PD PS2 Z PS1 DC PS0 C 1111 1111 0000 0000 0001 1xxx xxxx xxxx -- 1111 1111 -- -- -- ---0 0000 0000 000x xxxx xxxx 1111 1111 0000 0000 000q quuu uuuu uuuu -- 1111 1111 -- -- -- ---0 0000 0000 000u
SPECIAL FUNCTION REGISTERS SUMMARY BANK3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other resets(1)
Legend: -- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
DS40300B-page 18
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
4.2.2.1 STATUS REGISTER The STATUS register, shown in Register 4-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory (SRAM). The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the status register as 000uu1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect any status bit. For other instructions, not affecting any status bits, see the "Instruction Set Summary". Note 1: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 4-1: STATUS REGISTER (ADDRESS 03H OR 83H)
R/W-0 IRP bit7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR reset -x = Unknown at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 19
PIC16F62X
4.2.2.2 OPTION REGISTER Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1). See Section 6.3.1 The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0, and the weak pull-ups on PORTB.
REGISTER 4-2: OPTION REGISTER (ADDRESS 81H)
R/W-1 RBPU bit7 bit 7: R/W-1 R/W-1 INTEDG T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0
R = Readable bit W = Writable bit -n = Value at POR reset
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
DS40300B-page 20
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
4.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). The INTCON register is a readable and writable register which contains the various enable and flag bits for all interrupt sources except the comparator module. See Section 4.2.2.4 and Section 4.2.2.5 for a description of the comparator enable and flag bits.
REGISTER 4-3: INTCON REGISTER (ADDRESS 0BH OR 8BH)
R/W-0 GIE bit7 R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR reset -x = Unknown at POR reset
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 21
PIC16F62X
4.2.2.4 PIE1 REGISTER This register contains interrupt enable bits.
REGISTER 4-4: PIE1 REGISTER (ADDRESS 8CH)
R/W-0 EEIE bit7 R/W-0 CMIE R/W-0 RCIE R/W-0 TXIE U R/W-0 CCP1IE R/W-0 R/W-0 TMR2IE TMR1IE bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR reset
bit 7:
EEIE: EE Write Complete Interrupt Enable Bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt Unimplemented: Read as `0' CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt
bit 6:
bit 5:
bit 4:
bit 3: bit 2:
bit 1:
bit 0:
DS40300B-page 22
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
4.2.2.5 PIR1 REGISTER Note: This register contains interrupt flag bits. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 4-5: PIR1 REGISTER (ADDRESS 0CH)
R/W-0 EEIF bit7 R/W-0 CMIF R-0 RCIF R-0 TXIF U R/W-0 CCP1IF R/W-0 R/W-0 TMR2IF TMR1IF bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR reset
bit 7:
EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed 0 = Comparator input has not changed RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full 0 = The USART receive buffer is empty TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty 0 = The USART transmit buffer is full Unimplemented: Read as `0' CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow
bit 6:
bit 5:
bit 4:
bit 3: bit 2:
bit 1:
bit 0:
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 23
PIC16F62X
4.2.2.6 PCON REGISTER The PCON register contains flag bits to differentiate between a Power-on Reset, an external MCLR reset, WDT reset or a Brown-out Detect.
Note: BOD is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOD is cleared, indicating a brown-out has occurred. The BOD status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (by programming BOREN bit in the Configuration word).
REGISTER 4-6: PCON REGISTER (ADDRESS 8Eh)
U-0 -- bit7 U-0 -- U-0 -- U-0 -- R/W-1 OSCF U-0 -- R/W-q POR R/W-q BOD bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR reset
bit 7-4,2: Unimplemented: Read as '0' bit 3: OSCF: INTRC/ER oscillator speed 1 = 4 MHz typical(1) 0 = 37 KHz typical POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOD: Brown-out Detect Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
bit 1:
bit 0:
Note 1: When in ER oscillator mode, setting OSCF = 1 will cause the oscillator speed to change to the speed specified by the external resistor.
DS40300B-page 24
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
4.3 PCL and PCLATH
4.3.2 STACK The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any reset, the PC is cleared. Figure 4-7 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The PIC16F62X family has an 8 level deep x 13-bit wide hardware stack (Figure 4-1 and Figure 4-2). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1:
Instruction with PCL as Destination ALU result
FIGURE 4-7:
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 8 7 0
PCH 12 PC 5
There are no STATUS bits to indicate stack overflow or stack underflow conditions. There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address.
PCLATH<4:0>
8
Note 2:
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note "Implementing a Table Read" (AN556).
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 25
PIC16F62X
4.4 Indirect Addressing, INDF and FSR Registers EXAMPLE 4-1:
movlw movwf NEXT clrf incf btfss goto CONTINUE:
INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the file select register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-8. A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 4-1.
FIGURE 4-8:
DIRECT/INDIRECT ADDRESSING PIC16F62X
Direct Addressing Indirect Addressing 0 IRP 7 FSR register 0
RP1
RP0
6
from opcode
bank select
location select 00 00h 01 10 11
bank select 180h
location select
Data Memory
7Fh
1FFh
Bank 0 For memory map detail see Figure 4-3.
Bank 1
Bank 2
Bank 3
DS40300B-page 26
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
5.0 I/O PORTS
The PIC16F62X have two ports, PORTA and PORTB. Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Note 1: On reset, the TRISA register is set to all inputs. The digital inputs are disabled and the comparator inputs are forced to ground to reduce excess current consumption. Note 2: When RA6/OSC2/CLKOUT is configured as CLKOUT, the corresponding TRIS bit is overridden and the pin is configured as an output. The PORTA data bit reads 0, and the PORTA TRIS bit reads 0. TRISA controls the direction of the RA pins, even when they are being used as comparator inputs. The user must make sure to keep the pins configured as inputs when using them as comparator inputs. The RA2 pin will also function as the output for the voltage reference. When in this mode, the VREF pin is a very high impedance output. The user must configure TRISA<2> bit as an input and use high impedance loads. In one of the comparator modes defined by the CMCON register, pins RA3 and RA4 become outputs of the comparators. The TRISA<4:3> bits must be cleared to enable outputs to use this function.
5.1
PORTA and TRISA Registers
PORTA is an 8-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. Port RA4 is multiplexed with the T0CKI clock input. RA5 is a Schmitt Trigger input only and has no output drivers. All other RA port pins have Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as input or output. A '1' in the TRISA register puts the corresponding output driver in a hi- impedance mode. A '0' in the TRISA register puts the contents of the output latch on the selected pin(s). Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. The PORTA pins are multiplexed with comparator and voltage reference functions. The operation of these pins are selected by control bits in the CMCON (comparator control register) register and the VRCON (voltage reference control register) register. When selected as a comparator input, these pins will read as '0's.
EXAMPLE 5-1:
CLRF PORTA MOVLW 0X07 MOVWF CMCON
INITIALIZING PORTA
;Initialize PORTA by setting ;output data latches ;Turn comparators off and ;enable pins for I/O ;functions
BCF STATUS, RP1 BSF STATUS, RP0 ;Select Bank1 MOVLW 0x1F ;Value used to initialize ;data direction MOVWF TRISA ;Set RA<4:0> as inputs ;TRISA<7:5> are always ;read as '0'.
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 27
PIC16F62X
FIGURE 5-1:
Data Bus WR PORTA
BLOCK DIAGRAM OF RA0/AN0:RA1/AN1 PINS
Q VDD VDD
FIGURE 5-2:
Data Bus WR PORTA
BLOCK DIAGRAM OF RA2/VREF PIN
Q VDD VDD
D
D
CK
Q
P D I/O Pin N WR TRISA VSS VSS Analog Input Mode Schmitt Trigger Input Buffer
CK
Q
P
Data Latch D WR TRISA Q
Data Latch Q N CK Q VSS Analog Input Mode Schmitt Trigger Input Buffer RA2 Pin VSS
CK
Q
TRIS Latch
TRIS Latch
RD TRISA
RD TRISA
Q
D
Q
D
EN RD PORTA RD PORTA
EN
To Comparator
To Comparator VROE VREF
DS40300B-page 28
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
FIGURE 5-3:
Data Bus WR PORTA D
BLOCK DIAGRAM OF THE RA3/AN3 PIN
Comparator Mode = 110 Q Comparator Output 1 CK Q 0 VDD P VDD
Data Latch D WR TRISA Q
N CK Q VSS Analog Input Mode Schmitt Trigger Input Buffer VSS
RA3 Pin
TRIS Latch
RD TRISA Q D
EN RD PORTA
To Comparator
FIGURE 5-4:
Data Bus WR PORTA D
BLOCK DIAGRAM OF RA4/T0CKI PIN
Comparator Mode = 110 Q Comparator Output 1 CK Q 0 Data Latch D Q N CK Q VSS VSS RA4 Pin
WR TRISA
TRIS Latch
RD TRISA Q D
Schmitt Trigger Input Buffer
EN RD PORTA
TMR0 Clock Input
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 29
PIC16F62X
FIGURE 5-5: BLOCK DIAGRAM OF THE RA5/MCLR/THV PIN
MCLRE MCLR circuit MCLR Filter(1) VDD
Program mode HV Detect RA5/MCLR/THV
Data Bus WR PORT
D
Q Q
VDD
VSS
CK
P
Data Latch D WR TRIS Q N CK Q TRIS Latch VSS
RD TRIS Q D
EN RD Port
DS40300B-page 30
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
FIGURE 5-6: BLOCK DIAGRAM OF RA6/OSC2/CLKOUT PIN
(Fosc=101,111)
CLKOUT (FOSC/4) 1 0
From OSC1
Oscillator Circuit VDD
Data Bus WR PORTA
D
Q
VDD
RA6/OSC2/CLKOUT Pin
CK
Q
P
VSS
Data Latch D Q N CK Q TRIS Latch VSS (Fosc=100, 101, 110, 111) RD TRISA Q D (Fosc=110, 100) Schmitt Trigger Input Buffer
WR TRISA
EN RD PORTA
CLKOUT is 1/4 of the Fosc frequency.
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 31
PIC16F62X
FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN
To OSC2 Oscillator Circuit VDD
CLKIN to core Data Bus WR PORTA D WR TRISA D Q Q VDD RA7/OSC1/CLKIN Pin CK P Schmitt Trigger VSS N CK Q (Fosc=101, 100) TRIS Latch VSS (Fosc=101, 100) RD TRISA Q D Schmitt Trigger Input Buffer
Data Latch Q
EN RD PORTA
DS40300B-page 32
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
TABLE 5-1:
Name RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3 RA4/T0CKI RA5/MCLR/THV
PORTA FUNCTIONS
Bit # bit0 bit1 bit2 bit3 bit4 bit5 Buffer Type ST ST ST ST ST ST Function Bi-directional I/O port/comparator input Bi-directional I/O port/comparator input Bi-directional I/O port/analog/comparator input or VREF output Bi-directional I/O port/analog/comparator input/comparator output Bi-directional I/O port/external clock input for TMR0 or comparator output. Output is open drain type. Input port/master clear (reset input/programming voltage input. When configured as MCLR, this pin is an active low reset to the device. Voltage on MCLR/THV must not exceed VDD during normal device operation. Bi-directional I/O port/Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In ER mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Bi-directional I/O port/oscillator crystal input/external clock source input.
RA6/OSC2/CLKOUT
bit6
ST
RA7/OSC1/CLKIN bit7 ST Legend: ST = Schmitt Trigger input
TABLE 5-2:
Address Name
05h 85h 1Fh 9Fh PORTA TRISA CMCON VRCON
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
RA7 TRISA7 C2OUT VREN
Bit 6
RA6 TRISA6 C1OUT VROE
Bit 5
RA5 -- C2INV VRR
Bit 4
RA4 TRISA4 C1INV --
Bit 3
RA3 TRISA3 CIS VR3
Bit 2
RA2 TRISA2 CM2 VR2
Bit 1
RA1 TRISA1 CM1 VR1
Bit 0
RA0 TRISA0 CM0 VR0
Value on POR
xxxx 0000 11-1 1111 0000 0000 000- 0000
Value on All Other Resets
xxxu 0000 11-1 1111 0000 0000 000- 0000
Legend: -- = Unimplemented locations, read as `0', u = unchanged, x = unknown Note: Shaded bits are not used by PORTA.
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 33
PIC16F62X
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. A '1' in the TRISB register puts the corresponding output driver in a high impedance mode. A '0' in the TRISB register puts the contents of the output latch on the selected pin(s). PORTB is multiplexed with the interrupt, USART, CCP module and the TMR1 clock input/output. The standard port functions and the alternate port functions are shown in Table 5-3. Reading PORTB register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. Each of the PORTB pins has a weak internal pull-up (200 µA typical). A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION<7>) bit. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on Power-on Reset. Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RBIF interrupt (flag latched in INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a key pad and make it possible for wake-up on key-depression. (See AN552 in the Microchip Embedded Control Handbook.) Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set.
The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.
DS40300B-page 34
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
FIGURE 5-8: BLOCK DIAGRAM OF RB0/INT PIN
VDD RBPU VDD weak P pull-up
RB0/INT pin Data Bus D Q VSS CK Data Latch
WR PORTB
D WR TRISB
Q TTL input buffer
CK TRIS Latch
Schmitt Trigger Buffer
RD TRISB Q D EN EN
RD PORTB
INT input
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 35
PIC16F62X
FIGURE 5-9: BLOCK DIAGRAM OF RB1/TX/DT PIN
VDD RBPU P weak pull-up PORT/PERIPHERAL Select(1) USART data output 0 VDD 1 Data Bus WR PORTB D Q Q P VDD
CK
Data Latch D WR TRISB Q Q N VSS VSS RB1/RX/DT pin
CK
TRIS Latch
RD TRISB Peripheral OE(2) Q RD PORTB EN USART receive input D
TTL input buffer
Schmitt Trigger
RD PORTB
Note 1: Port/Peripheral select signal selects between port data and peripheral output. Note 2: Peripheral OE( output enable) is only active if peripheral select is active.
DS40300B-page 36
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
FIGURE 5-10: BLOCK DIAGRAM OF RB2/TX/CK PIN
VDD P weak pull-up PORT/PERIPHERAL Select(1) USART TX/CK output 0 VDD 1 Data Bus WR PORTB D Q Q VSS Data Latch D WR TRISB Q Q N Vss P RB2/TX/CK pin VDD
RBPU
CK
CK
TRIS Latch
RD TRISB Peripheral OE(2) Q RD PORTB EN EN USART Slave Clock in D
TTL input buffer
Schmitt Trigger
RD PORTB
Note 1: Port/Peripheral select signal selects between port data and peripheral output. Note 2: Peripheral OE( output enable) is only active if peripheral select is active.
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 37
PIC16F62X
FIGURE 5-11: BLOCK DIAGRAM OF THE RB3/CCP1 PIN
VDD RBPU P weak pull-up Port/Peripheral Select(1) PWM/Compare output 0 VDD 1 Data Bus WR PORTB D Q Q P VDD
CK
Data Latch D WR TRISB Q N VSS TRIS Latch Vss RB3/CCP1 pin
CK
Q
RD TRISB
TTL input buffer Q D EN EN
RD PORTB
CCP input
Schmitt Trigger
RD PORTB
Note 1: Peripheral Select is defined by CCP1M3:CCP1M0. (CCP1CON<3:0>)
DS40300B-page 38
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
FIGURE 5-12: BLOCK DIAGRAM OF RB4/PGM PIN
VDD RBPU P weak pull-up
VDD Data Bus WR PORTB D Q Q P VDD
CK
Data Latch D WR TRISB Q Q N VSS TRIS Latch VSS RB4/PGM
CK
RD TRISB LVP
RD PORTB
PGM input Schmitt Trigger TTL input buffer Q D Q1
EN Set RBIF
From other RB<7:4> pins
Q
D RD Port EN Q3
Note:
The low voltage programming disables the interrupt on change and the weak pullups on RB4.
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 39
PIC16F62X
FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN
VDD RBPU weak VDD P pull-up
Data Bus
D
Q RB5 pin
WR PORTB
CK Data Latch VSS D Q
WR TRISB
CK TRIS Latch TTL input buffer
RD TRISB Q RD PORTB EN Set RBIF D Q1
From other RB<7:4> pins
Q
D RD Port Q3
EN
DS40300B-page 40
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN
VDD RBPU P weak pull-up VDD Data Bus WR PORTB D Q Q P
VDD
CK
Data Latch D WR TRISB Q Q N VSS TRIS Latch VSS RB6/ T1OSO/ T1CKI pin
CK
RD TRISB T1OSCEN TTL input buffer
RD PORTB
TMR1 Clock
From RB7 Serial programming clock
Schmitt Trigger TMR1 oscillator
Q
D Q1
EN Set RBIF
From other RB<7:4> pins
Q
D RD Port EN Q3
© 1999 Microchip Technology Inc.
Preliminary
DS40300B-page 41
PIC16F62X
FIGURE 5-15: BLOCK DIAGRAM OF THE RB7/T1OSI PIN
VDD RBPU P weak pull-up To RB6 T1OSCEN VDD VDD Data Bus WR PORTB D Q Q P RB7/T1OSI pin TMR1 oscillator
CK
Data Latch D WR TRISB Q Q N Vss VSS
CK
TRIS Latch
RD TRISB T10SCEN
RD PORTB
TTL input buffer
Serial programming input
Schmitt Trigger Q D Q1
EN Set RBIF
From other RB<7:4> pins
Q
D RD Port EN Q3
DS40300B-page 42
Preliminary
© 1999 Microchip Technology Inc.
PIC16F62X
TABLE 5-3:
Name
RB0/INT
PORTB FUNCTIONS
Bit # bit0 Buffer Type TTL/ST(1) Function
Bi-directional I/O port/external interrupt. Can be software programmed for internal weak pull-up. (3) RB1/RX/DT bit1 Bi-directional I/O port/ USART receive pin/synchronous data I/O. Can be TTL/ST software programmed for internal weak pull-up. (3) RB2/TX/CK bit2 Bi-directional I/O port/ USART transmit pin/synchronous clock I/O. Can be TTL/ST software programmed for internal weak pull-up. (4) RB3/CCP1 bit3 Bi-directional I/O port/Capture/Compare/PWM I/O. Can be software proTTL/ST grammed for internal weak pull-up. (5) RB4/PGM bit4 Bi-directional I/O port/Low voltage programming input pin. Wake-up from TTL/ST SLEEP on pin change. Can be software programmed for internal weak pull-up. When low voltage programming is enabled, the interrupt on pin change and weak pull-up resistor are disabled. RB5 bit5 TTL Bi-directional I/O port/Wake-up from SLEEP on pin change. Can be software programmed for internal weak pull-up. RB6/T1OSO/T1CKI bit6 TTL/ST(2) Bi-directional I/O port/Timer1 oscillator output/Timer1 clock input. Wake up from SLEEP on pin change. Can be software programmed for internal weak pull-up. RB7/T1OSI bit7 TTL/ST(2) Bi-directional I/O port/Timer1 oscillator input. Wake up from SLEEP on pin change. Can be software programmed for internal weak pull-up. Legend: ST = Schmitt Trigger, TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode. Note 3: Th