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Data Sheet
18-pin Enhanced FLASH/EEPROM
8-bit Microcontroller
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PIC16F84A Data Sheet
18-pin Enhanced FLASH/EEPROM 8-bit Microcontroller
© 2001 Microchip Technology Inc.
DS35007B
Note the following details of the code protection feature on PICmicro® MCUs. · · · The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product.
· · ·
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL, MPLAB and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Total Endurance, ICSP, In-Circuit Serial Programming, FilterLab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM, MPLINK, MPLIB, PICC, PICDEM, PICDEM.net, ICEPIC, Migratable Memory, FanSense, ECONOMONITOR, Select Mode and microPort are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Term Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2001, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
DS35007B - page ii
© 2001 Microchip Technology Inc.
M
PIC16F84A
Pin Diagrams
PDIP, SOIC
RA2 RA3 RA4/T0CKI MCLR VSS RB0/INT RB1 RB2 RB3 ·1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
18-pin Enhanced FLASH/EEPROM 8-Bit Microcontroller
High Performance RISC CPU Features:
· Only 35 single word instructions to learn · All instructions single-cycle except for program branches which are two-cycle · Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle · 1024 words of program memory · 68 bytes of Data RAM · 64 bytes of Data EEPROM · 14-bit wide instruction words · 8-bit wide data bytes · 15 Special Function Hardware registers · Eight-level deep hardware stack · Direct, indirect and relative addressing modes · Four interrupt sources: - External RB0/INT pin - TMR0 timer overflow - PORTB<7:4> interrupt-on-change - Data EEPROM write complete
PIC16F84A
SSOP
RA2 RA3 RA4/T0CKI MCLR VSS VSS RB0/INT RB1 RB2 RB3 ·1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4
PIC16F84A
Peripheral Features:
· 13 I/O pins with individual direction control · High current sink/source for direct LED drive - 25 mA sink max. per pin - 25 mA source max. per pin · TMR0: 8-bit timer/counter with 8-bit programmable prescaler
Special Microcontroller Features:
· 10,000 erase/write cycles Enhanced FLASH Program memory typical · 10,000,000 typical erase/write cycles EEPROM Data memory typical · EEPROM Data Retention > 40 years · In-Circuit Serial ProgrammingTM (ICSPTM) - via two pins · Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) · Watchdog Timer (WDT) with its own On-Chip RC Oscillator for reliable operation · Code protection · Power saving SLEEP mode · Selectable oscillator options
CMOS Enhanced FLASH/EEPROM Technology:
· Low power, high speed technology · Fully static design · Wide operating voltage range: - Commercial: 2.0V to 5.5V - Industrial: 2.0V to 5.5V · Low power consumption: - < 2 mA typical @ 5V, 4 MHz - 15 µA typical @ 2V, 32 kHz - < 0.5 µA typical standby current @ 2V
© 2001 Microchip Technology Inc.
DS35007B-page 1
PIC16F84A
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 3 2.0 Memory Organization ................................................................................................................................................................... 5 3.0 Data EEPROM Memory ............................................................................................................................................................. 13 4.0 I/O Ports ..................................................................................................................................................................................... 15 5.0 Timer0 Module ........................................................................................................................................................................... 19 6.0 Special Features of the CPU ...................................................................................................................................................... 21 7.0 Instruction Set Summary ............................................................................................................................................................ 35 8.0 Development Support................................................................................................................................................................. 43 9.0 Electrical Characteristics ............................................................................................................................................................ 49 10.0 DC/AC Characteristic Graphs .................................................................................................................................................... 61 11.0 Packaging Information................................................................................................................................................................ 71 Appendix A: Revision History .............................................................................................................................................................. 75 Appendix B: Conversion Considerations.............................................................................................................................................. 76 Appendix C: Migration from Baseline to Mid-Range Devices .............................................................................................................. 78 Index .................................................................................................................................................................................................... 79 On-Line Support................................................................................................................................................................................... 83 Reader Response ................................................................................................................................................................................ 84 PIC16F84A Product Identification System ........................................................................................................................................... 85
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Most Current Data Sheet
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: · Microchip's Worldwide Web site; http://www.microchip.com · Your local Microchip sales office (see last page) · The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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DS35007B-page 2
© 2001 Microchip Technology Inc.
PIC16F84A
1.0 DEVICE OVERVIEW
This document contains device specific information for the operation of the PIC16F84A device. Additional information may be found in the PICmicroTM MidRange Reference Manual, (DS33023), which may be downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC16F84A belongs to the mid-range family of the PICmicro® microcontroller devices. A block diagram of the device is shown in Figure 1-1. The program memory contains 1K words, which translates to 1024 instructions, since each 14-bit program memory word is the same width as each device instruction. The data memory (RAM) contains 68 bytes. Data EEPROM is 64 bytes. There are also 13 I/O pins that are user-configured on a pin-to-pin basis. Some pins are multiplexed with other device functions. These functions include: · External interrupt · Change on PORTB interrupt · Timer0 clock input Table 1-1 details the pinout of the device with descriptions and details for each pin.
FIGURE 1-1:
PIC16F84A BLOCK DIAGRAM
13 Data Bus Program Counter 8 EEPROM Data Memory
FLASH Program Memory 1K x 14 8 Level Stack (13-bit) RAM File Registers 68 x 8 EEDATA
EEPROM Data Memory 64 x 8
Program Bus
14
7
RAM Addr
EEADR
Instruction Register 5 Direct Addr
Addr Mux 7 Indirect Addr TMR0
FSR reg RA4/T0CKI STATUS reg 8
Power-up Timer Instruction Decode & Control Oscillator Start-up Timer Power-on Reset Watchdog Timer W reg ALU
MUX 8 I/O Ports
RA3:RA0 RB7:RB1
Timing Generation
RB0/INT
OSC2/CLKOUT OSC1/CLKIN
MCLR
VDD, VSS
© 2001 Microchip Technology Inc.
DS35007B-page 3
PIC16F84A
TABLE 1-1:
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16F84A PINOUT DESCRIPTION
PDIP No. 16 15 SOIC No. 16 15 SSOP No. 18 19 I/O/P Type I O Buffer Type Description
ST/CMOS(3) Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Master Clear (Reset) input/programming voltage input. This pin is an active low RESET to the device. PORTA is a bi-directional I/O port.
MCLR
4
4
4
I/P
ST
RA0 RA1 RA2 RA3 RA4/T0CKI
17 18 1 2 3
17 18 1 2 3
19 20 1 2 3
I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST Can also be selected to be the clock input to the TMR0 timer/counter. Output is open drain type. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 VSS VDD Legend: I= input
6 7 8 9 10 11 12 13 5 14
6 7 8 9 10 11 12 13 5 14
7 8 9 10 11 12 13 14 5,6 15,16
I/O I/O I/O I/O I/O I/O I/O I/O P P
TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST
(2)
RB0/INT can also be selected as an external interrupt pin.
Interrupt-on-change pin. Interrupt-on-change pin. Interrupt-on-change pin. Serial programming clock. Interrupt-on-change pin. Serial programming data. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
TTL/ST(2) -- --
O = Output I/O = Input/Output P = Power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS35007B-page 4
© 2001 Microchip Technology Inc.
PIC16F84A
2.0 MEMORY ORGANIZATION
FIGURE 2-1:
There are two memory blocks in the PIC16F84A. These are the program memory and the data memory. Each block has its own bus, so that access to each block can occur during the same oscillator cycle. The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the "core" are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module. The data memory area also contains the data EEPROM memory. This memory is not directly mapped into the data memory, but is indirectly mapped. That is, an indirect address pointer specifies the address of the data EEPROM memory to read/write. The 64 bytes of data EEPROM memory have the address range 0h-3Fh. More details on the EEPROM memory can be found in Section 3.0. Additional information on device memory may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023).
3FFh
PROGRAM MEMORY MAP AND STACK - PIC16F84A
PC<12:0> 13 CALL, RETURN RETFIE, RETLW Stack Level 1
· · ·
Stack Level 8 RESET Vector Peripheral Interrupt Vector
0000h 0004h
2.1
Program Memory Organization
The PIC16FXX has a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PIC16F84A, the first 1K x 14 (0000h-03FFh) are physically implemented (Figure 2-1). Accessing a location above the physically implemented address will cause a wraparound. For example, for locations 20h, 420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h, the instruction will be the same. The RESET vector is at 0000h and the interrupt vector is at 0004h.
User Memory Space
1FFFh
© 2001 Microchip Technology Inc.
DS35007B-page 5
PIC16F84A
2.2 Data Memory Organization
FIGURE 2-2:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB
--
The data memory is partitioned into two areas. The first is the Special Function Registers (SFR) area, while the second is the General Purpose Registers (GPR) area. The SFRs control the operation of the device. Portions of data memory are banked. This is for both the SFR area and the GPR area. The GPR area is banked to allow greater than 116 bytes of general purpose RAM. The banked areas of the SFR are for the registers that control the peripheral functions. Banking requires the use of control bits for bank selection. These control bits are located in the STATUS Register. Figure 2-2 shows the data memory map organization. Instructions MOVWF and MOVF can move values from the W register to any location in the register file ("F"), and vice-versa. The entire data memory can be accessed either directly using the absolute address of each register file or indirectly through the File Select Register (FSR) (Section 2.5). Indirect addressing uses the present value of the RP0 bit for access into the banked areas of data memory. Data memory is partitioned into two banks which contain the general purpose registers and the special function registers. Bank 0 is selected by clearing the RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank 1. Each Bank extends up to 7Fh (128 bytes). The first twelve locations of each Bank are reserved for the Special Function Registers. The remainder are General Purpose Registers, implemented as static RAM.
REGISTER FILE MAP PIC16F84A
File Address Indirect addr.(1) OPTION_REG PCL STATUS FSR TRISA TRISB
--
80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch
EEDATA EEADR PCLATH INTCON
EECON1 EECON2(1) PCLATH INTCON
68 General Purpose Registers (SRAM)
Mapped (accesses) in Bank 0
4Fh 50h
CFh D0h
2.2.1
GENERAL PURPOSE REGISTER FILE
Each General Purpose Register (GPR) is 8-bits wide and is accessed either directly or indirectly through the FSR (Section 2.5). The GPR addresses in Bank 1 are mapped to addresses in Bank 0. As an example, addressing location 0Ch or 8Ch will access the same GPR.
7Fh Bank 0 Bank 1
FFh
Unimplemented data memory location, read as '0'. Note 1: Not a physical register.
DS35007B-page 6
© 2001 Microchip Technology Inc.
PIC16F84A
2.3 Special Function Registers
The Special Function Registers (Figure 2-2 and Table 2-1) are used by the CPU and Peripheral functions to control the device operation. These registers are static RAM. The special function registers can be classified into two sets, core and peripheral. Those associated with the core functions are described in this section. Those related to the operation of the peripheral features are described in the section for that specific feature.
TABLE 2-1:
SPECIAL FUNCTION REGISTER FILE SUMMARY
Value on Power-on RESET Details on page
Addr Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 0Ah 0Bh
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INDF TMR0 PCL STATUS FSR PORTA(4) PORTB(5) -- EEDATA EEADR PCLATH INTCON INDF OPTION_REG PCL STATUS (2) FSR TRISA TRISB -- EECON1 EECON2 PCLATH INTCON
(2)
Uses contents of FSR to address Data Memory (not a physical register) 8-bit Real-Time Clock/Counter Low Order 8 bits of the Program Counter (PC) IRP -- RB7 RP1 -- RB6 RP0 -- RB5 TO RA4/T0CKI RB4 PD RA3 RB3 Z RA2 RB2 DC RA1 RB1 C RA0
---- ---xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx ---x xxxx -- xxxx xxxx xxxx xxxx RB0/INT xxxx xxxx
11 20 11 8 11 16 18 -- 13,14 13,14 11 10 11 9 11 8 11 16 18 -- 13 14 11 10
Indirect Data Memory Address Pointer 0
Unimplemented location, read as '0' EEPROM Data Register EEPROM Address Register -- GIE -- EEIE -- T0IE Write Buffer for upper 5 bits of the PC INTE RBIE T0IF
(1)
---0 0000 RBIF 0000 000x ---- ---PS0 1111 1111 0000 0000
INTF
Bank 1 Uses Contents of FSR to address Data Memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1
Low order 8 bits of Program Counter (PC) IRP -- RP1 -- RP0 -- TO PD Z DC C
0001 1xxx xxxx xxxx ---1 1111 1111 1111 --
Indirect data memory address pointer 0 PORTA Data Direction Register PORTB Data Direction Register Unimplemented location, read as '0' -- -- -- EEIF WRERR WREN WR
(1)
RD
---0 x000 ---- ------0 0000
EEPROM Control Register 2 (not a physical register) -- GIE -- EEIE -- T0IE Write buffer for upper 5 bits of the PC INTE RBIE T0IF
INTF
RBIF
0000 000x
Legend: x = unknown, u = unchanged. - = unimplemented, read as '0', q = value depends on condition Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> are never transferred to PCLATH. 2: The TO and PD status bits in the STATUS register are not affected by a MCLR Reset. 3: Other (non power-up) RESETS include: external RESET through MCLR and the Watchdog Timer Reset. 4: On any device RESET, these pins are configured as inputs. 5: This is the value that will be in the port output latch.
© 2001 Microchip Technology Inc.
DS35007B-page 7
PIC16F84A
2.3.1 STATUS REGISTER
The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bit for data memory. As with any register, the STATUS register can be the destination for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). Only the BCF, BSF, SWAPF and MOVWF instructions should be used to alter the STATUS register (Table 7-2), because these instructions do not affect any status bit. Note 1: The IRP and RP1 bits (STATUS<7:6>) are not used by the PIC16F84A and should be programmed as cleared. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. 2: The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. 3: When the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. The specified bit(s) will be updated according to device logic
REGISTER 2-1:
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 IRP bit 7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
bit 7-6 bit 5
Unimplemented: Maintain as `0' RP0: Register Bank Select bits (used for direct addressing) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit
- n = Value at POR
W = Writable bit
'1' = Bit is set
U = Unimplemented bit, read as `0'
'0' = Bit is cleared x = Bit is unknown
DS35007B-page 8
© 2001 Microchip Technology Inc.
PIC16F84A
2.3.2 OPTION REGISTER
Note: The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORTB. When the prescaler is assigned to the WDT (PSA = '1'), TMR0 has a 1:1 prescaler assignment.
REGISTER 2-2:
OPTION REGISTER (ADDRESS 81h)
R/W-1 RBPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
© 2001 Microchip Technology Inc.
DS35007B-page 9
PIC16F84A
2.3.3 INTCON REGISTER
Note: The INTCON register is a readable and writable register that contains the various enable bits for all interrupt sources. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
REGISTER 2-3:
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 GIE bit 7 R/W-0 EEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit 0
bit 7
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE Write Complete interrupts 0 = Disables the EE Write Complete interrupt T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS35007B-page 10
© 2001 Microchip Technology Inc.
PIC16F84A
2.4 PCL and PCLATH 2.5
The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. If the program counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. All updates to the PCH register go through the PCLATH register.
Indirect Addressing; INDF and FSR Registers
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
EXAMPLE 2-1:
· · · ·
INDIRECT ADDRESSING
2.4.1
STACK
The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution. Mid-range devices have an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed. After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).
Register file 05 contains the value 10h Register file 06 contains the value 0Ah Load the value 05 into the FSR register A read of the INDF register will return the value of 10h · Increment the value of the FSR register by one (FSR = 06) · A read of the INDF register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2:
HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
movlw movwf NEXT clrf incf btfss goto CONTINUE :
An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-3. However, IRP is not used in the PIC16F84A.
© 2001 Microchip Technology Inc.
DS35007B-page 11
PIC16F84A
FIGURE 2-3: DIRECT/INDIRECT ADDRESSING
Direct Addressing RP1 RP0 (2) 6 From Opcode 0 IRP (2) 7 Indirect Addressing (FSR) 0
Bank Select
Location Select
Bank Select
Location Select
00 00h
01 80h
0Bh 0Ch Data Memory(1) 4Fh 50h 7Fh (3) Bank 0 Note 1: For memory map detail, see Figure 2-2. 2: Maintain as clear for upward compatibility with future products. 3: Not implemented. (3) Bank 1 FFh
Addresses map back to Bank 0
DS35007B-page 12
© 2001 Microchip Technology Inc.
PIC16F84A
3.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory. These registers are: · · · · EECON1 EECON2 (not a physically implemented register) EEDATA EEADR The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles. The write time is controlled by an on-chip timer. The writetime will vary with voltage and temperature as well as from chip to chip. Please refer to AC specifications for exact limits. When the device is code protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access this memory. Additional information on the Data EEPROM is available in the PICmicroTM Mid-Range Reference Manual (DS33023).
EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. PIC16F84A devices have 64 bytes of data EEPROM with an address range from 0h to 3Fh.
REGISTER 3-1:
EECON1 REGISTER (ADDRESS 88h)
U-0 -- bit 7 U-0 -- U-0 -- R/W-0 EEIF R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 7-5 bit 4
Unimplemented: Read as '0' EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset or any WDT Reset during normal operation) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM WR: Write Control bit 1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software. 0 = Write cycle to the EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate an EEPROM read Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 3
bit 2
bit 1
bit 0
© 2001 Microchip Technology Inc.
DS35007B-page 13
PIC16F84A
3.1 Reading the EEPROM Data Memory
Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.
To read a data memory location, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>). The data is available, in the very next cycle, in the EEDATA register; therefore, it can be read in the next instruction. EEDATA will hold this value until another read or until it is written to by the user (during a write operation).
EXAMPLE 3-1:
BCF MOVLW MOVWF BSF BSF BCF MOVF
DATA EEPROM READ
; ; ; ; ; ; ; Bank 0 Address to read Bank 1 EE Read Bank 0 W = EEDATA
STATUS, RP0 CONFIG_ADDR EEADR STATUS, RP0 EECON1, RD STATUS, RP0 EEDATA, W
3.3
Write Verify
3.2
Writing to the EEPROM Data Memory
To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDATA register. Then the user must follow a specific sequence to initiate the write for each byte.
Depending on the application, good programming practice may dictate that the value written to the Data EEPROM should be verified (Example 3-3) to the desired value to be written. This should be used in applications where an EEPROM bit will be stressed near the specification limit. Generally, the EEPROM write failure will be a bit which was written as a '0', but reads back as a '1' (due to leakage off the bit).
EXAMPLE 3-2:
BSF BCF BSF MOVLW
DATA EEPROM WRITE
; Bank 1 ; Disable INTs. ; Enable Write ; ; ; ; ; ; ; Write 55h Write AAh Set WR bit begin write Enable INTs.
EXAMPLE 3-3:
WRITE VERIFY
STATUS, RP0 INTCON, GIE EECON1, WREN 55h EECON2 AAh EECON2 EECON1,WR INTCON, GIE
BCF STATUS,RP0 ; Bank 0 : ; Any code : ; can go here MOVF EEDATA,W ; Must be in Bank 0 BSF STATUS,RP0 ; Bank 1 READ BSF ; YES, Read the ; value written BCF STATUS, RP0 ; Bank 0 ; ; Is the value written ; (in W reg) and ; read (in EEDATA) ; the same? ; SUBWF EEDATA, W ; BTFSS STATUS, Z ; Is difference 0? GOTO WRITE_ERR ; NO, Write error EECON1, RD
Required Sequence
MOVWF MOVLW MOVWF BSF BSF
The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment.
TABLE 3-1:
Address 08h 09h 88h 89h
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other RESETS
EEDATA EEADR EECON1 EECON2
EEPROM Data Register EEPROM Address Register -- -- -- EEIF WRERR WREN WR RD EEPROM Control Register 2
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu ---0 x000 ---0 q000 ---- ---- ---- ----
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends upon condition. Shaded cells are not used by data EEPROM.
DS35007B-page 14
© 2001 Microchip Technology Inc.
PIC16F84A
4.0 I/O PORTS
FIGURE 4-1:
Data Bus WR Port
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicroTM Mid-Range Reference Manual (DS33023).
BLOCK DIAGRAM OF PINS RA3:RA0
Q VDD
D
CK
Q
P I/O pin
4.1
PORTA and TRISA Registers
Data Latch N
PORTA is a 5-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Note: On a Power-on Reset, these pins are configured as inputs and read as '0'.
D WR TRIS
Q VSS CK Q TTL Input Buffer RD TRIS Q D
TRIS Latch
Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read. This value is modified and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers.
EN RD Port Note: I/O pins have protection diodes to VDD and VSS.
FIGURE 4-2:
Data Bus WR Port
EXAMPLE 4-1:
BCF CLRF
INITIALIZING PORTA
Initialize PORTA by clearing output data latches Select Bank 1 Value used to initialize data direction Set RA<3:0> as inputs RA4 as output TRISA<7:5> are always read as '0'.
D
BLOCK DIAGRAM OF PIN RA4
Q Q
BSF MOVLW
MOVWF
STATUS, RP0 ; PORTA ; ; ; STATUS, RP0 ; 0x0F ; ; ; TRISA ; ; ; ;
CK
Data Latch
D Q Q
N VSS
RA4 pin
WR TRIS
CK
TRIS Latch
Schmitt Trigger Input Buffer
RD TRIS
Q D EN EN
RD Port
TMR0 Clock Input Note: I/O pins have protection diodes to VDD and VSS.
© 2001 Microchip Technology Inc.
DS35007B-page 15
PIC16F84A
TABLE 4-1:
Name RA0 RA1 RA2 RA3 RA4/T0CKI
PORTA FUNCTIONS
Bit0 bit0 bit1 bit2 bit3 bit4 Buffer Type TTL TTL TTL TTL ST Function
Input/output Input/output Input/output Input/output Input/output or external clock input for TMR0. Output is open drain type. Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 4-2:
Address 05h 85h Name PORTA TRISA
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- -- Bit 6 -- -- Bit 5 -- -- Bit 4 RA4/T0CKI TRISA4 Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on Power-on Reset Value on all other RESETS
---x xxxx ---u uuuu
TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are unimplemented, read as '0'.
DS35007B-page 16
© 2001 Microchip Technology Inc.
PIC16F84A
4.2 PORTB and TRISB Registers
FIGURE 4-3:
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin).
BLOCK DIAGRAM OF PINS RB7:RB4
VDD Weak P Pull-up Data Latch D CK TRIS Latch D Q TTL Input Buffer Q I/O pin(2)
RBPU(1)
Data Bus WR Port
EXAMPLE 4-2:
BCF CLRF
INITIALIZING PORTB
Initialize PORTB by clearing output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
WR TRIS
BSF MOVLW
MOVWF
STATUS, RP0 ; PORTB ; ; ; STATUS, RP0 ; 0xCF ; ; ; TRISB ; ; ;
CK
RD TRIS
Latch Q D EN
Set RBIF
RD Port
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Four of PORTB's pins, RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
From other RB7:RB4 pins
Q
D EN RD Port
Note 1: 2:
TRISB = '1' enables weak pull-up (if RBPU = '0' in the OPTION_REG register). I/O pins have diode protection to VDD and VSS.
FIGURE 4-4:
BLOCK DIAGRAM OF PINS RB3:RB0
VDD Weak P Pull-up Data Latch D Q I/O pin(2) CK TRIS Latch D Q TTL Input Buffer
RBPU(1)
Data Bus WR Port
WR TRIS
CK
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature.
RD TRIS Q RD Port RB0/INT Schmitt Trigger Buffer Note 1: 2: RD Port D EN
TRISB = '1' enables weak pull-up (if RBPU = '0' in the OPTION_REG register). I/O pins have diode protection to VDD and VSS.
© 2001 Microchip Technology Inc.
DS35007B-page 17
PIC16F84A
TABLE 4-3:
Name RB0/INT
PORTB FUNCTIONS
Bit bit0 Buffer Type TTL/ST(1) I/O Consistency Function
Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). RB6 bit6 TTL/ST(2) Internal software programmable weak pull-up. Serial programming clock. Input/output pin (with interrupt-on-change). RB7 bit7 TTL/ST(2) Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger. Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 4-4:
Address 06h 86h 81h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 RB7 RBPU GIE Bit 6 RB6 INTEDG EEIE Bit 5 RB5 T0CS T0IE Bit 4 RB4 T0SE INTE Bit 3 RB3 PSA RBIE Bit 2 RB2 PS2 T0IF Bit 1 RB1 PS1 INTF Bit 0 Value on Power-on Reset Value on all other RESETS
PORTB TRISB OPTION_REG
RB0/INT xxxx xxxx uuuu uuuu TRISB0 1111 1111 1111 1111 PS0 RBIF 1111 1111 1111 1111 0000 000x 0000 000u
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1
0Bh,8Bh INTCON
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS35007B-page 18
© 2001 Microchip Technology Inc.
PIC16F84A
5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: · · · · · · 8-bit timer/counter Readable and writable Internal or external clock select Edge select for external clock 8-bit software programmable prescaler Interrupt-on-overflow from FFh to 00h When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. Additional information on external clock requirements is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
5.2
Prescaler
Figure 5-1 is a simplified block diagram of the Timer0 module. Additional information on timer modules is available in the PICmicroTM Mid-Range Reference Manual (DS33023).
5.1
Timer0 Operation
Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed below.
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 5-2). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. The prescaler is not readable or writable. The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to the WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.
FIGURE 5-1:
TIMER0 BLOCK DIAGRAM
Data Bus FOSC/4 0 1 1 PSOUT Sync with Internal Clocks PSOUT (2 Cycle Delay) Set Interrupt Flag bit T0IF on Overflow 8 TMR0
RA4/T0CKI pin T0SE
Programmable Prescaler 3 PS2, PS1, PS0 T0CS
0
PSA
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 5-2 for detailed block diagram).
© 2001 Microchip Technology Inc.
DS35007B-page 19
PIC16F84A
5.2.1 SWITCHING PRESCALER ASSIGNMENT
5.3
Timer0 Interrupt
The prescaler assignment is fully under software control (i.e., it can be changed "on the fly" during program execution). Note: To avoid an unintended device RESET, a specific instruction sequence (shown in the PICmicroTM Mid-Range Reference Manual, DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut-off during SLEEP.
FIGURE 5-2:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus M U X 8 1 0 M U X SYNC 2 Cycles TMR0 reg
CLKOUT (= FOSC/4)
0 RA4/T0CKI pin 1 T0SE
T0CS
PSA
Set Flag bit T0IF on Overflow
0 M U X
8-bit Prescaler 8 8 - to - 1 MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
TABLE 5-1:
Address 01h 0Bh,8Bh 81h 85h
REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx INTE T0SE RBIE PSA T0IF PS2 INTF PS1 RBIF PS0 0000 000x 1111 1111 ---1 1111 Value on all other RESETS uuuu uuuu 0000 000u 1111 1111 ---1 1111
TMR0 INTCON OPTION_REG TRISA
Timer0 Module Register GIE -- EEIE -- T0IE T0CS -- RBPU INTEDG
PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
DS35007B-page 20
© 2001 Microchip Technology Inc.
PIC16F84A
6.0 SPECIAL FEATURES OF THE CPU
the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. This design keeps the device in RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry. SLEEP mode offers a very low current power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Time-out or through an interrupt. Several oscillator options are provided to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select the various options. Additional information on special features is available in the PICmicroTM Mid-Range Reference Manual (DS33023).
What sets a microcontroller apart from other processors are special circuits to deal with the needs of real time applications. The PIC16F84A has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are: · OSC Selection · RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) · Interrupts · Watchdog Timer (WDT) · SLEEP · Code Protection · ID Locations · In-Circuit Serial ProgrammingTM (ICSPTM) The PIC16F84A has a Watchdog Timer which can be shut-off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep
6.1
Configuration Bits
The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. These bits are mapped in program memory location 2007h. Address 2007h is beyond the user program memory space and it belongs to the special test/configuration memory space (2000h - 3FFFh). This space can only be accessed during programming.
REGISTER 6-1:
R/P-u CP bit13 bit 13-4
PIC16F84A CONFIGURATION WORD
R/P-u R/P-u R/P-u R/P-u R/P-u CP CP CP CP CP R/P-u CP R/P-u R/P-u R/P-u R/P-u bit0
R/P-u R/P-u R/P-u CP CP CP
PWRTE WDTE
F0SC1 F0SC0
CP: Code Protection bit 1 = Code protection disabled 0 = All program memory is code protected PWRTE: Power-up Timer Enable bit 1 = Power-up Timer is disabled 0 = Power-up Timer is enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator
bit 3
bit 2
bit 1-0
© 2001 Microchip Technology Inc.
DS35007B-page 21
PIC16F84A
6.2
6.2.1
Oscillator Configurations
OSCILLATOR TYPES
FIGURE 6-2:
The PIC16F84A can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: · · · · LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor
EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1 PIC16FXX Open OSC2
Clock from Ext. System
6.2.2
CRYSTAL OSCILLATOR/CERAMIC RESONATORS
TABLE 6-1:
Ranges Tested: Mode XT
CAPACITOR SELECTION FOR CERAMIC RESONATORS
In XT, LP, or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 6-1).
Freq
OSC1/C1
OSC2/C2
FIGURE 6-1:
CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1 To Internal Logic SLEEP PIC16FXX
HS Note:
C1(1)
XTAL OSC2 C2(1) RS(2)
RF(3)
Note 1: See Table 6-1 for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. The PIC16F84A oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP, or HS modes, the device can have an external clock source to drive the OSC1/CLKIN pin (Figure 6-2). Note:
455 kHz 47 - 100 pF 47 - 100 pF 2.0 MHz 15 - 33 pF 15 - 33 pF 4.0 MHz 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 8.0 MHz 10.0 MHz 15 - 33 pF 15 - 33 pF Recommended values of C1 and C2 are identical to the ranges tested in this table. Higher capacitance increases the stability of the oscillator, but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for the appropriate values of external components.
When using resonators with frequencies above 3.5 MHz, the use of HS mode rather than XT mode, is recommended. HS mode may be used at any VDD for which the controller is rated.
DS35007B-page 22
© 2001 Microchip Technology Inc.
PIC16F84A
TABLE 6-2:
Mode LP XT
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Freq OSC1/C1 OSC2/C2
6.2.3
RC OSCILLATOR
HS Note:
32 kHz 68 - 100 pF 68 - 100 pF 200 kHz 15 - 33 pF 15 - 33 pF 100 kHz 100 - 150 pF 100 - 150 pF 2 MHz 15 - 33 pF 15 - 33 pF 4 MHz 15 - 33 pF 15 - 33 pF 4 MHz 15 - 33 pF 15 - 33 pF 20 MHz 15 - 33 pF 15 - 33 pF Higher capacitance increases the stability of the oscillator, but also increases the start-up time. These values are for design guidance only. Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. For VDD > 4.5V, C1 = C2 30 pF is recommended.
For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) values, capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types also affects the oscillation frequency, especially for low CEXT values. The user needs to take into account variation, due to tolerance of the external R and C components. Figure 6-3 shows how an R/C combination is connected to the PIC16F84A.
FIGURE 6-3:
VDD REXT
RC OSCILLATOR MODE
OSC1 CEXT VSS FOSC/4 Recommended values: OSC2/CLKOUT
Internal Clock PIC16FXX
5 k REXT 100 k CEXT > 20pF
© 2001 Microchip Technology Inc.
DS35007B-page 23
PIC16F84A
6.3 RESET
The PIC16F84A differentiates between various kinds of RESET: · · · · · Power-on Reset (POR) MCLR during normal operation MCLR during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) Some registers are not affected in any RESET condition; their status is unknown on a POR and unchanged in any other RESET. Most other registers are reset to a "RESET state" on POR, MCLR or WDT Reset during normal operation and on MCLR during SLEEP. They are not affected by a WDT Reset during SLEEP, since this RESET is viewed as the resumption of normal operation. Table 6-3 gives a description of RESET conditions for the program counter (PC) and the STATUS register. Table 6-4 gives a full description of RESET states for all registers. The TO and PD bits are set or cleared differently in different RESET situations (Section 6.7). These bits are used in software to determine the nature of the RESET.
Figure 6-4 shows a simplified block diagram of the On-Chip RESET Circuit. The MCLR Reset path has a noise filter to ignore small pulses. The electrical specifications state the pulse width requirements for the MCLR pin.
FIGURE 6-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR WDT Module VDD Rise Detect VDD OST/PWRT OST 10-bit Ripple Counter OSC1/ CLKIN On-Chip RC Osc(1) PWRT 10-bit Ripple Counter R Q SLEEP WDT Time-out Reset S
Power-on Reset
Chip_Reset
See Table 6-5
Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 2: See Table 6-5.
TABLE 6-3:
RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
Condition Program Counter 000h 000h 000h 000h PC + 1 PC + 1(1) STATUS Register
0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu uuu1 0uuu
Power-on Reset MCLR during normal operation MCLR during SLEEP WDT Reset (during normal operation) WDT Wake-up Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
DS35007B-page 24
© 2001 Microchip Technology Inc.
PIC16F84A
TABLE 6-4: RESET CONDITIONS FOR ALL REGISTERS
MCLR during: normal operation SLEEP WDT Reset during normal operation uuuu uuuu ---- ---uuuu uuuu 0000 0000 000q quuu(3) uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---0 0000 0000 000u ---- ---1111 1111 0000 0000 000q quuu(3) uuuu uuuu ---1 1111 1111 1111 ---0 q000 ---- ------0 0000 0000 000u Wake-up from SLEEP: through interrupt through WDT Time-out uuuu uuuu ---- ---uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu(1) ---- ---uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu ---u uuuu uuuu uuuu ---0 uuuu ---- ------u uuuu uuuu uuuu(1)
Register
Address
Power-on Reset
W INDF TMR0 PCL STATUS FSR PORTA(4) PORTB(5) EEDATA EEADR PCLATH INTCON INDF OPTION_REG PCL STATUS FSR TRISA TRISB EECON1 EECON2 PCLATH INTCON
-- 00h 01h 02h 03h 04h 05h 06h 08h 09h 0Ah 0Bh 80h 81h 82h 83h 84h 85h 86h 88h 89h 8Ah 8Bh
xxxx xxxx ---- ---xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx ---x xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---0 0000 0000 000x ---- ---1111 1111 0000 0000 0001 1xxx xxxx xxxx ---1 1111 1111 1111 ---0 x000 ---- ------0 0000 0000 000x
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: Table 6-3 lists the RESET value for each specific condition. 4: On any device RESET, these pins are configured as inputs. 5: This is the value that will be in the port output latch.
© 2001 Microchip Technology Inc.
DS35007B-page 25
PIC16F84A
6.4 Power-on Reset (POR) 6.6 Oscillator Start-up Timer (OST)
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A minimum rise time for VDD must be met for this to operate properly. See Electrical Specifications for details. When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting." The POR circuit does not produce an internal RESET when VDD declines. The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle delay (from OSC1 input) after the PWRT delay ends (Figure 6-6, Figure 6-7, Figure 6-8 and Figure 6-9). This ensures the crystal oscillator or resonator has started and stabilized. The OST time-out (TOST) is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP. When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD has reached its final value. In this case (Figure 6-9), an external Power-on Reset circuit may be necessary (Figure 6-5).
FIGURE 6-5:
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD
6.5
Power-up Timer (PWRT)
VDD D
The Power-up Timer (PWRT) provides a fixed 72 ms nominal time-out (TPWRT) from POR (Figures 6-6 through 6-9). The Power-up Timer operates on an internal RC oscillator. The chip is kept in RESET as long as the PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level (possible exception shown in Figure 6-9). A configuration bit, PWRTE, can enable/disable the PWRT. See Register 6-1 for the operation of the PWRTE bit for a particular device. The power-up time delay TPWRT will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details.
R R1 MCLR C PIC16FXX
Note 1: External Power-on Reset circuit is required only if VDD power-up rate is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not exceed 0.2V (max leakage current spec on MCLR pin is 5 µA). A larger voltage drop will degrade VIH level on the MCLR pin. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C, in the event of a MCLR pin breakdown due to ESD or EOS.
DS35007B-page 26
© 2001 Microchip Technology Inc.
PIC16F84A
FIGURE 6-6:
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 6-7:
VDD MCLR INTERNAL POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 6-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
© 2001 Microchip Technology Inc.
DS35007B-page 27
PIC16F84A
FIGURE 6-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.
6.7
Time-out Sequence and Power-down Status Bits (TO/PD)
On power-up (Figures 6-6 through 6-9), the time-out sequence is as follows: 1. 2. PWRT time-out is invoked after a POR has expired. Then, the OST is activated.
Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high, execution will begin immediately (Figure 6-6). This is useful for testing purposes or to synchronize more than one PIC16F84A device when operating in parallel. Table 6-6 shows the significance of the TO and PD bits. Table 6-3 lists the RESET conditions for some special registers, while Table 6-4 lists the RESET conditions for all the registers.
The total time-out will vary based on oscillator configuration and PWRTE configuration bit status. For example, in RC mode with the PWRT disabled, there will be no time-out at all.
TABLE 6-6:
TO
1 0 x 0 0
STATUS BITS AND THEIR SIGNIFICANCE
Condition Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR WDT Reset (during normal operation) WDT Wake-up MCLR during normal operation MCLR during SLEEP or interrupt wake-up from SLEEP
TABLE 6-5:
TIME-OUT IN VARIOUS SITUATIONS
Power-up Wake-up from SLEEP 1024TOSC --
PD
1 x 0 1 0 1 0
Oscillator Configuration XT, HS, LP RC
PWRT Enabled
PWRT Disabled
72 ms + 1024TOSC 1024TOSC 72 ms --