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16-Bit CMOS Single-Chip Microcontrollers
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Microcomputer Components
SAB 80C166/83C166 16-Bit CMOS Single-Chip Microcontrollers for Embedded Control Applications
User's Manual 06.90 / 08.97
SAB 80C166/83C166 Revision History: Previous Releases: Page A-* D-* Current Version: 06.90 / 08.97 Original version 6.90
Subjects (major changes since last revision) Instruction Set removed. See separate "Instruction Set Manual" (B158-H6772-G1-X-7600). Device Specifications removed. Please refer to actual data sheet. Addendum to User's Manual 9.90 included. Now both documents are combined to one single book.
Note:
The contents of the combined documents is identical with the respective original version (6.90 or 9.90)
Edition 06.90 / 08.97 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
Microcomputer Components
SAB 80C166/83C166 16-Bit CMOS Single-Chip Microcontrollers for Embedded Control Applications
User's Manual 06.90 / 08.97
Note: The User's Manual describes the SAB 80C166 up to the AB step. The Addendum to the User's Manual describes the improvements and features implemented in the SAB 80C166 from the BA step. There is no explicit notice which parts of the User's Manual are to be replaced by the addendum. Please be aware that reading the addendum is essential for the correct programming of the SAB 80C166 devices available today.
Contents
Page
13
13.1 13.1.1 13.1.2 13.1.3 13.2 13.3 13.4 13.4.1 13.4.1.1 13.4.2 13.5 13.6 13.6.1 13.6.2 13.6.3 13.7 13.8 13.9 13.10
System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Instructions Provided as Subsets of Instructions. . . . . . . . . . . . . . . . . . . . . . Directly Substitutable Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modification of System Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Data Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13-1 13-1 13-2
Multiplication and Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 BCD Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 Stack Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal System Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Use of Stack Underflow/Overflow Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13-4 13-5 13-6
Register Banking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 Procedure Call Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Passing Parameters on the System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cross Segment Subroutine Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Providing Local Registers for Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13-7 13-7 13-8
Table Searching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 Peripheral Control and Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 Floating Point Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 Trap/Interrupt Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
14
14.1 14.2 14.2.1 14.2.2` 14.2.3 14.3
Support Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
Hardware Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assembler Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . `C' Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulator Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14-2 14-3 14-3
Hosts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
Appendix Appendix A Removed
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Contents
Page
B
B.1 B.1.1 B.1.2 B.2 B.2.1 B.2.2 B.3
SAB 80C166 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
CPU General Purpose Registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Word Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 Special Function Registers Ordered by Address . . . . . . . . . . . . . . . . . . . . . . B-4 Non-Bit Addressable Special Function Registers. . . . . . . . . . . . . . . . . . . . . . . . . . B-4 Bit Addressable Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 Special Function Registers Alphabetical Order . . . . . . . . . . . . . . . . . . . . . . B-12
C
C.1 C.1
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
External Bus and Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 Calculation of the user Selectable Bus Timing Parameters . . . . . . . . . . . . . . . C-9
D
D.1 D.2 D.3 D.4 D.5 D.6 D.7 D.8 D.9 D.10 D.11
Addendum to User's Manual 09.90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
GPT2 Timer T5 Clear Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3 Serial Port Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3 Implementation of a 16/18-Bit Address, 8-Bit Data, Non-Multiplexed Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-4 Mapping the internal ROM address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-4 Selection of Bus Modes and ROM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . D-5 Change of the READY#-Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-8 Implementation of an additional Bus Configuration Register . . . . . . . . . . . . . D-9 Switching between the Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-11 Implementation of ALE Lengthening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-11 Automatic Continuation of Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . D-12 Implementation of HOLD/HLDA/BREQ Bus Arbitration . . . . . . . . . . . . . . . . . D-12
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Architectural Overview
2
Architectural Overview
This chapter contains an overview of the SAB 80C166's architecture with combines advantages of both RISC and CISC processors in a very well-balanced way. It introduces the features which do in sum result in a high performance microcontroller which is the right choice not only for today's applications, but also for future engineering challenges. 2.1 Basic CPU concepts and optimizations To meet the demand for greater performance and flexibility, a number of areas has been optimized in the processor core. These are summarized below, and described in detail in the following sections: 1) High Instruction Bandwidth/Fast Execution 2) High Function 8-bit and 16-bit Arithmetic and Logic Unit 3) Extended Bit Processing and Peripheral Control 4) High Performance Branch-, Call-, and Loop Processing 5) Consistent and Optimized Instruction Formats 6) Programmable Multiple Priority Interrupt Structure 2.1.1 High Instruction Bandwidth/Fast Execution To achieve the desired performance, a goal of approximately one instruction executed during each machine cycle was set for the core CPU. Primarily, this goal has been reached except for branch-, multiply- or divide instructions. These instructions, however, have also been optimized. For example, branch instructions only require an additional machine cycle when a branch is taken, and most branches taken in loops require no additional machine cycles. The instruction cycle time has been dramatically reduced through the use of instruction pipelining. This technique allows the core CPU to process portions of multiple sequential instruction stages in parallel. The following four stage pipeline provides the optimum balancing for the SAB 80C166 family's CPU core: FETCH: DECODE: In this stage, an instruction is fetched from the internal ROM or RAM, or from the external memory based on the current IP value. In this stage, the previously fetched instruction is decoded and the required operands are fetched.
EXECUTE: In this stage, the specified operation is performed on the previously fetched operands. WRITE BACK: In this stage, the result is written to the specified location. If this technique were not used, each instruction would require four machine cycles. This increased performance allows a greater number of tasks and interrupts to be processed.
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Architectural Overview
2.1.2 High Function 8-bit and 16-bit Arithmetic and Logic Unit Most internal execution blocks have been optimized to perform operations on either 8-bit or 16bit quantities. Once the pipeline has been filled, one instruction is completed per machine cycle except for multiply and divide. An advanced Booth algorithm has been incorporated to allow four bits to be multiplied and two bits to be divided per machine cycle. Thus, these operations require four and nine machine cycles, respectively, to perform a 16-bit by 16-bit (or 32-bit by 16-bit) calculation plus one machine cycle to setup and adjust the operands and the result. Even these longer multiply and divide instructions can be interrupted during their execution to allow for very fast interrupt response. Instructions have also been provided to allow byte packing in memory while providing sign extension of bytes for word wide arithmetic operations. The internal bus structure also allows transfers of bytes or words to or from peripherals based on the peripheral requirements. A set of consistent flags is automatically updated in the PSW after each arithmetic, logical, shift, or movement operation. These flags allow branching on specific conditions. Support for both signed and unsigned arithmetic is provided through user-specifiable branch tests. These flags are also preserved automatically by the CPU upon entry to an interrupt or trap routine. 2.1.3 Extended Bit Processing and Peripheral Control A large number of instructions has been dedicated to bit processing. These instructions provide efficient control and testing of peripherals while enhancing data manipulation. Unlike many current microcontrollers, these instructions provide direct access to two operands in the bit-addressable space without requiring movement into temporary flags. The same logical instructions available for words and bytes are also supported for bits. This allows the user to compare and modify a control bit for a peripheral in one instruction. Multiple bit shift instructions have been included to avoid long instruction streams of single bit shift operations. These are also performed in a single machine cycle. In addition, bit field instructions have been provided which allow the modification of multiple bits from one operand in a single instruction. 2.1.4 High Performance Branch-, Call-, and Loop Processing Due to the high percentage of branching in controller applications, branch instructions have been optimized to require one extra machine cycle only when a branch is taken. This is implemented by precalculating the target address while decoding the instruction. To decrease loop execution overhead, three enhancements have been provided. The first solution provides single cycle branch execution after the first iteration of a loop. Thus, only one machine cycle is lost during the execution of the entire loop. In loops which fall through upon completion, no machine cycles are lost when exiting the loop. No special instructions are required to perform loops, and loops are automatically detected during execution of branch instructions.
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Architectural Overview
The second loop enhancement allows the detection of the ends of tables and avoids the use of two compare instructions embedded in loops. One simply places the lowest negative number at the end of the specific table, and specifies branching if neither this value nor the compared value have been found. Otherwise the loop is terminated if either condition has been met. One can then test which condition has occurred. This method is described in detail in section 13.7. The third loop enhancement provides a more flexible solution than the Decrement and Skip on Zero instruction which is found in many other microcontrollers. Through the use of Compare and Increment or Decrement instructions, the user can make comparisons to any value. This allows loop counters to cover any range. This is particularly advantageous in table searching. Saving of system state is automatically performed on the internal system stack avoiding the use of instructions to preserve state upon entry and exit of interrupt or trap routines. Call instructions push the value of the IP on the system stack, and require the same execution time as branch instructions. Instructions have also been provided to support indirect branch and call instructions. This supports implementation of multiple CASE statement branching in assembler macros and high level languages. 2.1.5 Consistent and Optimized Instruction Formats To obtain optimum performance in a pipelined design, an instruction set has been designed which incorporates concepts from Reduced Instruction Set Computers (RISC). These concepts primarily allow fast decoding of the instructions and operands while reducing pipeline holds. These concepts, however, do not preclude the use of complex instructions which are required by microcontroller users. The following goals were used to design the instruction set: 1) Provide powerful instructions to perform operations which currently require sequences of instructions and are frequently used. Avoid transfer into and out of temporary registers such as accumulators and carry bits. Perform tasks in parallel such as saving state upon entry to interrupt routines or subroutines. 2) Avoid complex encoding schemes by placing operands in consistent fields for each instruction. Also avoid complex addressing modes which are not frequently used. This decreases the instruction decode time while also simplifying the development of compilers and assemblers. 3) Provide most frequently used instructions with one-word instruction formats. All other instructions are placed into two-word formats. This allows all instructions to be placed on word boundaries, which alleviates the need for complex alignment hardware. It also has the benefit of increasing the range for relative branching instructions.
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Architectural Overview
2.1.6 Programmable Multiple Priority Interrupt Structure A number of enhancements have been included to allow processing of a large number of interrupt sources. These are presented below: 1) Peripheral Event Controller (PEC): This processor is used to off-load many interrupt requests from the CPU. It avoids the overhead of entering and exiting interrupt or trap routines by performing single-cycle interrupt-driven byte or word data transfers. 2) Multiple Priority Interrupt Controller: This controller allows all interrupts to be placed at any specified priority. Interrupts may also be grouped, which provides the user with the ability to prevent similar priority tasks from interrupting each other. 3) Multiple Register Banks: This feature allows the user to specify up to sixteen general purpose registers located anywhere in the internal RAM. A single one-machine-cycle instruction is used to switch register banks from one task to another. 4) Interruptable Multiple Cycle Instructions: Reduced interrupt latency is provided by allowing multiple-cycle instructions (multiply, divide) to be interruptable. 2.2 Functional Blocks The SAB 80C166 family clearly separates peripherals from the core. This structure permits the maximum number of operations to be performed in parallel and allows peripherals to be added or deleted from family members without modifications to the core. Each functional block processes data independently and communicates information over common buses. Functional blocks in the CPU core are controlled by signals from the instruction decode logic. Peripherals are controlled by data written to the Special Function Registers (SFRs). The following sections describe the functional blocks of the SAB 80C166 and interactions between these blocks. 2.2.1 16-Bit CPU
2.2.1.1 Instruction Decoding Instruction decoding is primarily generated from PLA outputs based on the selected opcode. No microcode is used and each pipeline stage receives control signals staged in control registers from the decode stage PLAs. Pipeline holds are primarily caused by wait states for external memory accesses and cause the holding of signals in the control registers. Multiplecycle instructions are performed through instruction injection and simple internal state machines which modify required control signals.
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Architectural Overview
Clock Generator
ROM 8 KBytes (SAB 83C166)
RAM 1 KBytes
Watchdog Timer
16-Bit CPU
10-Channel 10-Bit A/D Converter
16-Bit Timer T0 16-Channel Capture / Compare Unit
Interrupt & PEC Control Serial Channel ASC0
General Purpose Timer Unit GPT2 16-Bit Timer T2 16-Bit Timer T3
General Purpose Timer Unit GPT2 16-Bit Timer T5
16-Bit Timer T1
16-Bit Timer T4
16-Bit Timer T6
Serial Channel ASC1
External Bus Controller
I/O Ports
Functional Block Diagram Semiconductor Group 25
Architectural Overview
2.2.1.2 Arithmetic and Logic Unit All standard arithmetic and logical operations are performed in a 16-bit ALU. In addition, for byte operations, signals are provided from bits six and seven of the ALU result to correctly set the condition flags. Multiple precision arithmetic is provided through a 'CARRY-IN' signal to the ALU from previously calculated portions of the desired operation. Booth multiplication and division are supported by an extended ALU and a bit shifter placed on two coupled 16-bit registers, MDL and MDH. All targets for branch calculations are also computed in the central ALU. 2.2.1.3 Barrel Shifter A 16-bit barrel shifter provides multiple bit shifts in a single cycle. Rotates and arithmetic shifts are also supported. 2.2.2 Peripheral Event Controller (PEC) and Interrupt Control Each interrupt source is prioritized every machine cycle in the interrupt control block. If PEC service is selected, a PEC transfer is started. If CPU interrupt service is requested, the current CPU priority level stored in the PSW register is tested to determine whether a higher priority interrupt is currently being serviced. When an interrupt is acknowledged, the current state of the machine is saved on the internal system stack and the CPU branches to the system specific vector for the peripheral. The PEC contains a set of SFRs which store the count value and control bits for eight data transfer channels. In addition, the PEC uses a dedicated area of RAM which contains the source and destination addresses. The PEC is controlled similar to any other peripheral through SFRs containing the desired configuration of each channel. 2.2.3 Internal RAM A dual port 512 by 16-bit internal RAM provides fast access to General Purpose Registers (GPRs), user data,and system stack. A unique decoding scheme provides flexible user register banks in the internal memory while optimizing the remaining RAM for user data. Hardware detection of the selected memory space is placed at the internal memory decoders and allows the user to specify any address directly or indirectly and obtain the desired data without using temporary registers or special instructions. 2.2.4 Internal ROM An optional large internal ROM of 8 Kbytes is provided for both code and constant data storage. This memory area is connected to the CPU via a 32-bit-wide bus. Thus, an entire double-word instruction can be fetched in just one machine cycle. Program execution from the on-chip ROM is the fastest of all possible alternatives.
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Architectural Overview
2.2.5 Clock Generator The on-chip clock generator contains a prescaler which divides the external clock frequency by 2. Thus, the internal clock frequency is half the external clock frequency (i.e. fOSC=40 MHz internal clock frequency=20 MHz). Two separated clocks are generated for the CPU and the peripheral part of the chip. While the CPU clock is stopped during waitstates or during the idle mode, the peripheral clock keeps running. Both clocks are switched off when the power down mode is entered. 2.2.6 Peripherals and Ports The SAB 80C166 also contains: two blocks of general purpose timers a capture/compare unit two serial interface channels an A/D converter a watchdog timer six I/O ports with a total of 76 I/O lines Each peripheral also contains a set of SFRs which control the functionality of the peripheral and temporarily store intermediate data results. Each peripheral has an associated set of status flags. Individually selected clock signals are generated for each peripheral from binary multiples of the system clock.
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System Description
3
System Description
In this chapter, a summary of the SAB 80C166 is presented. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the SAB 80C166.
16
Internal ROM 8 KBytes (SAB 83C16 6
32
SAB 80C166
16
16
CPU CORE
Internal RAM 1K Bytes
PEC
XTAL
OSC.
16
Interrupt Controller
Watchdog
16
16
Port 0 Port 4
Ext. Bus Controller
10-bit ADC
USART USART GPT1 ASC0 ASC1 T2
T3 BRG BRG T4
GPT2
T5 T6 T 1
CAPCOM
...
...
Port 5
T 0
2
Port 1
Port 3
Port 2
16
10
16
16
Figure 3.1 Block Diagram
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System Description
3.1 Memory Organization The memory space of the SAB 80C166 is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which currently includes 256 Kbytes. Address space expansion to 16 Mbytes is provided for future versions. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The SAB 83C166 contains 8 Kbytes of a mask-programmable on-chip ROM for code or constant data. A large dual port RAM of 1Kbyte is contained on both the SAB 80C166 and the SAB 83C166. This internal RAM is provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so called General Purpose Registers (GPRs). 512 bytes of the address space are reserved for the Special Function Register (SFR) area. SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. 98 SFRs are currently implemented. Unused SFR addresses are reserved for future members of the SAB 80C166 family. In order to meet the needs of designs where more memory is required than is provided on chip, up to 256 Kbytes of external RAM and/or ROM can be connected to the microcontroller. 3.2 External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed to either the Single Chip Mode when no external memory is required, or to one of three different external memory access modes, which are as follows: 16-bit/18-bit Addresses, 16-bit Data, Non-Multiplexed 16-bit/18-bit Addresses, 16-bit Data, Multiplexed 16-bit/18-bit Addresses, 8-bit Data, Multiplexed In the non-multiplexed bus mode, Port 1 is used as an output for addresses and Port 0 is used as an input/output for data. In the multiplexed bus modes, just one of the two 16-bit ports, Port 0, is used as an input/output for both addresses and data. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory TriState Time and Read/Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories. Access to very slow memories is supported via a particular 'Ready' function.
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System Description
For applications which require less than 64 Kbytes of memory space, a non-segmented memory model can be selected. In this case, all memory locations can be addressed by 16 bits, and thus Port 4 is not needed as an output for the two most significant address bits (A17 and A16), as is the case when using the segmented memory model. 3.3 Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the SAB 80C166's instructions can be exected in just one machine cycle which requires 100 ns at 20 MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: A 32-bit/16-bit division in 1µs, a 16-bit * 16-bit multiplication in 0.5 µs, and branches in 200 ns. Another pipeline optimization, the so called 'Jump Cache', allows reducing the execution time of repeatedly performed jumps in a loop from 200 ns to100 ns.
CPU
SP STKOV STKUV MDH MDL Mul./Div.-HW Bit-Mask Gen. R15
16
1K Bytes RAM
8K Bytes ROM
32
Exec.Uni t Instr.Ptr. 4-Stage Pipeline
General R15 Purpose
ALU
(16-bit)
Barrel-
Register s R0
PSW SYSCON Data Page Ptr.
Context Ptr. Code Seg. Ptr.
16
Figure 3.2 CPU Block Diagram
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System Description
The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at the time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, register banks can also be organized overlappingly. A system stack of up to 512 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly functional SAB 80C166 instruction set which includes the following instruction classes: Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions
The basic instruction lenght is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands. 3.4 Interrupt System With an interrupt response time within a range from just 250 ns to 500 ns (in case of internal program execution), the SAB 80C166 is capable of reacting very fast to the occurence of nondeterministic events. The architecture of the SAB 80C166 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
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System Description
In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is 'stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data, or for transferring A/D converted results to a memory table. The SAB 80C166 has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield, exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Software interrupts are supported by means of the 'TRAP' instruction in combination with an individual trap (interrupt) number. The SAB 80C166 also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so called 'Hardware Traps'. Hardware traps cause immediate non-maskable system reaction which is similiar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by a individual bit in the trap flag register (TFR). Except another higher prioritized trap service being in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. 3.5 Capture/Compare (CAPCOM) Unit The CAPCOM unit supports generation and control of timing sequences on up to 16 channels with a maximum resolution of 400 ns. The CAPCOM unit is typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PWM), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Two 16-bit timers (T0/T1) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
Semiconductor Group
35
System Description
This provides a wide range of variation for the timer period and resolution and allows precise adjustment to the application specific requirements. In addition, an external count input for CAPCOM timer T0 allows event scheduling for the capture/compare registers relative to external events. The capture/compare register array contains 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1, and programmed for capture or compare function. Each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched ('captured') into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event.The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. 3.6 General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurement, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one of three basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derived from the internal system clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the 'gate' level on an external input pin. For these purposes, each timer has one associated port pin which serves as gate or clock input. The maximum resolution of the timers in the GPT1 module is 400 ns (@ fOSC=40 MHz). The count direction (up/down) for each timer is programmable by software. For timer T3, the count direction may additionally be altered dynamically by an external signal on a port pin to facilitate e.g. position tracking. Timer T3 has an output toggle latch which changes its state on each timer oveflow/underflow. The state of this latch may be output on a port pin e.g for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are Semiconductor Group 36
System Description
stopped. The contents of timer T3 are captured into T2 or T4 in response to a signal at their associated input pins. Timer T3 is reloaded with the contents of T2 or T4 either by an external signal or by a selectable state transition of its toggle latch. When both T2 and T4 are configured to alternately reload T3 with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. With its maximum resolution of 200 ns (@ fOSC=40 MHz), the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can independently count up or down, clocked with an input clock which is derived from a programmable prescaler. Concatenation of the timers is supported via the output toggle latch of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin. The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin, and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. 3.7 A/D Converter For analog signal measurement, a 10-bit A/D converter with 10 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation which returns the conversion result for an analog channel within 9.75 µs @ fOSC=40 MHz. Overrun error detection capability is provided for the conversion result register: an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete. For applications which require less than 10 analog input channels, the remaining channels can be used as digital input port pins. The A/D converter of the SAB 80C166 supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is once sampled and converted into a digital result. In the Single Channel Continous mode, the analog level is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of ertering and exiting interrupt routines for each data transfer. 3.8 Serial Channels Serial communication with other microcontrollers, processors, terminals, or external peripheral components is provided by two serial interfaces with identical functionality, Serial Channel 0 (ASC0) and Serial Channel 1 (ASC1).
Semiconductor Group
37
System Description
They are upward compatible with the serial ports of the Siemens SAB 8051x microcontroller family and support full-duplex asynchronous communication up to 625 Kbaud and half-duplex synchronous communication up to 2.5 Mbaud. Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning. For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for each serial channel. In the synchronous mode, one data byte is transmitted or received synchronously to a shift clock which is generated by the SAB 80C166. In the asynchronous mode, an 8- or 9-bit data frame is transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data+wake up bit mode), and a loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated if the last character received has not been read out of the receive buffer register at the time reception of a new character is complete. 3.9 Watchdog Timer The Watchdog Timer of the SAB 80C166 represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer of the SAB 80C166 is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The Watchdog Timer of the SAB 80C166 is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. When the software has been designed to service the Watchdog Timer before it overflows, the Watchdog Timer times out if the program does not progress properly due to hardware or software related failures. When the Watchdog Timer overflows, it generates an internal hardware reset and pulls the RSTOUT# pin low in order to allow external hardware components to reset. The Watchdog Timer of the SAB 80C166 is a 16-bit timer which can either be clocked with fOSC/ 4 or fOSC/256. The high byte of the Watchdog Timer register can be set to a prespecified reload value in order to allow further variation of the monimored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 µs and 420 ms can be monitored (@ fOSC=40 MHz). The default Watchdog Timer interval after reset is 6.55 ms. 3.10 Parallel Ports The SAB 80C166 provides 76 I/O lines which are organized into four 16-bit I/O ports (Port 0 through 3), one 2-bit I/O port (Port 4), and one 10-bit input port (Port 5). All port lines are bit addressable, and all lines of Port 0 through 4 are individually bit-wise programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched Semiconductor Group 38
System Description
to the high impedance state when configured as inputs. During the internal reset, all port pins are configured as inputs. Each port line has one programmable alternate input or output function associated with it. Ports 0 and 1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A16 and A17 in systems where segmentation is enabled to access more than 64 Kbytes of memory. Port 2 is associated with the capture inputs/compare outputs of the CAPCOM unit, and Port 3 includes alternate functions of timers, serial interfaces, optional bus control signals (WR#, BHE#, READY#), and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter. When anyone of these alternate functions is not used, the respective port line may be used as general purpose I/O line.
Semiconductor Group
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Peripherals
8
Peripherals
This chapter provides a description of the functionality and programming of the peripherals incorporated in the SAB 80C166. Each of the peripheral units is discussed in a separate section: the CAPCOM unit in section 8.1, the General Purpose Timers (GPT) in section 8.2, the A/D Converter in section 8.3, the Serial Channels in section 8.4, and the Watchdog Timer in section 8.5. Peripheral Interfaces The peripherals generally have two different types of interfaces, an interface to the CPU and an interface to external hardware. Communication between CPU and peripherals is performed through Special Function Registers (SFRs) and interrupts. The SFRs serve as control/status and data registers for the peripherals. Interrupt requests are generated by the peripherals based on specific events (e.g. operation complete, error) which occur during their operation. For interfacing with external hardware, specific pins of ports P2, P3, or P5 are used when an input or output function has been selected for a peripheral. During this time, the port pins are controlled by the peripheral (when used as outputs) or by the external hardware which controls the peripheral (when used as inputs). This is called the 'alternate (input or output) function' of a port pin, in contrast to its function as a general purpose I/O pin. Each port consists of a port data register and a direction control register (except for port 5 which is an input only port). The name Px (x=0..5) of a port data register is generally used to refer to the whole port Px. For reference to a port pin, the notation Px.y (y=0..15) for the associated bit in the port data register is used as well as the symbol for the alternate function of a port pin. This chapter about the peripherals will provide all information which is necessary to use the alternate functions of a port in conjunction with a peripheral. A detailed description of the internal port structure will be given in chapter 10 (Parallel Ports). Peripheral Timing Internal operation of CPU and peripherals is based on the oscillator frequency (fosc) divided by 2. The resulting frequency is referred to as 'system clock'. The basic time unit for internal operation of a chip is commonly called 'state time'. For the SAB 80C166, one state is defined as 2 periods of the oscillator frequency. When a 40 MHz oscillator is used, the internal system clock is 20 MHz, and 1 state lasts for 50 ns. The clock which is gated to the peripherals is independent from the CPU clock. During Idle mode, the CPU clock is stopped while the peripherals continue their operation. Peripheral SFRs may be accessed by the CPU on ceper state. When an SFR is written to by software in the same state where it is also to be modified by the peripheral, the software write operation has priority. Further details on peripheral timing are included in the specific sections about each peripheral.
Semiconductor Group
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Peripherals
Programming Hints (1) All SFRs reside in data page 3 of the memory space. Whenever SFRs are to be accessed through indirect or direct addressing with 16-bit (mem) addresses, it must be guaranteed that data page 3 is selected by one of the data page pointer registers DPP0 through DPP3. This is not required for accessing SFRs via short 8-bit (reg) addressing or via the Peripheral Event Controller (PEC), because in these cases the data page pointers are not used. (2) Byte write operations to word wide SFRs via indirect or direct 16-bit (mem) addressing or byte transfers via the PEC force zeros in the non-addressed byte. Byte write operations via short 8-bit (reg) addressing can only access the low byte of an SFR and force zeros in the high byte. It is therefore recommended to use the bit field instructions (BFLDL and BFLDH) to write to any number of bits in either byte of an SFR without disturbing the non-addressed byte and the unselected bits. (3) Some of the bits which are contained in the 80C166's SFRs are marked as 'reserved'. User software should never write '1's to reserved bits. These bits are currently not implemented and may be used in future SAB 80C166 family products to invoke new functions. In this case, the active state for these functions will be '1', and the inactive state will be '0'. In the SAB 80C166, the value read from reserved bits is 0. 8.1 Capture/Compare (CAPCOM) Unit The CAPCOM unit supports generation and control of timing sequences on up to 16 channels with a minimum of software intervention. The CAPCOM unit is typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation, or recording of the time at which specific events occur, and it also allows the implemenation of up to 16 software timers. The maximum resolution of the CAPROM unit is 400 ns (@ 40 MHz oscillatorn frequency). CAPCOM Block Diagram The CAPCOM unit consists of two 16-bit timers (T0 and T1), each with its own reload register (T0REL and T1REL), and a bank of sixteen dual purpose 16-bit capture/compare registers (CC0 through CC15). The input clock for T0 or T1 is programmable to several prescaled values of the system clock, or it can be derived from an overflow/underflow of timer T6 in block GPT2. T0 may also operate in counter mode allowing it to be clocked by an external event. Each capture/compare register may be programmed individually for capture or compare function, and each register may be allocated to either timer T0 or T1. Each capture/compare register has one pin of port 2 associated with it which serves as an input pin for the capture function or as an output pin for the compare function. The capture function causes the current timer contents to be latched into the capture/compare register based on an external event on its associated port 2 pin. The compare function may cause an output signal transition on that port 2 pin whose associated capture/compare register matches the current timer contents. Specific interrupt requests are generated up on each capture/compare event or upon timer overflow. Figure 8.1.1 shows a block diagram of the CAPCOM unit. .
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Peripherals
Reload Reg. System Clock Input GPT2 Timer T6 CC0IR 16 Port 2 Alternate Mode 16-Bit Capture / 16 Capture/Compare CAPCOM Timer T0IR Interrupt
CC15IO/P2.15 System Clock GPT2 Timer T6 Input CAPCOM Timer Control T1IR
CC15IR
Interrupt
Reload Reg.
Figure 8.1.1 CAPCOM Unit Block Diagram
Register Overview From the programmer's point of view, the term 'CAPCOM unit' refers to a set of SFRs which are associated with this peripheral, including the port pins which may be used for alternate input/output functions. As can be seen from figure 8.1.2, for each pin (e.g. P3.0) within a port there is a direction control bit (e.g. DP3.0) within the associated port direction control register (e.g. DP3). In this figure, those portions of port and direction registers which are not used by the CAPCOM unit for alternate functions are not shaded.
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Peripherals
Ports & Direction Control Data Registers Alternate Functions
DP3 P3 T0REL T0
Control Registers Interrupt Control
T0IC
T0IN/P3.0
T1REL T1 DP2 P2 CC0 CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 CC11 CC12 CC13 CC14 CC15
T01CON T1IC
CCM0
CC15IO ... CC0IO P2.15 ... P2.0
CC0IC CC1IC CC2IC CC3IC CC4IC CC5IC CC6IC CC7IC CC8IC CC9IC CC10IC CC11IC CC12IC CC13IC CC14IC CC15IC
CCM1
CCM2
CCM3
DP3 P3 P2 T0 T0REL T1 T1REL CC0 .. CC15 T01CON CCM0 .. CCM3 T0IC T1IC CC0IC .. CC15IC
Port 3 Direction Control Register Port 3 Data RegisterDP2Port 2 Direction Control Register Port 2 Data Register CAPCOM Timer 0 Register CAPCOM Timer 0 Reload Register CAPCOM Timer 1 Register CAPCOM Timer 1 Reload Register CAPCOM Registers 0 .. 15 CAPCOM Timer 0 and Timer 1 Control Register CAPCOM Mode Control Registers 0 .. 3 CAPCOM Timer 0 Interrupt Control Register CAPCOM Timer 1 Interrupt Control Register CAPCOM Register 0 .. 15 Interrupt Control Registers
Figure 8.1.2 SFRs and Port Pins Associated with the CAPCOM Unit Semiconductor Group 84
Peripherals
8.1.1
Timers T0 and T1
The primary use of the timers T0 and T1 is to provide two independent time bases (400 ns maximum resolution for the capture/compare registers, but they may also be used independent of the capture/compare registers. The functions of the timers T0 and T1 are controlled by the bit addressable 16-bit control register T01CON shown in figure 8.1.3. T1 is controlled by the upper byte, and T0 is controlled by the lower byte of T01CON.
T01CON (FF50h/A8h) 15 14 7 T1R 6 T0R
13 5
12
11 T1M
10
Reset Value: 0000h 9 8 T1I
4
3 T0M
2
1 T0I
0
Figure 8.1.3 CAPCOM Timer 0 and 1 Control Register T01CON
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Peripherals
Symbol T0I
Position T01CON [2 ..0]
Function Timer/Counter 0 Input Selection For Timer mode, see table 8.1.1 For Counter mode, see table 8.1.2 Timer/Counter 0 Mode Selection T0M = 0: Timer Mode T0M = 1: Counter Mode Timer/Counter 0 Run Bit T0R = 0: Timer/Counter 0 disabled T0R = 1: Timer/Counter 0 enabled
T0M
T01CON.3
T0R
T01CON.6
T1I
T01CON [10 .. 8] Timer/Counter 1 Input Selection For Timer mode, see table 8.1.1. For Counter mode, see table 8.1.2 T01CON.11 Timer/Counter 1 Mode Selection T1M = 0: Timer Mode T1M = 1: Counter Mode Timer/Counter 1 Run Bit. T1R = 0: Timer/Counter 1 disabled T1R = 1: Timer/Counter 1 enebled (reserved)
T1M
T1R
T01CON.14
T0R and T1R are the run flags of T0 and T1, respectively. They allow for enabling and disabling the timers. The following description of the timer modes and operation always applies to the enabled state of the timers, i.e., when both T0R and T1R are set to '1'. In all modes, both timer T0 and timer T1 are always counting upward. The current timer values are accessible by the CPU in timer registers T0 and T1, which are both non-bit-addressable SFRs. When T0 or T1 are written by the CPU in the state immediately before a timer increment or reload is to be performed, the CPU write operation has priority, and the increment or reload is disabled to guarantee correct timer operation.
Semiconductor Group
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Peripherals
8.1.1.1 Timer Mode Bits T0M and T1M in SFR T01CON select between timer or counter mode for T0 or T1, respectively. In timer mode (T0M=0 or T1M=0), the input clock for a timer is derived from the internal system clock divided by a programmable prescaler. The different options for the prescaler are selected separately for T0 and T1 by the bit fields T0I and T1I. The input frequencies fT0 and fT1 for T0 and T1 are determined as a function of the oscillator frequency as follows, where and represent the contents of the bit fields T0I and T1I: fOSC fOSC fT0= , fT1= 16 * 2 16 * 2 When a timer overflows from FFFFh to 0000h, it is reloaded with the value stored in its respective reload register T0REL or T1REL. The reload values determine the periods pT0 and pT1 between two consecutive overflows of T0 and T1 as follows:
pT0=
16 * (216 - ) * 2
,
fOSC
pT1=
16 * (216 - ) * 2
fOSC
The timer input frequencies, resolution, and periods which result from the selected prescaler option in T0I or T1I when using a 40 MHz oscillator are listed in table 8.1.1. The numbers for the timer periods are based on a reload value of 0000h. Note that some numbers may be rounded to 3 significant digits. Table 8.1.1 CAPCOM Timers T0 and T1 Input Frequencies, Resolution and Periods
fOSC= 40MHz
Prescaler for fOSC Input Frequency Resolution Period
Timer Input Selection T0I/T1I 000b 001b 010b 011b 100b 101b 110b 111b 16 32 64 128 256 512 1024 2048 2.5 1.25 625 312.5 156.25 78.125 39.06 19.53 MHz MHz kHz kHz kHz kHz kHz kHz 400 ns 800 ns 1.6 µs 3.2 µs 6.4 µs 12.8 µs 25.6 µs 51.2 µs 26 ms 52.5 ms 105 ms 210 ms 420 ms 840 ms 1.68 s 3.36 s
After a timer has been started by setting its run flag (T0R or T1R) to '1', the first increment will occur within the time interval which is defined by the selected timer resolution. All further increments occur exactly after the time defined by the timer resolution. When both timers are to be incremented or reloaded at the same time, T0 is always serviced one state before T1.
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Peripherals
8.1.1.2 Counter Mode Counter mode is selected for timer T0 or T1 by setting the appropriate mode selection bit (T0M or T1M) in register T01CON to '1'. Both timers can operate in counter mode by counting the overflows/underflows of timer T6 in block GPT2 (see section 8.2.2 for details on GPT2). In addition, timer T0 offers the capability of being clocked by external events. Either a positive, a negative, or both a positive and a negative transition at pin T0IN (alternate input function of port pin P3.0) can be selected to cause an increment of T0. When T1 is programmed to run in counter mode (T1M=1), bit field T1I is used to enable the overflows/underflows of timer T6 as the count source for T1. This is the only option for T1, and it is selected by the combination T1I=X00b. When bit field T1I is programmed to other combinations, timer T1 stops. When T0 is programmed to run in counter mode (T0M=1), bit field T0I is used to select the count source and transition which should cause a count trigger for T0. Table 8.1.2 shows the possible selections for the counter mode of timers T0 and T1. Table 8.1.2 Input Selection for T0 and T1 in Counter Mode
Counter T0 is Incremented on (2) Overflow or Underflow of GPT2 Timer T6 Positive External Transition at Pin T0IN Negative External Transition at Pin T0IN Positive and Negative Transition at T0IN X X X X T0I/T1I (1) 0 0 1 1 (0) 0 1 0 1 Overflow or Underflow of GPT2 Timer T6 (Counter T1 stops) (Counter T1 stops) (Counter T1 stops) Counter T1 is incremented on
In order to use pin P3.0/T0IN as external count input pin for T0, P3.0 must be configured as input, i.e., the corresponding direction control bit DP3.0 in register DP3 must be set to '0'. If P3.0/T0IN is configured as output, timer T0 may be clocked by modifying port data register bit P3.0 through software, e.g. for testing purposes. The maximum external input frequency to T0 in counter mode is fOSC/16 (1.25 MHz @ 40 MHz fOSC). To ensure that a signal transition is properly recognized, an external count input signal should be held for at least 8 state times before it changes its level again. The incremented count value appears in SFR T0 within 8 state times after the signal transition at pin T0IN. 8.1.1.3 Reload A reload of a timer with the 16-bit value stored in its associated reload register is performed in timer mode as well as in counter mode each time a timer overflows from FFFFh to 0000h. The reload registers T0REL and T1REL are not bit-addressable.
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Peripherals
8.1.1.4
Timer T0 and T1 Interrupts
Upon timer overflow, the corresponding timer interrupt request flag T0IR or T1IR for the respective timer will be set. This flag can be used to generate an interrupt or trigger a PEC service request when enabled by the interrupt enable bits T0IE or T1IE. Each of the two timers (T0 or T1) has its own bit-addressable interrupt control register (T0IC or T1IC) and its own interrupt vector (T0INT or T1INT). Figure 8.1.4 shows the organization of the interrupt control registers T0IC and T1IC. Refer to chapter 7 for more details on the interrupt control registers.
T0IC (FF9Ch/CEh)Reset Value: 0000h 7 6 5 4 3 2 1 0
T1IC (FF9Eh/CFhReset Value: 0000h 7 6 5 4 3 2 1 0
Figure 8.1.4 CAPCOM Timer T0 and T1 Interrupt Control Registers T0IC and T1IC 8.1.1.5 Block Diagram The following block diagrams illustrate the selection of the available functions for timer T0 and timer T1. Figure 8.1.5 shows a block diagram of timer T0, while figure 8.1.6 shows a block diagram of timer T1.
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Peripherals
T0I
Input Reload Reg. T0REL
System GPT2 Timer T6 P3.0
÷X CAPCOM Timer Edge T0R T0I
T0I T0M
Interrupt T0IR Request
Figure 8.1.5 CAPCOM Timer To Block Diagram
Reload Reg.
T1I
System
÷X CAPCOM Timer T1IR
Interrupt
GPT2 Timer T6 T1M T1R
Figure 8.1.6 CAPCOM Timer T1 Block Diagram 8.1.2 Capture/Compare Registers The sixteen 16-bit capture/compare registers CC0 through CC15 are used as data registers for capture or compare operations with respect to timer T0 and T1. The capture/ compare registers are not bit-addressable. Each of the registers CC0 through CC15 may be individually programmed for capture- or one of 4 different compare modes, and may be allocated individually to one of the timers T0 or T1. A special combination of compare modes additionally allows the implementation of a 'doubleregister' compare mode. When capture or compare operation is disabled for one of the registers, it may be used for general purpose variable storage.
Semiconductor Group
8 10
Peripherals
The functions of the 16 capture/compare registers are controlled by 4 bit-addressable 16-bit mode control registers named CCM0, CCM1, CCM2, and CCM3, which are all organized identically. Each register contains bits for the mode selection and timer allocation of four capture/compare registers. Figure 8.1.7 shows the organization of CAPCOM mode control register CCM0, while figure 8.1.8 shows the organization of CAPCOM mode control registers CCM1, CCM2, and CCM3. As the selection of the individual operating mode is identical for each of the capture/compare registers, only a detailed description of register CCM0 is included in figure 8.1.7. The description for registers CCM1 through CCM3 is identical except for the indices of the respective capture/compare registers. CCM0 (FF52h/A9h) 15 ACC3 7 ACC1 6 14 13 CCMOD3 5 CCMOD1 4 12 11 ACC2 3 ACC0 2 10 Reset Value: 0000h 9 CCMOD2 1 CCMOD0 0 8
Figure 8.1.7 CAPCOM Mode Control Register CCM0
Symbol CCMOD0 ACC0
Position CCM0 [2 .. 0] CCM0.3
CCMOD1 ACC1
CCM0 [6 .. 4] CCM0.7
CCMOD2 ACC2
CCM0 [10 .. 8] CCM0.11
CCMOD3 ACC3
CCM0 [14 .. 12] CCM0.15
Function Capture/Compare Register CC0 Mode Selection (see table 8.1.3) Capture/Compare Register CC0 Allocation Bit ACC0 = 0: CC0 allocated to Timer 0 ACC0 = 1: CC0 allocated to Timer 1 Capture/Compare Register CC1 Mode Selection (see table 8.1.3) Capture/Compare Register CC1 Allocation Bit ACC1 = 0: CC1 allocated to Timer 0 ACC1 = 1: CC1 allocated to Timer 1 Capture/Compare Register CC2 Mode Selection (see table 8.1.3) Capture/Compare Register CC2 Allocation Bit ACC2 = 0: CC2 allocated to Timer 0 ACC2 = 1: CC2 allocated to Timer 1 Capture/Compare Register CC3 Mode Selection (see table 8.1.3) Capture/Compare Register CC3 Allocation Bit ACC3 = 0: CC3 allocated to Timer 0 ACC3 = 1: CC3 allocated to Timer 1 8 11
Semiconductor Group
Peripherals
CCM1 (FF54h/AAh)
15 ACC7 14 13 CCMOD7 12 11 ACC6 10
Reset Value: 0000h
9 CCMOD6 8
7 ACC5
6
5 CCMOD5
4
3 ACC4
2
1 CCMOD4
0
CCM2 (FF56h/ABh)
15 ACC11 14 13 CCMOD11 12 11 ACC10 10
Reset Value: 0000h
9 CCMOD10 8
7 ACC9
6
5 CCMOD9
4
3 ACC8
2
1 CCMOD8
0
CCM3 (FF58h/ABh)
15 ACC15 14 13 CCMOD15 12 11 ACC14 10
Reset Value: 0000h
9 CCMOD14 8
7 ACC13
6
5 CCMOD13
4
3 ACC12
2
1 CCMOD12
0
Figure 8.1.8 CAPCOM Mode Control Registers CCM1, CCM2, CCM3
Semiconductor Group
8 12
Peripherals
Table 8.1.3 lists the possible capture and compare modes which can be programmed for each capture/compare register. The different modes are discussed in detail in the following subsections. Table 8.1.3 Capture/Compare Register Mode Selection; x=(0..15) CCMODx (2) (1) (0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 Function Capture/Compare Disabled Capture on Positive External Transition at Pin CCxIO Capture on Negative External Transition at Pin CCxIO Capture on Positive and Negative External Transition at Pin CCxIO Compare Mode 0: Interrupt only; several interrupts per timer period; enables double-register compare mode for registers CC8 through CC15 Compare Mode 1: Pin toggles on each match; several compare events per timer period; registers CC0 through CC7 have to be in this mode for double-register compare operation Compare Mode 2: Interrupt only; only one interrupt per timer period Compare Mode 3: Pin set on match: pin reset on timer overflow; only one compare event per timer period
1 1
1 1