Text preview for : HP500.pdf part of Compaq-HP HP500 Compaq-HP HP500.pdf
Back to : HP500.pdf | Home
1 2 3 4 5 6 7 8
PCB STACK UP
LAYER 1 : TOP
SW7 BLOCK DIAGRAM 01
LAYER 2 : SGND1 CPU CPU THERMAL SENSOR
FAN
LAYER 3 : IN1 Merom 14.318MHz
A A
PG 5
LAYER 4 : IN2
479P (uPGA)/46W
LAYER 5 : VCC PG 3,4 CLK_CPU_BCLK,CLK_CPU_BCLK#
CLK_MCH_BCLK,CLK_MCH_BCLK# CLOCK GEN
LAYER 6 : IN3 DREFCLK,DREFCLK# ALPR365K05
64pins
LAYER 7 : SGND2 DREFSSCLK,DREFSSCLK#
PG 2
LAYER 8 : BOT
LVDS
533/667 MHZ DDR II Panel Connector PG 22
DDR2-SODIMM1
PG 13,14
533/667 MHZ DDR II NORTH BRIDGE
DDR2-SODIMM2
PG 13,14
Crestline VGA
B
CRT Connector B
PG 21
PG 6~12
S-Video
I/O Board Connector PG 20
32.768KHz DMI LINK NBSRCCLK, NBSRCCLK#
USB2.0 (P2) (EXT Left Side)
SATA - HDD SATA USB
USB2.0 (P0,P1) (EXT Right Side)
PG 28 PG 32
SYSTEM CHARGER(MAX8724)
PAG 41 PATA - ODD 25MHz
IDE
PG 28 SOUTH BRIDGE MARVELL RJ45/Magnetics
SYSTEM POWER MAX8778 LAN
PAG 42 USB2.0 (P5)
8055/8039 PG 30
Bluetooth ICH-8M PG 29
PG 19
C 33MHz PCI C
DDR II SMDDR_VTERM Azalia
PG 15~18 PCIEx2
1.8V/1.8VSUS(TPS51116REGR)
PAG 46 USB2.0 (P6,P7) 1394/Card Reader
AUDIO MODEM USB2.0 P3
PCI7402
VCCP +1.5V AND GMCH
PG 25,26 PG 27 PG 23,24
1.05V(MAX8717)
PAG 43
LPC
24.576MHz 1394 P0
32.768KHz
VGACORE(1.025V)MAX1992 Audio KBC USB CAMERA
1394
PAG 45 Jacks
ene PG 32 SD/MMC/MS CONNECTOR
PG 25
KB3926 CARD READER PG 23
CPU CORE MAX8771
PG 24
PAG 44 PG 33
D D
PS/2 EXPRESS-CARD
Keyboard MINI-CARD
Flash Touchpad WLAN PROJECT : SW7
S/W&Led
PG 19
PG 33 PG 20 PG 31 Quanta Computer Inc.
Size Document Number Rev
BLOCK DIAGRAM 1A
Date: Friday, September 28, 2007 Sheet 1 of 44
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+3V
L37
1 2
BLM21PG600SN1D
+CK_VDD_MAIN
CLK_XTAL_IN 1
Y9
2
14.318MHZ
CLK_XTAL_OUT CLK_3GPLLREQ#
NEW-CARD_CLK_REQ#
R282
R276
2
2
1 10K/F
1 10K/F
+3V
02
1
1
120 ohms@100Mhz
1
1
1
1
1
C448 C447 C474 C475
C483 C482 C451 C466 C485 22pF/50V 22pF/50V
2
2
4.7uF/6.3V_6 4.7uF/6.3V_6 0.1uF/10V 0.1uF/10V 0.1uF/10V 0.1uF/10V 0.1uF/10V
2
2
2
2
2
14.318MHz
A L36 A
1 2 VDDCPU
BLM21PG600SN1D
1
C449 C450
C463
4.7uF/6.3V_6 4.7uF/6.3V_6
2
0.1uF/10V
L39
+CK_VDD_MAIN2 U24
1 2
BLM21PG600SN1D
120 ohms@100Mhz +CK_VDD_MAIN 16 54
VDDPLL3 CPUCLKT0 CLK_CPU_BCLK 3
1
1
1
1
1
C453 9 53
VDD48 CPUCLKC0 CLK_CPU_BCLK# 3
1
C455 C245 C486 C484 C464 C465
4.7uF/6.3V_6 4.7uF/6.3V_6 0.1uF/10V 0.1uF/10V 0.1uF/10V 0.1uF/10V 0.1uF/10V C467
2
61
VDDPCI CK505 51 CLK_MCH_BCLK 6
2
2
2
2
2
0.1uF/10V VDDREF CPUCLKT1
39 50 CLK_MCH_BCLK# 6
2
VDDCPU VDDSRC CPUCLKC1
55 VDDCPU
47 T18
+CK_VDD_MAIN2 CPUT2_ITP/SRCT8
12 VDD96I/O CPUT2_ITP/SRCC8 46 T17
20 VDDPLL3I/O
+3V 26 13
VDDSRCI/O DOTT_96/SRCT0 MCH_DREFCLK 7
+3V 45 14
VDDSRCI/O DOTC_96/SRCC0 MCH_DREFCLK# 7
36 VDDSRCI/O
27MHz_Nonss/SRCCLK1/SE1 17 DREF_SSCLK 7
2
49 VDDCPU_IO 27Mhz_ss/SRCCLC1/SE2 18 DREF_SSCLK# 7
2
4
B 48 B
R292 NC
SRCCLKT2/SATACL 21 CLK_PCIE_SATA 15
10K/F RP37 22
SRCCLKC2/SATACL CLK_PCIE_SATA# 15
4P2R-S-2.2K CLK_XTAL_IN 60
1
Q24 CLK_XTAL_OUT X1
59 X2 SRCCLKT3/CR#_C 24
2
TME 2N7002E 25
1
3
SRCCLKC3/CR#_D
3 1 CLK_SDATA 27
17,31 ICH_SMBDATA SRCCLKT4 CLK_PCIE_LAN 29
SRCCLKC4 28 CLK_PCIE_LAN# 29
R285
17 CK_PWG 56 CK_PWRGD/PD# PCI_STOP# 38 H_STP_PCI# 17
*4.7K CPU_MCH_BSEL1 R280 4.7K/F FSB 57 37
FSLB/TEST_MODE CPU_STOP# H_STP_CPU# 17
+3V
SRCCLKT6 41 CLK_PCIE_ICH 16
Q25 40
SRCCLKC6 CLK_PCIE_ICH# 16
2
2N7002E
CLK_SCLK 64 44
14,31 CLK_SCLK SCLK SRCCLKT7/CR#_F CLK_PCIE_MINI 31
3 1 CLK_SCLK CLK_SDATA 63 43
17,31 ICH_SMBCLK 14,31 CLK_SDATA SDATA SRCCLKC7/CR#_E CLK_PCIE_MINI# 31
0=overclocking SRCCLKT9 30 CLK_MCH_3GPLL 7
15 31 CLK_MCH_3GPLL# 7
of CPU and 19
GND SRCCLKC9
GND
SRC Allowed 11 GND48 SRCCLKT10 34 CLK_PCIE_EXPCARD 31
52 GNDCPU SRCCLKC10 35 CLK_PCIE_EXPCARD# 31
8 GNDPCI
1 = overclocking 58 33 NEW-CARD_CLK_REQ#_R R281 475/F NEW-CARD_CLK_REQ#
GNDREF SRCCLKT11/CR#_H NEW-CARD_CLK_REQ# 31
23 32 CLK_3GPLLREQ#_R R283 475/F CLK_3GPLLREQ#
of CPU and SRC GNDSRC SRCCLKC11/CR#_G CLK_3GPLLREQ# 7
29 GNDSRC
not Allowed 42 GNDSRC
1 PCI_EC R284 33
C PCICLK0/CR#_A CLK_PCI_EC 33 C
C487 *33pF/50V CLK_PCI_EC 3 PCI_PCCARD R291 33
PCICLK1/CR#_B CLK_PCI_PCCARD 23
4 TME
C503 *33pF/50V CLK_PCI_PCCARD PCICLK2/TME
PCICLK3 5
6 PCI_DBP R286 33
PCICLK4/27_SELECT CLK_PCI_DBP 31
C489 10pF/50V CLK_PCI_ICH
R287 33
CLK_PCI_ICH 16
C488 *33pF/50V CLK_PCI_DBP
7 ITP_EN R290 22
PCI_F5/ITP_EN CLK_7402_48M 24
C459 *33pF/50V CLK_ICH_14M R293 22
CLK_ICH_48M 17
10 FSA R298 4.7K/F CPU_MCH_BSEL0
USB_48MHZ/FSLA FSC R277 4.7K/F CPU_MCH_BSEL2
for EMI 62 R278 33
FSLC/TST_SL/REF CLK_ICH_14M 17
PCI_DBP
ICS9LPRS365AGLFT
2
R301 FSC FSB FSA CPU SRC PCI
10K/F CPU Clock select
1 0 1 100 100 33
1
R304 0
3 CPU_MCH_BSEL0 MCH_BSEL0 7
R308 *56
0 0 1 133 100 33
+1.05V_VCCP
0=UMA 0 1 1 166 100 33
1 = External VGA R306 1K/F
R279 0
0 1 0 200 100 33
3 CPU_MCH_BSEL1 MCH_BSEL1 7
R274 *0
0 0 0 266 100 33
ITP_EN 1 0 0 333 100 33
+1.05V_VCCP R273 1K/F
D D
1 1 0 400 100 33
1
R272 0
3 CPU_MCH_BSEL2 MCH_BSEL2 7
10K/F R271 *0
1 1 1 RSVD 100 33
R302 1K to NB only when
R270 1K/F XDP is implement.No
+1.05V_VCCP PROJECT : SW7
2
Disable ITP XDP can use 0 ohm
Quanta Computer Inc.
Size Document Number Rev
CLOCK GENERATOR 1A
Date: Friday, September 28, 2007 Sheet 2 of 44
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
H_A#[3..16] U22A H_D#[0..63] U22B H_D#[0..63]
03
6 H_A#[3..16] 6 H_D#[0..63]
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
A[3]# ADS# H_ADS# 6 D[0]# D[32]#
H_A#4 L5 E2 H_D#1 F24 AB24 H_D#33
A[4]# BNR# H_BNR# 6 D[1]# D[33]#
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34
A[5]# BPRI# H_BPRI# 6 D[2]# D[34]#
H_A#6 K5 H_D#3 G22 V26 H_D#35
H_A#7 A[6]# H_D#4 D[3]# D[35]# H_D#36
M3 A[7]# DEFER# H5 H_DEFER# 6 F23 D[4]# D[36]# V23
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
A[8]# DRDY# H_DRDY# 6 D[5]# D[37]#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
A[9]# DBSY# H_DBSY# 6 D[6]# D[38]#
H_A#10 N3 H_D#7 E23 U23 H_D#39
A A[10]# H_BR0# 6 D[7]# D[39]# A
DATA GRP 2
ADDR GROUP 0
DATA GRP 0
H_A#11 P5 F1 H_D#8 K24 Y25 H_D#40
H_A#12 A[11]# BR0# R60 56 H_D#9 D[8]# D[40]# H_D#41
P2 A[12]# G24 D[9]# D[41]# W22
H_A#13 L2 D20 H_IERR# 1 2 H_D#10 J24 Y23 H_D#42
CONTROL
A[13]# IERR# +1.05V_VCCP D[10]# D[42]#
H_A#14 P4 B3 H_D#11 J23 W24 H_D#43
A[14]# INIT# H_INIT# 15 D[11]# D[43]#
H_A#15 P1 H_D#12 H22 W25 H_D#44
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
R1 A[16]# LOCK# H4 H_LOCK# 6 F26 D[13]# D[45]# AA23
M1 R91 0 H_D#14 K22 AA24 H_D#46
6 H_ADSTB#0 H_REQ#[0..4] ADSTB[0]# D[14]# D[46]#
C1 H_D#15 H23 AB25 H_D#47
6 H_REQ#[0..4]