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5 4 3 2 1
CPU_CORE1
BD3G BLOCK DIAGRAM CPU_CORE2
CPU VDDNB_CORE CPU CORE PG 34 PCB STACK UP
LAYER 1 : TOP
+NB_CORE NB CORE
PG 35 LAYER 2 : GND
HOST 200MHz +1.35V_VDDHTTX (1.0~1.2V)
DDRII-SODIMM1 CPU_CLK LAYER 3 : IN1
AMD S1g2 CLOCK GENERATOR PCIE 100MHz
PG 8,9 NBGFX_CLK
LAYER 4 : IN2
DDR II 667 MHZ ICS9LPRS476AKLFT
D
Griffin Processor +2.5V +2.5V LAYER 5 : VCC D
USB 48MHz
NBGPP_CLK SLG8SP628VTR LAYER 6 : BOT
DDRII-SODIMM2 +1.5V +1.5V
RTM880N-795 REF 14MHz
PG 8,9 SBLINK_CLK
PG 3 +1.2V +1.2V
(638 S1g2 socket) Daughter Board
PG 4,5,6,7 +1.1V_NB PG 37
HDMI MMB Board
HT_LINK +1.2V_S5
PG 19 8040T(10/100)/8055(Giga) RJ45
PCI-E, 1X (port2)
+1.8VSUS +1.8VSUS
LVDS PG 24 PG 24 SMDDR USB Board
HDMI +1.8V
PG 20 +SMDDR_VTERM VTERM
LVDS(2ch) RX780/RS780M/RS780MC PCI-E, 1X (port0) PG 36
Mini Card (WLAN)
USB2.0 (P3)
S-VIDEO PG 25 Touch Pad board
+3VPCU
PG 18 21mm X 21mm, 528pin BGA
PCI-E, 1X (port1) +3V_S5 3V/5V
CRT TV LVDS HDMI MINI CARD (HD Video Decoder)
+3VSUS
CRT PG 25 Touch Pad board
+3V
C PG 18 (with Fingerprinter) C
PCI-E X16 PG 10,11,12,13 PCI-E, 1X (port3) NEW CARD +5VPCU
MXM Module USB2.0 (P6) +5V
PG 21 PG 25 PG 33
A_LINK (X4) SBSRC_CLK
SATA - HDD1 SATA0
PG 27 USB2.0 (P2) CCD USB2.0 (P0) USB2.0 I/O Ports X1
SB700 PG 28 (MB) PG 28
SATA - HDD2 SATA1
USB2.0 (P4) Fingerprint USB2.0 (P1) USB2.0 I/O Ports X1
PG 27 PG 19 (DB) PG 28
USB2.0 (P5) Felica USB2.0 (P7) USB2.0 I/O Ports X1
SATA - ODD SATA4 PG 28 (DB) PG 28
PG 27 USB2.0 (P8) Bluetooth
PG 28
B B
E - SATA SATA2 21mm X 21mm, 528pin BGA
PG ?? 4.5W(Ext)
Azalia Azalia Audio Codec
4.3W(Int) CX20561 PG 22
IDE /133
NAND FLASH CARD
PORT-A
PORT-B
PG ??
Speaker Amplifier MDC CONN FM Radio
PCI Bus 33MHz PG 14,15,16,17,18
PCI ROUTING TABLE G1441R51U
Device IDSEL# REQ#/GNT# Interrupt PG 22 PG 23 PG 23
OZ129 AD17 REQ0# / GNT0# INTE#
LPC
MDC
EC H.P/ MIC INT. INT.
Board
O2Micro OZ129T SPDIF JACK MIC S.P.
WPCE775 PG 23 PG 23 PG 23 PG 22
A A
PG 26 PG 29 RJ11
SPI
PROJECT : BD3G
Flash Touch
IEEE1394 CN. Card Reader VR FAN Keyboard CIR Kill SW Quanta Computer Inc.
ROM Pad
Size Document Number Rev
PG 23 PG 6 PG 30 PG 29 PG 28 PG 28 PG 30 BLOCK DIAGRAM
PG 26 PG 26 2A
Date: Thursday, May 29, 2008 Sheet 1 of 42
[email protected]
5 4 3 2 1
5 4 3 2 1
BD3G Power On Sequence BOM naming rule
From AC,Battery VIN
Items Function BTO Name Description
+5VPCU +3VPCU
D D
From PWM SYS_HWPG(PCU) 1 CIR v CIR@
From Power Button NBSWON# 2 HDMI port v HDM@
From EC S5_ON
3 HDMI transmitter v SI@ Silicon image SiI 1392/1932
+5V_S5
4 HDMI-CEC v CEC@ Renesas R8C/1B
+3V_S5
+1.2V_S5 5 Discrete VGA EV@ External VGA stuff
>10ms
From EC RSMRST# >100ms 6 UMA IV@ Internal VGA stuff
From EC DNBSWON#
7 New Card NEW@
From SB PCIE_WAKE#
From SB to EC SUSB#,SUSC# SUSON 8 RJ11 v MD@ Modem
From EC SUSON 9 RJ45-10/100 40@ Marvell 8040T(10/100)
+3VSUS +1.8VSUS SMDDR_VREF SMDDR_VTERM
10 RJ45-1000 55@ Marvell 8055(Giga)
From PWM HWPG_1.8V (SUS) MAINON
C From EC MAINON 11 Option for RJ45-10/100 and RJ45-1000 40@55@ Option for 8040/8055 C
+5V +3V +2.5V +1.8V +1.5V +NB_CORE +1.1V_NB +1.35V_VDDHTTX 12 TV v TV@
From PWM HWPG_1.5V,HWPG_2.5V,GFXPG(MAIN) HWPG_1.2_NB
13 Cardbus CB@
From EC VRON
CPU_CORE0, CPU_CORE1, CPU VDDNB_CORE, +1.2V 14 FM transmitter v FM@
From PWM VRM_PWRGD (CPU) 15 Mainstream ID LED MID@
HWPG 16 Low cost ID LED LID@
From EC ECPWROK
17 CCD v CCD@
SB_PWRGD 0ns~30ns
NB_PWRGD 18 INT MIC v I_MIC@
99ms~108ms
From SB CPU_PWRGD 19 AMD Hyper Flash HF@ Only for AMD platform
From SB PLTRST# PCIRST#
20 North bridge(690MC/RS780MC) MC@ Only for AMD platform
From SB CPU_LDT_RST#
From SB CPU_LDT_STOP# 21 North bridge(RX780) RX@ Only for AMD platform
B B
22 PowerXpress PX@ Only for AMD platform
23 PowerXpress with UMA SKU PX@IV@ Only for AMD platform
24 PowerXpress with Discrete VGA SKU PX@EV@ Only for AMD platform
25 Power player/Power Shift PP@ Only for AMD platform
*Note: EC will sampling SUSB# & EC SMBUS Table
SUSC# every 5ms. Battery CPU thermal Sensor EC EEPROM VGA thermal Sensor Touch Sensor HDMI CEC
AMD SB700 SMBUS Table EC775 SDATA1/SCLK1(+3VPCU) V
CLK GEN RAM Mini Card (HD-Decoder) Mini-card(WL) New Card HDMI EC775 SDATA2/SCLK2(+3VPCU) V V
SB700 SDATA0/SCLK0(+3V) V V V V V EC775 SDATA3/SCLK3(+3VPCU) V V V
A A
SB700 SDATA1/SCLK1(+3V_S5) V EC775 SDATA4/SCLK4(+3VPCU)
SB700 SDATA2/SCLK2(+3V_S5) Power +3VPCU +3V +3VPCU +3V +3VPCU +5VPCU
Power +3V +3V +3V +3V (Atheros) +3V +3V_S5 Reserve MOS ckt X V X V X V
Reserve MOS ckt V V V V V V
PROJECT : BD3G
Quanta Computer Inc.
Size Document Number Rev
SYSTEM INFORMATION 2A
Date: Thursday, May 29, 2008 Sheet 2 of 42
5 4 3 2 1
5 4 3 2 1
CLK_GEN_SLG8SP628 03
+3V +3V_CLK_VDD +1.2V +1.2V_CLK_VDDIO
L22 L23
BK1608HS600 BK1608HS600
C242 C236 C233 C219 C232 C535 C218 C231 C235 C221 C230 C234 C222 C216 C217
D 10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 D
ICS9LPRS480 P/N : ALPRS480000 Clock chip has internal serial terminations
for differencial pairs, external resistors are
SLG8SP628 P/N : AL8SP628000 reserved for debug purpose.
RTM880N-796 P/N : AL000880000
Place within 0.5"
of CLKGEN R147
U2
*261/F_4
4 50 CPUCLKP_R RP16 1 2 0X2 CPUCLKP
+3V +3V_CLK_48 +3V_CLK_VDD VDDDOT CPUK8_0T CPUCLKP 4
16 49 CPUCLKN_R 3 4 CPUCLKN To CPU
VDDSRC CPUK8_0C CPUCLKN 4
L21 26 VDDATIG
35 VDDSB_SRC RS780/RX780 for VGA
BK1608HS600 40 30 NBGFX_CLKP_R RP15 1 2 0X2 NBGFX_CLKP
VDDSATA ATIG0T NBGFX_CLKP 11
C220 48 29 NBGFX_CLKN_R 3 4 NBGFX_CLKN To NB
VDDCPU ATIG0C NBGFX_CLKN 11
55 28 MXM_REFCLKP_R RP14 1 2 EV@0X2 MXM_REFCLKP
VDDHTT ATIG1T MXM_REFCLKP 21
10/25 modify it 0.1u/10V_4 56 27 MXM_REFCLKN_R 3 4 MXM_REFCLKN
VDDREF ATIG1C MXM_REFCLKN 21
63 VDD48
C 37 SBLINK_CLKP_R RP18 1 2 0X2 SBLINK_CLKP C
SB_SRC0T SBLINK_CLKP 11
11 36 SBLINK_CLKN_R 3 4 SBLINK_CLKN To NB
+1.2V_CLK_VDDIO VDDSRC_IO0 SB_SRC0C SBLINK_CLKN 11
+3V 17 32 SBSRC_CLKP_R RP17 1 2 0X2 SBSRC_CLKP 11/4 check RX781 , RX781 not use
VDDSRC_IO1 SB_SRC1T SBSRC_CLKP 13
25 31 SBSRC_CLKN_R 3 4 SBSRC_CLKN To SB
VDDATIG_IO SB_SRC1C SBSRC_CLKN 13
34 VDDSB_SRC_IO
Q39 47 RX780 only
R498 *RHU002N06 VDDCPU_IO NBGPP_CLKP_R RP12 *0X2 NBGPP_CLKP
SRC0T 22 1 2 NBGPP_CLKP 11
2
21 NBGPP_CLKN_R 3 4 NBGPP_CLKN To NB
SRC0C NBGPP_CLKN 11
*10K_4 1 20 CLK_PCIE_NEW_R RP11 1 2 NEW@0X2 CLK_PCIE_NEW
GND48 SRC1T CLK_PCIE_NEW 25
CLKREQ4# 1 3 7 19 CLK_PCIE_NEW#_R 3 4 CLK_PCIE_NEW# To New Card
CLKREQ_LAN# 24 GNDDOT SRC1C CLK_PCIE_NEW# 25
10 15 CLK_PCIE_MINI_R RP2 1 2 0X2 CLK_PCIE_WLAN
GNDSRC0 SRC2T CLK_PCIE_WLAN 25
18 14 CLK_PCIE_MINI#_R 3 4 CLK_PCIE_WLAN# To Mini PCIE Slot
GNDSRC1 SRC2C CLK_PCIE_WLAN# 25
CLK_PCIE_MINI2_R RP1 0X2 CLK_PCIE_MINICARD
24
33
GNDATIG QFN64 SRC3T 13
12 CLK_PCIE_MINI2#_R
1
3
2
4 CLK_PCIE_MINICARD#
CLK_PCIE_MINICARD 25
To Mini PCIE Slot
GNDSB_SRC SRC3C CLK_PCIE_MINICARD# 25
+3V 43 9 CLK_PCIE_LAN_R RP3 1 2 0X2 CLK_PCIE_LAN
GNDSATA SRC4T CLK_PCIE_LAN 24
46 8 CLK_PCIE_LAN#_R 3 4 CLK_PCIE_LAN# To LAN Controller
GNDCPU SRC4C CLK_PCIE_LAN# 24
52 GNDHTT
Q30 60
R300 *RHU002N06 GNDREF
SRC6T/SATAT 42 T27
2
SRC6C/SATAC 41 T32
*10K_4 CG_XIN 61 6 T21
CLKREQ2# CG_XOUT X1 SRC7T/27M_SS
1 3 CLKREQ_WLAN# 25 62 X2 SRC7C/27M_NS 5 T22
B:(10/25) Add WLAN & LAN CLKREQ circuit (BOI request) 2 54 NBHT_REFCLKP_R RP13 1 2 0X2 NBHT_REFCLKP
7,8,14,25 PCLK_SMB SMBCLK HTT0T/66M NBHT_REFCLKP 11
3 53 NBHT_REFCLKN_R 3 4 NBHT_REFCLKN To NB
7,8,14,25 PDAT_SMB SMBDAT HTT0C/66M NBHT_REFCLKN 11
CLK_PD# 51 64 CLK_48M_USB_R R446 33_4 CLK_48M_USB To SB
PD# 48MHz_0 CLK_48M_USB 14
T25 23 59 SEL_HTT66
B NEW_CLKREQ# CLKREQ0# REF0/SEL_HTT66 SEL_SATA B
25 NEW_CLKREQ# 45 CLKREQ1# REF1/SEL_SATA 58 Ra
CLKREQ2# 44 57 SEL_27 R141 158/F_4 EXT_NB_OSC To NB
CLKREQ2# REF2/SEL_27 EXT_NB_OSC 11
T33 39 R138 90.9/F_4
CLKREQ4# CLKREQ3#
38 CLKREQ4#
Rb NB CLOCK INPUT TABLE
TGND0
TGND1
TGND2
TGND3
TGND4
TGND5
TGND6
TGND7
TGND8
TGND9
12/8 change from 20p to 33p
C201 C541 NB CLOCKS RX780 RS780
C225 33p/50V_4 *10p/50V_4 *10p/50V_4 RX780 RS780
SLG8SP628 HT_REFCLKP 100M DIFF 100M DIFF
65
66
67
68
69
70
71
72
73
74
1 2 CG_XIN