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8-Bit CMOS Single-Chip Microcontroller
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SAB 80C517A/83C517A-5 8-Bit CMOS Single-Chip Microcontroller
Addendum to User's Manual SAB 80C517/80C537 05.94
Edition 05.94 This edition was realized using the software system FrameMaker®. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1994. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
SAB 80C517A/83C517A-5 Revision History: 05.94 Previous Version: Page 3-8 4-1 5-3 5-10/5-11 11.92
Subjects (major changes since last revision 11.92) S0RELL adresses corrected HWPD pin number corrected TS/TC in table 5-1 corrected CC4EN bit names and table 5-3 corrected
Device Specifications SAB 80C517A/83C517A-5 Revision History: 05.94 Previous Releases: Page 5 4 6-14 several 2 25,26,30 33 39 57 60 62 65 several 66 68 Page 25 51 65 67 74 Page 47 01.94/08.93/11.92/10.91/04.91
Subjects (changes since last revision 04.91) Pin configuration P-MQFP-100-2 added Pin differences updated Pin numbers for P-MQFP-100-2 package added Correction of P-MRFP-100 into P-MQFP-100-2 Ordering information for 40 to + 110 °C versions Correction of register names S0RELL, SCON, ADCON, ICRON and SBUF Figure 4 corrected Figure 8 corrected PE/SWD function description completed Correct ordering numbers Test condition for VOH, VOH1 corrected tPXIZ name corrected tAVIV, tAZPL values corrected Minimum clock frequence is now 3.5 MHz tQVWH (data setup before WR) corrected and added tLLAX2 corrected Subjects (changes since last version 08.93) Corrected SFR name S0RELL Below "Termination of HWPD Mode": 4th paragraph with ident corrected Description of tLLIV corrected Program Memory Read Cycle: fPXAV added Oscillator circuit drawings: MQFP-100-2 pin numbers added. Subjects (changes since last revision 01.94) Minor changes on several pages Table 6 corrected
80C517A/83C517A-5
Contents
Page
1 2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 4 4.1 4.2 4.3 5 5.1 5.2 5.3 5.4 5.4.1 5.4.2 5.5 6 6.1 6.2 6.3 7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Program Memory, ROM Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Architecture for the XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Accesses to XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Control of XRAM in the SAB 80C517A . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Behaviour of Port0 and Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Additional Hardware Power Down Mode in the SAB 80C517A . . . . . . . . . . 4-1 Hardware Power Down Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Fast internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Digital I/O Port Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 10-bit A/D-Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Additional Compare Mode for the Concurrent Compare Unit . . . . . . . . . . . 5-8 New Baud Rate Generators for Serial Channel 0 and Serial Channel 1 . . 5-14 Serial Channel 0 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 Serial Channel 1 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 Modified Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Additional Interrupt for Compare Registers CM0 to CM7 . . . . . . . . . . . . . . . 6-1 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Semiconductor Group
Introduction
1
Introduction
The SAB 80C517A is a superset of the high end microcontroller SAB 80C517. While maintaining all architectural and operational characteristics of the SAB 80C517 the SAB 80C517A incorporates more on-chip RAM as well as some enhancements in the compare / capture unit. The oscillator watchdog got an improved functionality. Also the operating frequency is higher than that of the SAB 80C517.
SAB 80C517A / 83C517A-5 In this manual, any reference made to the SAB 80C517A applies to both versions, the SAB 80C517A and the SAB 83C517A-5, unless otherwise noted. Furthermore only new features of the SAB 80C517A in addition to the features of the SAB 80C517A/83C517A-5 are described. For additional reference, the user's manual of the SAB 80C517/80C537 (Ord. No. B258-H6075-G1-X7600) should be used.
Semiconductor Group
1-1
Introduction
Listed below is a summary of the main features of the SAB 80C517A:
q SAB 80C517A/83C517A-5, up to q q q q q Fast 32-bit division, 16-bit multiplication, 32-
q q
q
18 MHz operation frequency 32 K×8 ROM (SAB 83C517A-5 only, ROMProtection available) 256×8 on-chip RAM 2K×8 on-chip RAM (XRAM) Superset of SAB 80C51 architecture: 1 µs instruction cycle time at 12 MHz 666 ns instruction cycle time at 18 MHz 256 directly addressable bits Boolean processor 64 Kbyte external data and program memory addressing Four 16-bit timer/counters Powerful 16-bit compare/capture unit (CCU) with up to 21 high-speed or PWM output channels and 5 capture inputs Versatile "fail-safe" provisions
q q q q q q q q q
q
bit normalize and shift by peripheral MUL/ DIV unit (MDU) Eight data pointers for external memory addressing Seventeen interrupt vectors, four priority levels selectable genuine 10-bit A/D converter with 12 multiplexed inputs Two full duplex serial interfa ce s with programmable Baudrate-Generators Fully upward compatible with SAB 80C515, SAB 80C517, SAB 80C515A Extended power saving modes Fast Power-On Reset Nine ports: 56 I/O lines, 12 input lines Three temperature ranges available: 0 to 70 °C (T1) 40 to + 85 °C (T3) 40 to + 110 °C (T4) Plastic packages: P-LCC-84 P-MQFP-100-2
The pin functions of the SAB 80C517A are identical with those of the SAB 80C517/80C537 with one exception:
Package PLCC-84/60
SAB 80C517A HWPD
SAB 80C517 / 80C537
VSS
PMRFP-100/72
Semiconductor Group
1-2
Fundamental Structure
2
Fundamental Structure
The SAB 80C517A/83C517A-5 is a high-end member of the Siemens SAB 8051 family of microcontrollers. It is designed in Siemens ACMOS technology and based on the SAB 8051 architecture. ACMOS is a technology which combines high-speed and density characteristics with low-power consumption or dissipation. While maintaining all the SAB 80C517 features and operating characteristics the SAB 80C517A is expanded in its "fail-safe" characteristics and timer capabilities. Furthermore, the SAB 80C517A additionally contains 2 kByte of on-chip RAM (called XRAM), a 10bit A/D converter with 12 multiplexed inputs, enhanced Baud Rate Generators and the capabilities of the Compare Capture Unit are improved. The SAB 80C517A is identical with the SAB 83C517A-5 except that it lacks the on-chip program memory. The SAB 80C517A / 83C517A-5 is supplied in a 84-pin plastic leaded chip carrier package (P-LCC-84) and in a 100-pin plastic metric rectangular flat package (P-MRFP-100).
The essential enhancements to the SAB 80C517 are: Additional 2KByte RAM on chip. 32 kByte on-chip program memory (SAB 83C517A-5 only) 12-channel 10-bit A/D Converter Additional Compare Mode for Concurrent Compare function at Port 5; up to eight pins on P5 can be either set or reset on a compare match in two additional compare registers. Dedicated interrupt vector for the 16-bit compare registers CM0-CM7: Interrupt requested on a compare match in one of the eight compare channels (eight request flags are available) New baud rate generator for Serial Channel 0 Expanded baud rate range for Serial Channel 1 Hardware controlled Power Down Mode Improved functionality of the Oscillator Watchdog High speed operation of the device (up to 18 MHz crystal frequency)
Figure 2-1 shows a block diagram of the SAB 80C517A
Semiconductor Group
2-1
Fundamental Structure
Figure 2-1, Block Diagram of the SAB 80C517A
Semiconductor Group
2-2
Memory Organization
3
Memory Organization
According to the SAB 8051 architecture, the SAB 80C517A has separate address spaces for program and data memory. Figure 3-1 illustrates the mapping of address spaces.
Figure 3-1 Memory Map
Semiconductor Group
3-1
Memory Organization
3.1
Program Memory, ROM Protection
The SAB 83C517A-5 has 32 Kbyte of on-chip ROM, while the SAB 80C517A has no internal ROM. The program memory can externally be expanded up to 64 Kbyte. Pin EA controls whether program fetches below address 8000H are done from internal or external memory. As a new feature the SAB 83C517A-5 offers the possibillity of protecting the internal ROM against unauthorized access. This protection is implemented in the ROM-Mask. Therefore, the decision ROM-Protection 'yes' or 'no' has to be made when delivering the ROM-Code. Once enabled, there is no way of disabling the ROM-Protection. Effect : The access to internal ROM done by an externally fetched MOVC instruction is disabled. Nevertheless, an access from internal ROM to external ROM is possible. To verify the read protected ROM-Code a special ROM-Verify-Mode is implemented. This mode also can be used to verify unprotected internal ROM.
ROM-Protection no
ROM-Verification Mode (see 'AC Characteristics')
Restrictions
ROM-Verification Mode 1 (standard 8051 Verification Mode) ROM-Verification Mode 2 ROM-Verification Mode 2 standard 8051 Verification Mode is disabled externally applied MOVC accessing to internal ROM is disabled
yes
Semiconductor Group
3-2
Memory Organization
3.2
Data Memory
The data memory space consists of an internal and an external memory space. The SAB 80C517A contains another 2 kByte of On-Chip RAM above the 256 Bytes internal RAM of the base type SAB 80C517. This RAM is called XRAM in this document. External Data Memory Up to 64 Kbyte external data memory can be addressed by instructions that use 8-bit or 16bit indirect addressing. For 8-bit addressing MOVX instructions in combination with registers R0 and R1 can be used. A 16-bit external memory addressing is supported by eight 16-bit datapointers. Registers XPAGE and SYSCON are controlling whether data fetches at addresses F800H to FFFFH are done from internal XRAM or from external data memory. Internal Data Memory The internal data memory is divided into four physically distinct blocks: the lower 128 bytes of RAM including four banks containing eight registers each the upper 128 byte of RAM the 128 byte special function register area a 2Kx8 area which is accessed like external RAM (MOVX-instructions), called XRAM implemented on chip at the address range fromF800H to FFFFH. Special Function Register SYSCON controls whether data is read or written (to) XRAM or external RAM
Semiconductor Group
3-3
Memory Organization
3.3
Special Function Registers
All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 81 special function registers include arithmetic registers, pointers, and registers that provide an interface between the CPU and the on-chip peripherals. There are also 128 directly addressable bits within the SFR area. All special function registers are listed in table 3-1 and table 3-2. In table 3-1 they are organized in numeric order of their addresses. In table 3-2 they are organized in groups which refer to the functional blocks of the SAB 80C517A. Table 3-1, Special Function Register Address 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH Register P0 1) SP DPL DPH (WDTL) (WDTH) WDTREL PCON TCON 1) TMOD TL0 TL1 TH0 TH1 P1 1) XPAGE DPSEL S0CON 1) S0BUF IEN2 S1CON S1BUF S1RELL Contents after Reset FFH 07H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH 00H XXXXX000B 00H XXH XX00 00X0B 0X00 0000B XXH 00H Address A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH Register P2 1) COMSETL COMSETH COMCLRL COMCLRH SETMSK CJRMSK IEN0 1) IP0 SORELL P3 1) SYSCON IEN1 1) IP1 S0RELH S1RELH Contents after Reset FFH 00H 00H 00H 00H 00H 00H 00H 00H D9H FFH XXXX XX01B 00H XX00 0000B XXXX XX11B XXXX XX11B
1) : Bit-addressable Special Function Register
Semiconductor Group
3-4
Memory Organization
Table 3-1, Special Function Register (cont“d) Address C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH CCH CDH CEH CFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH Register IRCON0 1) CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 T2CON 1) CC4EN CRCL CRCH TL2 TH2 CCL4 CCH4 PSW 1) IRCON1 CML0 CMH0 CML1 CMH1 CML2 CMH2 ADCON0 1) ADDATH ADDATL P7 ADCON1 P8 CTRELL CTRELH Contents after Reset 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H XXH XXXX 0000B XXH 00H 00H Address E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0 F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH Register ACC 1) CTCON CML3 CMH3 CML4 CMH4 CML5 CMH5 P4 1) MD0 MD1 MD2 MD3 MD4 MD5 ARCON B 1) CML6 CMH6 CML7 CMH7 CMEN CMSEL P5 1) P6 Contents after Reset 00H 0X00 0000B 00H 00H 00H 00H 00H 00H FFH XXH XXH XXH XXH XXH XXH 0XXX XXXXB 00H 00H 00H 00H 00H 00H 00H FFH FFH
1) : Bit-addressable Special Function Register
Semiconductor Group
3-5
Memory Organization
Table 3-1, Special Function Register (cont“d) Block XRAM Symbol XPAGE SYSCON CPU ACC B DPH DPL DPSEL PSW SP ADCON0 ADCON1 ADDATH ADDATL IEN0 CTCON 2) IEN1 IEN2 IP0 IP1 IRCON0 IRCON1 TCON 2) T2CON 2) ARCON MD0 MD1 MD2 MD3 MD4 MD5 CCEN CC4EN CCH1 CCH2 CCH3 CCH4 CCL1 Name Address Contents after Reset 00H XXXX XX01B3) 00H 00H 00H 00H XXXXX000B 3) 00H 07H 00H 00H 00H 00H 00H 0X00 0000B3) 00H XX00 00X0B 3) 00H XX00 0000B 00H 00H 00H 00H 0XXX XXXXB XXH XXH XXH XXH XXH XXH 00H 00H 00H 00H 00H 00H 00H
Page Address. Reg. for extended onchip 91H RAM XRAM Control Reg. B1H E0H 1) Accumulator B-Register F0H 1) Data Pointer, High Byte 83H Data Pointer, Low Byte 82H Data Pointer Select Register 92H Program Status Word Register D0H 1) Stack Pointer 81H A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Data Register Low Byte Interrupt Enable Register 0 Com. Timer Control Register Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Request Control Register Interrupt Request Control Register Timer Control Register Timer 2 Control Register Arithmetic Control Register Multiplication/Division Register 0 Multiplication/Division Register 1 Multiplication/Division Register 2 Multiplication/Division Register 3 Multiplication/Division Register 4 Multiplication/Division Register 5 Comp./Capture Enable Reg. Comp./Capture 4 Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 4, High Byte Comp./Capture Reg. 1, Low Byte D8H 1) DH D9H DAH A8H 1) E1H B8H 1) 9AH A9H B9H C0H 1) D1H 88H 1) 0C8H 1) EFH E9H EAH EBH ECH EDH EEH C1H C9H C3H C5H C7H CFH C2H
A/DConverter
Interrupt System
MUL/DIV Unit
Compare/ CaptureUnit (CCU), Timer2
1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is indeterminate
Semiconductor Group
3-6
Memory Organization
Table 3-1, Special Function Register Block Compare/ CaptureUnit (CCU) (cont“d) Symbol CCL2 CCL3 CCL4 CMEM CMH0 CMH1 CMH2 CMH3 CMH4 CMH5 CMH6 CMH7 CML0 CML1 CML2 CML3 CML4 CML5 CML6 CML7 CMSEL CRCH CRCL COMSETL COMSETH COMCLRL COMCLRH SETMSK CLRMSK CTCON CTRELH CTRELL TH2 TL2 T2CON Name Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Comp./Capture Reg. 4, Low Byte Compare Enable Register Compare Reg. 0, High Byte Compare Reg. 1, High Byte Compare Reg. 2, High Byte Compare Reg. 3, High Byte Compare Reg. 4, High Byte Compare Reg. 5, High Byte Compare Reg. 6, High Byte Compare Reg. 7, High Byte Compare Register 0, Low Byte Compare Register 1, Low Byte Compare Register 2, Low Byte Compare Register 3, Low Byte Compare Register 4, Low Byte Compare Register 5, Low Byte Compare Register 6, Low Byte Compare Register 7, Low Byte Compare Input Select Com./Rel./Capt. Reg. High Byte Com./Rel./Capt. Reg. Low Byte Compare register, Low Byte Compare register, High Byte Compare register, Low Byte Compare register, High Byte mask register, concerning COMSET mask register, concerning COMCLR Com. Timer Control Reg. Com. Timer Rel. Reg., High Byte Com. Timer Rel. Reg., Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Address C4H C6H CEH F6H D3H D5H D7H E3H E5H E7H F3H F5H D2H D4H D6H E2H E4H E6H F2H F4H F7H CBH CAH A1H A2H A3H A4H A5H A6H E1H DFH DEH CDH CCH C8H 1) Contents after Reset 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0X00 0000B 3) 00H 00H 00H 00H 00H
1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is indeterminate
Semiconductor Group
3-7
Memory Organization
Table 3-1, Special Function Register Block Ports Symbol P0 P1 P2 P3 P4 P5 P6 P7 P8 PCON ADCON0 2) PCON 2) S0BUF S0CON S0RELL S0RELH S1BUF S1CON S1RELL S1RELH TCON TH0 TH1 TL0 TL1 TMOD IEN0 2) IEN1 2) IP0 2) IP1 2) WDTREL Name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7, Analog/Digital Input Port 8, Analog/Digital Input, 4-bit Power Control Register A/D Converter Control Reg. Power Control Register Serial Channel 0 Buffer Reg. Serial Channel 0 Control Reg. Serial Channel 0 Reload Reg., low byte Serial Channel 0 Reload Reg., high byte Serial Channel 1 Buffer Reg. Serial Channel 1 Control Reg. Serial Channel 1 Reload Reg., low byte Serial Channel 1 Reload Reg., high byte Timer Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 Watchdog Timer Reload Reg. Address 80H 1) 90H 1) A0H 1) B0H 1) E8H 1) F8H 1) FAH DBH DDH 87H D8H 1) 87H 99H 98H 1) 0AAH BAH 9CH 9BH 9DH BBH 88H 1) 8CH 8DH 8AH 8BH 89H A8H 1) B8H 1) A9H B9H 86H Contents after Reset FFH FFH FFH FFH FFH FFH FFH 00H 00H 00H XXH 00H D9H XXXX XX11B3) XXH 3) 0X00 0000B 3) 00H XXXX XX11B 3) 00H 00H 00H 00H 00H 00H 00H 00H 00H XX00 0000B 3) 00H
Pow. Save Modes Serial Channels
Timer 0/ Timer 1
Watchdog
1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is indeterminate
Semiconductor Group
3-8
Memory Organization
3.4
Architecture for the XRAM
The contents of the XRAM is not affected by a reset or HW Power Down. After power-up the contents is undefined, while it remains unchanged during and after a reset or HW Power Down if the power supply is not turned off. The additional On-Chip RAM is logically located in the "external data memory" range at the upper end of the 64 KByte address range (F800H-FFFFH). It is possible to enable and disable (only by reset) the XRAM. If it is disabled the device shows the same behaviour as the parts without XRAM, i.e. all MOVX accesses use the external bus to physically external data memory. 3.4.1 Accesses to XRAM Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM. Note: If a reset occurs during a write operation to XRAM, the effect on XRAM depends on the cycle which the reset is detected at (MOVX is a 2-cycle instruction): Reset detection at cycle 1: The new value will not be written to XRAM. The old value is not affected. Reset detection at cycle 2: The old value in XRAM is overwritten by the new value. Accesses to XRAM using the DPTR There are a Read and a Write instruction from and to XRAM which use one of the 16-bit DPTR for indirect addressing. The instructions are: MOVX MOVX A, @DPTR @DPTR, A (Read) (Write)
Normally the use of these instructions would use a physically external memory. However, in the SAB 80C517A the XRAM is accessed if it is enabled and if the DPTR points to the XRAM address space (DPTR F800H).
Semiconductor Group
3-9
Memory Organization
Accesses to XRAM using the Registers R0/R1 The 8051 architecture provides also instructions for access to external data memory range which use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions are: MOVX MOVX A, @ Ri @Ri, A (Read) (Write)
In application systems, either a real 8-bit bus (with 8-bit address) is used or Port 2 serves as page register which selects pages of 256-Byte. However, the distinction, whether Port 2 is used as general purpose I/0 or as "page address" is made by the external system design. From the device's point of view it cannot be decided whether the Port 2 data is used externally as address or as I/0 data! Hence, a special page register is implemented into the SAB 80C517A to provide the possibility of accessing the XRAM also with the MOVX @Ri instructions, i.e. XPAGE serves the same function for the XRAM as Port 2 for external data memory. Special Function Register XPAGE Bit No. Addr. 91H The reset value of XPAGE is 00H. XPAGE can be set and read by software. Figures 3-2 to 3-4 show the dependencies of XPAGE- and Port 2 - addressing in order to explain the differencies in accessing XRAM, ext. RAM or what is to do when Port 2 is used as an I/O-port. MSB 7 6 5 4 3 2 1 LSB 0 XPAGE
Semiconductor Group
3 - 10
Memory Organization
Figure 3-2 Write Page Address to Port 2 MOV P2, pageaddress will write the page address to Port 2 and XPAGE-Register. When external RAM is to be accessed in the XRAM address range (F800H - FFFFH) XRAM has to be disabled. When additional external RAM is to be addressed in an address range XRAM (F800H) XRAM may remain being enabled and there is no need to overwrite XPAGE by a second move.
Semiconductor Group
3 - 11
Memory Organization
Figure 3-3 Write Page Address to XPAGE The page address is only written to XPAGE-register. Port 2 is available for addresses or I/O-Data. See figure 3-4 to see what happens when Port 2 is used as I/O-Port.
Semiconductor Group
3 - 12
Memory Organization
Figure 3-4 Use of Port 2 as I/O-Port At a write to Port 2, XRAM address in XPAGE-register will be overwritten because of the concurrent write to Port 2 and XPAGE-register. So whenever XRAM is used and the XRAM address differs from the byte written to Port 2 latch it is absolutely nessesary to rewrite XPAGE with page address.
Example: I/O-Data at Port 2 shall be 0AAH. A Byte shall be fetched from XRAM at address 0F830H MOV R0, #30H MOV P2, #0AAH MOV XPAGE, #0F8H MOVX A, @R0
; P2 shows 0AAH ; P2 still shows 0AAH but XRAM is addressed ; the contents of XRAM at 0F830H is moved to accu
Semiconductor Group
3 - 13
Memory Organization
The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri instructions. If the address formed from XPAGE and Ri is less than the XRAM address range, then an external access is performed. For the SAB 80C517A the contents of XPAGE must be greater or equal than F8H in order to use the XRAM. Of course, the XRAM must be enabled if it shall be used with MOVX @Ri instructions. Thus, the register XPAGE is used for addressing of the XRAM; additionally its contents are used for generating the internal XRAM select. If the contents of XPAGE is less than the XRAM address range then an external bus access is performed where the upper address byte is provided by P2 and not by XPAGE! Therefore, the software has to distinguish two cases, if the MOVX @Ri instructions with paging shall be used: The upper address byte must be written to XPAGE or P2; both writes selects the XRAM address range. b) Access to external memory: The upper address byte must be written to P2; XPAGE will be loaded with the same address in order to deselect the XRAM. The behaviour of Port0, Port2 and the RD/WR signals depends on the state of pin EA and on the control bits XMAP0 and XMAP1 in register SYSCON. a) Access to XRAM:
Semiconductor Group
3 - 14
Memory Organization
3.4.2 Control of XRAM in the SAB 80C517A There are two control bits in register SYSCON which control the use and the bus operation during ^ accesses to the additional On-Chip RAM in XDATA range ( = XRAM). Special Function Register SYSCON Bit No. Addr. 0B1H MSB 7 6 5 4 3 2 1 LSB 0
XMAP1 XMAP0 SYSCON
Bit XMAP0
Function Global enable/disable bit for XRAM memory. XMAP0 = 0: The access to XRAM (= On-Chip XDATA memory) is enabled. XMAP0 = 1: The access to XRAM is disabled. All MOVX accesses are performed by the external bus. Control bit for RD/WR signals during accesses to XRAM; this bit has no effect if XRAM is disabled (XMAP0 = 1) or if addresses outside the XRAM address range are used for MOVX accesses. XMAP1 = 0: The signals RD and WR are not activated during accesses to XRAM. XMAP1 = 1: The signals RD and WR are activated during accesses to XRAM.
XMAP1
Reset value of SYSCON is XXXX XX01B. The control bit XMAP0 is a global enable/disable bit for the additional On-Chip RAM (XRAM). If this bit is set, the XRAM is disabled, all MOVX accesses use external memory via the external bus. In this case the SAB80C517A can't use the additional On-Chip RAM and is compatible with the types without XRAM.
Semiconductor Group
3 - 15
Memory Organization
A hardware protection is done by an unsymetric latch at XMAP0-bit. A unintentional disabling of XRAM could be dangerous since indeterminate values could be read from external bus. To avoid this the XMAP-bit is forced to '1' only by reset. Additional during reset an internal capacitor is loaded. So the reset state is a disabled XRAM. Because of the load time of the capacitor XMAP0-bit once written to '0' (that is, discharging capacitor) cannot be set to '1' again by software. On the other hand any distortion (software hang up, noise,...) is not able to load this capacitor, too. That is, the stable status is XRAM enabled. The only way to disable XRAM after it was enabled is a reset. The clear instruction for the XMAP0-bit should be integrated in the program initialization routine before XRAM is used. In extremely noisy systems the user may have redundant clear instructions. The control bit XMAP1 is relevant only if the XRAM is accessed. In this case the external RD and WR signals at P3.6 and P3.7 are not activated during the access, if XMAP1 is cleared. For debug purposes it might be useful to have these signals available. This is performed if XMAP1 is set. 3.4.3 Behaviour of Port0 and Port2 The behaviour of Port 0 and P2 during a MOVX access depends on the control bits in register SYSCON and on the state of pin EA. The table 3-3 lists the various operating conditions. It shows the following characteristics: a) Use of P0 and P2 pins during the MOVX access. Bus: The pins work as external address/data bus. If (internal) XRAM is accessed, the data read from the XRAM can not be seen on the bus. I/0: The pins work as Input/Output lines under control of their latch.
b) Activation of the RD and WR pin during the access. c) Use of internal or external XDATA memory. The shaded areas describe the standard operation as each 80C51 device without on-chip XRAM behaves.
Semiconductor Group
3 - 16
EA = 0 EA = 1 XMAP1, XMAP0 X1 a)P0/P2Bus b)RD/WR active c)ext.memory is used a)P0/P2Bus a)P0/P2Bus (WR-Data only) b)RD/WR active b)RD/WR active c)XRAM is used c) ext.memory is used a)P0Bus P2I/O b)RD/WR active c)ext.memory is used a)P0Bus P2I/O b)RD/WR active c)ext.memory is used a)P0Bus a)P0Bus (WR-Data only) P2I/O P2I/O b)RD/WR active b)RD/WR active c)XRAM is used c)ext.memory is used a)P0/P2Bus b)RD/WR active c)ext.memory is used a)P0/P2Bus b)RD/WR active c)ext.memory is used a)P0/P2Bus b)RD/WR active c)ext.memory is used 00 10 X1 XMAP1, XMAP0 10 a)P0/P2Bus b)RD/WR active c)ext.memory is used a)P0/P2Bus a)P0/P2Bus a)P0/P2I/O (WR-Data only) b)RD/WR active b)RD/WR active b)RD/WR c)XRAM is used c) ext.memory inactive is used c)XRAM is used a)P0Bus P2I/O b)RD/WR active c)ext.memory is used a)P0Bus a)P0/P2I/O a)P0Bus (WR-Data only) P2I/O P2I/O b)RD/WR active b)RD/WR active b)RD/WR inactive c)XRAM is used c)ext.memory c)XRAM is used is used a)P0Bus P2I/O b)RD/WR active c)ext.memory is used a)P0Bus P2I/O b)RD/WR active c)ext.memory is used
Semiconductor Group
00
MOVX DPTR @DPTR < XRAM address range
a)P0/P2Bus b)RD/WR active c)ext.memory is used
DPTR XRAM address range
a)P0/P2Bus (WR-Data only) b)RD/WR inactive c)XRAM is used
MOVX @ Ri
3 - 17
XPAGE < XRAM addr.page range
a)P0Bus P2I/O b)RD/WR active c)ext.memory is used
XPAGE XRAM addr.page range
a)P0Bus (WR-Data only) P2I/O b)RD/WR inactive c)XRAM is used
modes compatible to 8051-family
Memory Organization
Table 3-3: Behaviour of P0/P2 and RD/WR During MOVX Accesses
System Reset
4 4.1
System Reset Additional Hardware Power Down Mode in the SAB 80C517A
The SAB 80C517A has an additional Power Down Mode which can be initiated by an external signal at a dedicated pin. This pin is labeled HWPD and is a floating input line (active low). This pin substitutes one of the VSS pins of the base types SAB 80C517 (PLCC84: Pin60; P-MQFP-100-2: Pin36). Because this new power down mode is activated by an external hardware signal this mode is referred to as Hardware Power Down Mode in opposite to the program controlled Software Power Down Mode. For a correct function of the Hardware Power Down Mode the oscillator watchdog unit including its internal RC oscillator is needed. Therefore this unit must be enabled by pin OWE (OWE = High), if the Hardware Power Down Mode shall be used. However, the control pin PE/SWD has no control function for the Hardware Power Down Mode; it enables and disables only the use of all software controlled power saving modes (Slow Down Mode, Idle Mode, Software Power Down Mode). The function of the new Hardware Power Down Mode is as follows: The pin HWPD controls this mode. If it is on logic high level (inactive) the part is running in the normal operating modes. If pin HWPD gets active (low level) the part enters the Hardware Power Down Mode; as mentioned above this is independent of the state of pin PE/SWD. HWPD is sampled once per machine cycle. If it is found active, the device starts a complete internal reset sequence. This takes two machine cycles; all pins have their default reset states during this time. This reset has exactly the same effects as a hardware reset; i.e.especially the watchdog timer is stopped and its status flag WDTS is cleared. In this phase the power consumption is not yet reduced. After completion of the internal reset both oscillators of the chip are disabled, the on-chip oscillator as well as the oscillator watchdog's RC oscillator. At the same time the port pins and several control lines enter a floating state as shown in table 4-1. In this state the power consumption is reduced to the power down current IPD. Also the supply voltage can be reduced. Table 4-1 also lists the voltages which may be applied at the pins during Hardware Power Down Mode without affecting the low power consumption.
Semiconductor Group
4-1
System Reset
Table 4-1, Status of all Pins During Hardware Power Down Mode Pins Status Voltage Range at Pin During HW-Power Down
P0, P1, P2, P3, P4, Floating outputs / P5, P6, P7, P8 Disabled input function EA PE/SWD XTAL1 XTAL2 PSEN, ALE active input
VSS VIN VCC VIN = VCC or VIN = VSS
active input, Pull-up resistor disabled VIN = VCC or VIN = VSS during HW power down active output disabled input function Floating outputs / Disabled input function (for test modes only) active supply pins pin may not be driven
VSS VIN VCC VSS VIN VCC
VAREF, VAGND OWE
VAGnd VIN VCC
active input; must be at high level for VIN = VCC start-up after HW PD; pull up resistor or disabled during HW-power down (VIN = VSS) active input; must be on high level if HW PD is used Floating output
Reset R0
VIN = VCC VSS VIN VCC
Semiconductor Group
4-2
System Reset
The power down state is maintained while pin HWPD is held active. If HWPD goes to high level (inactive state) an automatic start up procedure is performed: First the pins leave their floating condition and enter their default reset state as they had immediately before going to float state. Both oscillators are enabled (only if OWE = high). While the on-chip oscillator (with pins XTAL1 and XTAL2) usually needs a longer time for start-up, if not externally driven (with crystal approx. 1 ms), the oscillator watchdog's RC oscillator has a very short start-up time (typ. less than 2 microseconds). Because the oscillator watchdog is active it detects a failure condition if the on-chip oscillator hasn't yet started. Hence, the watchdog keeps the part in reset and supplies the internal clock from the RC oscillator. Finally, when the on-chip oscillator has started, the oscillator watchdog releases the part from reset after it performed a final internal reset sequence and switches the clock supply to the on-chip oscillator. This is exactly the same procedure as when the oscillator watchdog detects first a failure and then a recovering of the oscillator during normal operation. Therefore, also the oscillator watchdog status flag is set after restart from Hardware Power Down Mode. When automatic start of the watchdog was enabled (PE/SWD connected to V CC ), the Watchdog Timer will start, too (with its default reload value for time-out period). The SWD-Function of the PE/SWD Pin is sampled only by a hardware reset. Therefore at least one Power On Reset has to be performed.
Semiconductor Group
4-3
System Reset
4.2
Hardware Power Down Reset Timing
Following figures are showing the timing diagrams for entering (figure 4-1) and leaving (figure 4-2) the Hardware Power Down Mode. If there is only a short signal at pin HWPD (i.e. HWPD is sampled active only once), then a complete internal reset is executed. Afterwards the normal program execution starts again (figure 4-3). Note: Delay time caused by internal logic is not included. The Reset pin overrides the Hardware Power Down function, i.e. if reset gets active during Hardware Power Down it is terminated and the device performs the normal reset function. Thus, pin Reset has to be inactive during Hardware Power Down Mode.
Semiconductor Group
4-4
System Reset
Figure 4-1 Timing Diagram of Entering Hardware Power Down Mode
Semiconductor Group
4-5
System Reset
Figure 4-2 Timing Diagram of Leaving Hardware Power Down Mode Semiconductor Group 4-6
System Reset
Figure 4-3 Timing Diagram of Hardware Power Down Mode, HWPD-Pin is Active for only one cycle Semiconductor Group 4-7
System Reset
4.3
Fast internal Reset after Power-On
The SAB 80C517A can use the oscillator watchdog unit for a fast internal reset procedure after power-on. Figure 4-4 shows the power-on sequence under control of the oscillator watchdog. Normally the devices of the 8051 family (like the SAB 80C517) enter their default reset state not before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. Especially if a crystal is used the start up time of the oscillator is relatively long (typ. 1ms). During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins. In the SAB 80C517A the oscillator watchdog unit can avoid this situation. For doing this, the oscillator watchdog must be enabled. In this case, after power-on the oscillator watchdog's RC oscillator starts working within a very short start-up time (typ. less than 2 microseconds). In the following the watchdog circuitry detects a failure condition for the on-chip oscillator because this has not yet started (a failure is always recognized if the watchdog's RC oscillator runs faster than the on-chip oscillator). As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on-chip oscillator's output. This allows correct resetting of the part and brings also all ports to the defined state (see figure 4-4, I). The time period from power-on till reaching the reset state at the ports adds from the following terms: RC oscillator start-up synchronization of the RC oscillators divider-by-5 synchronization of the state and cycle counters reset procedure till correct port states are reached Delay between power-on and correct reset state: Typ.: 18 µs Max.: 34 µs < 2 µs <6T <6T < 12T
Semiconductor Group
4-8
System Reset
After the on-chip oscillator finally has started, the oscillator watchdog detects the correct function; then the watchdog still holds the reset active for a time period of 768 cycles of the RC oscillator in order to allow the oscillation of the on-chip oscillator to stabilize (figure 4-4, II). Subsequently the clock is supplied by the on-chip oscillator and the oscillator watchdog's reset request is released (figure 4-4, III). However, an externally applied reset still remains (figure 4-4, IV) active and the device does not start program execution (figure 4-4, V) before the external reset is also released. Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up. The reasons are as follows: Termination of Hardware Power Down Mode (a HWPD signal is overridden by reset) Termination of Software Power Down Mode Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence. The external reset signal must be hold active at least until the on-chip oscillator has started and the internal watchdog reset phase is completed. An external reset time of more than 5 ms should be sufficient in typical applications. If only a capacitor at pin Reset is used a value of 100 nF provides the desired reset time.
Semiconductor Group
4-9
System Reset
Figure 4-4 Power-On of the SAB 80C517A
Semiconductor Group
4 - 10
On-Chip Peripheral Components
5 5.1
On-Chip Peripheral Components Digital I/O Port Circuitry
To realize the Hardware Power Down Mode with floating Port pins in the SAB 80C517A/83C517A 5 the standard port structure used in the 8051 Family is modified (figure 5-1). The FETs p4, p5 and n2 are added. During Hardware Power Down this FETs disconnect the port pins from internal logic.
Figure 5-1 Port Structure
Semiconductor Group
5-1
On-Chip Peripheral Components
P1 and p3 are not active during Hardware Power Down. P1 is activated only for two oscillator periods if a 0-to-1 transition is programmed to the port pin (not possible during HWPD). P3 is turned off during reset state (also HWPD). For detailled description of the port structure please refer to the SAB 80C517/80C537 User's Manual.
Semiconductor Group
5-2
On-Chip Peripheral Components
5.2
10-bit A/D-Converter
In the SAB 80C517A is a new high performance / high speed 12-channel 10-bit A/D-Converter is implemented. Its successive approximation techniqe provides 7 µs conversion time (fOSC=16 MHz). The conversion principle is upward compatible to the one used in the SAB 80C517. The major components are shown in figure 5-1. The comparator is a fully differential comparator for a high power supply rejection ratio and very low offset voltages. The capacitor network is binary weighted providing 10-bit resolution. The table 5-1 below shows the sample time TS and the conversion time TC (including TS), which depend on fOSC and the selected prescaler (see also Bit ADCL in SFR ADCON 1). Table 5-1, ADC-Convertion Time
fOSC[MHz]
12 16 18
Prescaler ÷8 ÷ 16 ÷8 ÷ 16 ÷8 ÷ 16
fADC[MHz]
1.5 0.75 2.0 1.0 1.125
TS [µs]
1.33 2.8 2.0 4.0 3.555
TC [µs] (incl. TS)
8 16 7.0 14.0 12.4
Semiconductor Group
5-3
On-Chip Peripheral Components
Figure 5-1 10-Bit A/D-Converter
Semiconductor Group
5-4
On-Chip Peripheral Components
Special Function Registers ADCON0, ADCON1 MSB 7 BD LSB 0 MX0 ADCON0
Bit No. Addr. 0D8H
6 CLK
5 ADEX
4 BSY
3 ADM
2 MX2
1 MX1
Bit No.
MSB 7
6
5
4
3 MX3
2 MX2
1 MX1
LSB 0 MX0 ADCON1
Addr. 0DCH ADCL
These bits are not used in controlling A/D converter functions in the 80C517A
Bit ADEX BSY
Function Internal / external start of conversion. When set, the external start of conversion by P6.0 / ADST is enabled. Busy flag. This flag indicates whether a conversion is in progress (BSY = 1). The flag is cleared by hardware when the conversion is finished. A/D Conversion mode. When set, a continous conversion is selected. If cleared, the converter stops after one conversion. Select 12 input channels of the ADC. Bits MX0 to MX2 con be written or read either in ADCON0 or in ADCON1. ADC Clock. When set fADC = fOSC / 16. Has to be set when fOSC > 16 MHz
ADM
MX3 - MX0 ADCL
The reset value of ADCON0 and ADCON1 is 00H
Semiconductor Group
5-5
On-Chip Peripheral Components
Special Function Register ADDATH, ADDATL MSB 7 msb LSB 0 ADDATH
Bit No. Addr. 0D9H
6
5
4
3
2
1
Bit No. Addr. 0DAH
MSB 7
6 lsb
5
4
3
2
1
LSB 0 ADDATL
These bits are not used for conversion result
The reset value of ADDATH and ADDATL is 00H. The registers ADDATH (0D9H) and ADDATL (0DAH) contain the 10-bit conversion result. The data is read as two 8-bit bytes. Data is presented in left justified format (i.e. the msb is the most left-hand bit in a 16-bit word). To get a 10-bit conversion result two READ operations are required. Otherwise ADDATH contains the 8-bit conversion result.
Semiconductor Group
5-6
On-Chip Peripheral Components
A/D Converter Timing After a conversion has been started (by a write to ADDATL, external start by P6.0/ADST or in continous mode) the analog input voltage is sampled for 4 clock cycles. The analog source must be capable of charging the capacitor network of appr. 50 pF to full accuracy in this time. During this period the converter is susceptable to spikes and noise at the analog input, which may cause wrong codes at the digital outputs. Therefore RC-filtering at the analog inputs is recommended (see figure 5-2 below). Conversion of the sampled analog voltage takes place between the 4th an 14th clock cycle.
Figure 5-2 Recommended RC-filtering at the Analog Inputs
Semiconductor Group
5-7
On-Chip Peripheral Components
5.3
Additional Compare Mode for the Concurrent Compare Unit
The SAB 80C517A has an additional compare mode (compare mode 2) in the Compare/Capture Unit which can be used for the Concurrent Compare Output at P5. In this compare mode 2 the P5 pins are no longer general purpose I/O pins or under control of compare/capture register CC4, but under control of the new compare registers COMSET and COMCLR. These both 16-bit registers are always associated with Timer 2 (same as CRC, CC1 to CC4). Each of these registers consists of two 8-bit portions, i.e COMSET consists of COMSETL (address 0A1 H) and COMSETH (address 0A2H), COMCLR consists of COMCLRL (address 0A3H) and COMCLRH (address 0A4H) In compare mode 2 the concurrent compare output pins on Port 5 are used as follows (see figure 5-3): When a compare match occurs with register COMSET, a high level appears at the pins of port 5 whose corresponding bits in the mask register SETMSK (address 0A5H) are set. When a compare match occurs in register COMCLR, a low level appears at the pins of port 5 whose corresponding bits in the mask register CLRMSK (address 0A6H) are set. Additionally the Port 5 pins used for compare mode 2 may also be directly written to by write instructions to SFR P5. Of course, the pins can also be read under program control. If compare mode 2 shall be selected register CC4 must operate in compare mode 1 (with the corresponding output pin P1.4); thus, compare mode 2 is selected by enabling compare function for register CC4 (COCAH4=1; COCAL4=0 SFR CC4EN) and by programming bits COCOEN0 and COCOEN1 in SFR CC4EN. Like in concurrent compare mode associated with CC4, the number of port pins at P5 which serve the compare output function can be selected by bits COCON0COCON2 (in SFR CC4EN). If a set and reset request occurs at the same time (identical values in COMSET and COMCLR), the set operation takes precedence. It is also possible to use only the interrupts which are generated by matches in COMSET and COMCLR without affecting P5 ("software compare"). For this "interrupt-only" mode it is not necessary that the compare function at CC4 is selected.
Semiconductor Group
5-8
On-Chip Peripheral Components
Figure 5-3 Compare Mode 2 (Port 5 only)
Semiconductor Group
5-9
On-Chip Peripheral Components
Special Function Register CC4EN Bit No. MSB 7 LSB 0
COM0
6
5
4
3
2
1
COCAL4
0C9H
COCOEN1 COCON2 COCON1 COCON0 COCOEN0 COCAH4
CC4EN
Bit COCON2 COCON1 COCON0 COCAH4 COCAL4 0 0 1 1 COCOEN1 COCOEN0 COM0 0 1 0 1
Function Selects number of compare outputs at P5 (for compare modes 1 and 2); see table 2-2 Compare/capture mode for register CC4 and compare modes 1 and 2 at P5 Compare/capture at CC4 disabled Capture on falling/rising edge at pin P1.4/INT2/CC4 Compare enabled at CC4 Capture on write operation into register CCL4
Selection of compare modes 1 and 2 at P5; valid only in combination with certain configurations in COCAH4, COCAL4; see table 2-3 Setting of bit COCOEN0 automatically sets COM0 Compare Mode for register CC4 COM0 = 0 selects compare mode 0 COM0 = 1 selects compare mode 1 Setting of bit COCOEN0 automatically sets COM0
The reset value of SFR CC4EN is 00H.
COCON2 0 0 0 0 1 1 1 1
COCON1 0 0 1 1 0 0 1 1
COCON0 0 1 0 1 0 1 0 1
Function One additional output of CC4 at P5.0 Additional outputs of CC4 at P5.0 to P5.1 Additional outputs of CC4 at P5.0 to P5.2 Additional outputs of CC4 at P5.0 to P5.3 Additional outputs of CC4 at P5.0 to P5.4 Additional outputs of CC4 at P5.0 to P5.5 Additional outputs of CC4 at P5.0 to P5.6 Additional outputs of CC4 at P5.0 to P5.7
Semiconductor Group
5 - 10
On-Chip Peripheral Components
Table 5-3, Configurations for Concurrent Compare Mode and Compare Mode 2 at P5 COCAH4 0 0 COCAL4 0 0 COCOEN1 COCOEN0 0 1 0 0 Function of CC4 Compare / Capture disabled Compare / Capture disabled Function of Compare Modes at P5 Disabled Compare mode 2 selected, but only interrupt generation (ICR, ICS); no output signals Compare Mode 2 selected at P5 Disabled
0 0
0 1
1 0
1 0
Compare / Capture disabled Capture on falling/ rising edge at pin P1.4/INT2/CC4
0
1
1
0
Compare modes 2 selected, but olny interrupt generation (ICR, ICS); no output signals at P5 Disabled
1
0
0
0
1
0
0
1
1
0
1
0
Compare enable at CC4; Mode 0/1 is selected by COM0 Compare mode 1 enabled at CC4; COM0 is automatically set Compare enable at CC4; mode 0/1 is selected by COM0
Concurrent compare (mode 1) selected at P5
1
0
1
1
Compare mode 2 selected, but only interrupt generation (ICR, ICS); no output signals at P5 Compare mode 1 en- Compare Mode 2 abled at CC4; COM0 selected at P5 is automatically set Capture on write operation into register CCL4 Capture on write operation into register CCL4 Disabled
1
1
0
0
1
1
1
0
Compare mode 2 selected, but only interrupt generation (ICR, ICS); no output signals at P5
The other combinations are reserved and must not be used.
Semiconductor Group
5 - 11
On-Chip Peripheral Components
The following table 5-4 lists the SFR's with their addresses and default values after reset which are used in compare mode 2:
Table 5-4, Compare Mode 2, used SFR's and their default Reset Value SFR COMSETL COMSETH COMCLRL COMCLRH SETMSK CLRMSK CTCON CC4EN Address 0A1H 0A2H 0A3H 0A4H 0A5H 0A6H 0E1H 0C9H Default Value after Reset 00H 00H 00H 00H 00H 00H 0X00 0000B 00H
The compare registers COMSET and COMCLR have their dedicated interrupt vectors. The corresponding request flags are ICS for register COMSET and ICR for register COMCLR. The flags are set by a match in registers COMSET and COMCLR, when enabled. As long as the match condition is valid the request flags can't be reset (neither by hardware nor software). The request flags are located in SFR CTCON. Special Function Register CTCON Bit No. 0BAH MSB 7 T2PS1 LSB 0 CLK0 CTCON
6
5 ICR
4 ISC
3 CTF
2 CLK2
1 CLK1
Bit CLK0 CLK1 CLK2 CTF ICS ICR T2PS1
Function Same function as SAB 80C517
Interrupt request flag for Compare register COMSET. ICS is set when a compare match occured. Cleared when interrupt is processed. Interrupt request flag for Compare register COMRES. ICR is set when a compare match occured. Cleared when interrupt is processed. Prescaler select bit for Timer 2. See table 5-5
The default value of CTCON after reset is 0X00 0000B
Semiconductor Group
5 - 12
On-Chip Peripheral Components
Extended Prescaler for Timer 2 The prescaler for Timer 2 has an extended range. This prescaler divides the input clock for Timer 2 when it is operated in timer mode. In addition to the ÷ 2 option there are now scale ratings of ÷ 4 and ÷ 8 available. The rate is selected by the control bits T2PS (T2CON.7) and T2PS1 (CTCON.7). Table 5-5 lists all available options. This prescaler must not be used when Timer 2 is operated in counter mode.
Table 5-5, Timer 2 Prescaler T2PS1 (CTCON.7) 0 0 1 1 T2PS (T2CON.7) 0 1 0 1 Prescaler Ratio ÷1 ÷2 ÷4 ÷8
Semiconductor Group
5 - 13
On-Chip Peripheral Components
5.4
New Baud Rate Generators for Serial Channel 0 and Serial Channel 1
5.4.1 Serial Channel 0 Baud Rate Generator The Serial Channel 0 has a new baud rate generator which provides greater flexibility and better resolution. It substitutes the 80C517's baud rate generator at Serial Channel 0 which provides only 4.8 kBaud or 9.6 kBaud at 12 MHz crystal frequency. Since the new generator offers greater flexibility it is often possible to use it instead of Timer1 which is then free for other tasks. Figure 5-4 shows a block diagram of the new baud rate generator for Serial Channel 0. It consists of a free running 10-bit timer with fOSC /2 input frequency. On overflow of this timer there is an automatic reload from the registers S0RELL (address AAH) and S0RELH (address BAH). The lower 8 bits of the timer are reloaded from S0RELL, while the upper two bits are reloaded from bit 0 and 1 of register S0RELH. The baud rate timer is reloaded by writing to S0RELL.
Figure 5-4 Baud Rate Generator for Serial Interface 0 The default value after reset of S0RELL is 0D9H, S0 RELH contains XXXX XX11B.
Semiconductor Group
5 - 14
On-Chip Peripheral Components
Special Function Register S0RELH, S0RELL MSB 7 LSB 0 S0RELH
Bit No. Addr. 0BAH
6
5
4
3
2
1 msb
Bit No. Addr. 0AAH
MSB 7
6
5
4
3
2
1
LSB 0 lsb S0RELL
shaded areas are not used for programming the baudrate timer
Bit S0RELH.0-1 S0RELL.0-7
Function Reload value. Upper two bits of the timer reload value. Reload value. Lower 8 bit of timer reload value.
Reset value of S0RELL is 0D9H, S0RELH contains XXXX XXX11B.
Semiconductor Group
5 - 15
On-Chip Peripheral Components
Figure 5-5 shows a block diagram of the options available for baud rate generation of Serial Channel 0. It is a fully compatible superset of the functionality of the SAB 80C517. The new baud rate generator can be used in modes 1 and 3 of the Serial Channel 0. It is activated by setting bit BD (ADCON0.7). This also starts the baud rate timer. When Timer1 shall be used for baud rate generation, bit BD must be cleared. In any case, bit SMOD (PCON.7) selects an additional divider by two. The default values after reset in registers S0RELL and S0RELH provide a baud rate of 4.8 kBaud (with SMOD = 0) or 9.6 kBaud (with SMOD = 1) at 12 MHz oscillator frequency. This guarantees full compatibility to the SAB 80C517.
Figure 5-5 Block Diagram of Baud Rate Generation for Serial Interface 0 If the new baud rate generator is used the baud rate of Serial Channel 0 in Mode 1 and 3 can be determined as follows: 2SMOD x oscillator frequency 64 x (210 S0REL) with S0REL = S0RELH.1 0, S0RELL.7 0
Mode 1, 3 baud rate =
Semiconductor Group
5 - 16
On-Chip Peripheral Components
5.4.2 Serial Channel 1 Baud Rate Generator A new baud rate generator for Serial Channel 1 now offers a wider range of selectable baud rates. Especially a baud rate of 1200 baud can be achieved now. The baud rate generator itself is identical with the one used for Serial Channel 0. It consists of a free running 10-bit timer with FOSC /2 input frequency. On overflow of this timer there is an automatic reload from the registers S1RELL (address 9DH) and S1RELH (address BBH). The lower 8 bits of the timer are reloaded from S1RELL, while the upper two bits are reloaded from bit 0 and 1 of register S1RELH. The baud rate timer is reloaded by writing to S1RELL. The baud rate in mode A and B can be determined by the following formula: oscillator frequency 32 x (210 S1REL) with S1REL = S1RELH.1 0, S1RELL.7 0 Figure 5-6 shows a block diagram of the baud rate generator for Serial Interface 1.
Mode A, B baud rate =
Figure 5-6 Baud Rate Generator for Serial Interface 1
Semiconductor Group
5 - 17
On-Chip Peripheral Components
Special Function Register SRELH, SRELL MSB 7 LSB 0 S1RELH
Bit No. Addr. 0BBH
6
5
4
3
2
1 msb
Bit No. Addr. 09DH
MSB 7
6
5
4
3
2
1
LSB 0 lsb S1RELL
shaded areas are not used for programming the baudrate timer
Bit S1RELH.0-1 S1RELL.0-7
Function Reload value. Upper two bits of the timer reload value. Reload value. Lower 8 bit of timer reload value.
Reset value of S1RELL is 00H, S1RELH contains XXXX XXX11B.
Semiconductor Group
5 - 18
On-Chip Peripheral Components
5.5
Modified Oscillator Watchdog Unit
The SAB 80C517A has a new oscillator watchdog unit that has an improved functionality with respect to the SAB 80C517's oscillator watchdog. Use of the Oscillator Watchdog Unit The unit serves three functions: Monitoring of the on-chip oscillator's function. The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset; if the failure condition disappears (i.e. the onchip oscillator has a higher frequency than the RC oscillator), the part executes a final reset phase of appr. 0.5 ms in order to allow the oscillatior to stabilize; then the oscillator watchdog reset is released and the part starts program execution again. Restart from the Hardware Power Down Mode. If the Hardware Power Down Mode is terminated the oscillator watchdog has to control the correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog function is only part of the complete Hardware Power Down sequence; however, the watchdog works identically to the monitoring function. Fast internal reset after power-on. In this function the oscillator watchdog unit provides a clock supply for the reset before the onchip oscillator has started. In this case the oscillator watchdog unit also works identically to the monitoring function. If the oscillator watchdog unit shall be used it must be enabled (this is done by applying high level to the control pin OWE).
Semiconductor Group
5 - 19
On-Chip Peripheral Components
Detailled Description of the Oscillator Watchdog Unit Figure 5-7 shows the block diagram of the oscillator watchdog unit. It consists of an internal RC oscillator which provides the reference frequency for the comparison with the frequency of the onchip oscillator. The RC oscillator can be enabled/disabled by the control pin OWE . If it is disabled the complete unit has no function.
Figure 5-7 Oscillator Watchdog Unit Special Function Register IP0 (Address 0A9H) Bit No. 0A9H MSB 7 OWDS 6 WDTS 5 IP0.5 4 IP0.4 3 IP0.3 2 IP0.2 1 IP0.1 LSB 0 IP0.0 IP0
These bits are not used in controlling the fail safe mechanisms.
Bit OWDS
Function Oscillator watchdog timer status flag. Set by hardware when an oscillator watchdog reset occurred. Can be cleared or set by software.
Reset value of IP0 is 00H.
Semiconductor Group
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On-Chip Peripheral Components
The frequency coming from the RC oscillator is divided by 5 and compared to the on-chip oscillator's frequency. If the frequency coming from the on-chip oscillator is found lower than the frequency derived from the RC oscillator the watchdog detects a failure condition (the oscillation at the on-chip oscillator could stop because of crystal damage etc.). In this case it switches the input of the internal clock system to the output of the RC oscillator. This means that the part is being clocked even if the on-chip oscillator has stopped or has not yet started. At the same time the watchdog activates the internal reset in order to bring the part in its defined reset state. The reset is performed because clock is available from the RC oscillator. This internal watchdog reset has the same effects as an externally applied reset signal with the following exception: The Watchdog Timer Status flag WDTS (IP0.6) is not reset (the Watchdog Timer however is stopped) and bit OWDS is set. This allows the software to examine error conditions detected by the Watchdog Timer even if meanwhile an oscillator failure occured. The oscillator watchdog is able to detect a recovery of the on-chip oscillator after a failure. If the frequency derived from the on-chip oscillator is again higher than the reference the watchdog starts a final reset sequence which takes typ. 1 ms. Within that time the clock is still supplied by the RC oscillator and the part is held in reset. This allows a reliable stabilization of the on chip oscillator. After that, the watchdog toggles the clock supply back to the on-chip oscillator and releases the reset request. If no external reset is applied in this moment the part will start program execution. If an external reset is active, however, the device will keep the reset state until also the external reset request disappears. Furthermore, the status flag OWDS (IP0.7) is set if the oscillator watchdog was active. The status flag can be evaluated by software to detect that a reset was caused by the oscillator watchdog. The flag OWDS can be set or cleared by software. An external reset request, however, also resets OWDS (and WDTS).
Semiconductor Group
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Interrupt System
6 6.1
Interrupt System Additional Interrupt for Compare Registers CM0 to CM7
There is an additional interrupt which is vectored to on a compare match in one of the eight comparators of the compare registers CM0 to CM7, when compare mode 1 is selected for the corresponding channel (assigned to Timer 2 by control bit CMSEL.x). For that purpose the SAB 80C517A provides eight interrupt request flags (in SFR IRCON1, address 0D1H) which are ORed to form the interrupt request for that vector, i.e. each of the eight comparators has its own request flag. Thus the service routine may decide which compare match requested the interrupt. The corresponding request flag is set by every match in the compare channel when the Compare Mode 1 is selected for this channel (assigned to Timer 2). If Compare Mode 0 is selected for a channel (assigned to the Compare Timer), the corresponding interrupt request flag will not be set on a compare match. This interrupt is enabled by setting the enable bit ECMP in SFR IEN2. If this bit is set the program vectors to location 0A3H if one of the eight request flags in IRCON 1 is set. Figure 6-1 shows a functional block diagram of the new structure concerning the interrupts. The further functions of this compare unit keep full compatibility to the SAB 80C517.
Semiconductor Group
6-1
Interrupt System
Figure 6-1 Interrupts of Compare Registers CM0-CM7 Assigned to Timer II
Semiconductor Group
6-2
Interrupt System
Special Function Register IRCON1 MSB 7 ICMP7 LSB 0
Bit No. 0D1H
6
5
4
3
2
1
ICMP6 ICMP5 ICMP4 ICMP3 ICMP2
ICMP1 ICMP0 IRCON1
Bit ICMPx
Function Compare x interrupt request flag. Set by hardware when a compare match in compare mode 1 with compare register CMx occured (only, if compare function enabled for CMx). ICMPx must be cleared by software (CMSEL.x = 0 and CMEN.x = 1).
The reset value of IRCON1 is 00H.
Semiconductor Group
6-3
Interrupt System
6.2
Interrupt Structure
This section summarizes the expanded interrupt structure of the SAB 80C517A which has 3 new interrupt vectors in addition to the 14 vectors of the SAB 80C517. Thus, 17 vectors are available now. The new interrupt sources are: 1. Request Flags ICMP0 to ICMP7: These eight request flags are set by compare matches in the compare registers CM0-7, if the compare function is enabled and compare mode 1 is selected for the corresponding register SCM0-7. Interrupt vector: Enable Bit: Priority: 0093H ECMP (IEN2.2) Same priority as IE1/IEX3, programmed by IP1.2/IP0.2
2. Request Flag: ICS Interrupt Vector: Enable Bit: Priority:
This request flag is set by a compare match in compare register COMSET. 00A3H ECS (IEN2.4) Same priority as RI0+TI0/IEX5, programmed by IP1.4/IP0.4
3. Request Flag: ICR Interrupt Vector: Enable Bit: Priority:
This request flag is set by a compare match in compare register COMCLR 00ABH ECR (IEN2.5) Same priority as TF2+EXF2/IEX6, programmed by IP1.5/IP0.5
Semiconductor Group
6-4
Interrupt System
3.1
Priority Level Structure
The following tables show the SFR IEN2, the priority level grouping (table 6-1) and the priority within level (table 6-2). The principle of the priority level selection is identical to the SAB 80C517, i.e. a pair or triple can be programmed to one of four priority levels. Special Function Register IEN2 MSB 7 LSB 0 ES1 IEN2
Bit No. 09AH
6
5 ECR
4 ECS
3 ECT
2 ECMP
1
Bit ES1 ECMP ECT ECS ECR
Function Enable serial interrupt of interface 1. Enables or disables the interrupt of serial interface 1. If ES1 = 0, the interrupt is disabled. Enables interrupt on compare match in compare registers