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XEROX
Mesa Processor Principles of Operation
Version 4.0
May 1985
Office Systems Division
2400 Geng Road
Palo Alto, California 94303
J.
Mesa Processor Principles of Operation
Notice
This document is being provided for information only. Xerox makes no warranties or representations of any kind
relative to this document or its use, including implied warranties of merchantability or of fitness for a particular
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manner.
The information contained herein is subject to change without any obligation of notice on the part of Xerox.
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Copyright c> 1985 by Xerox Corporation.
All Rights Reserved.
Table of contents
1 Introduction
1.1 Technical Summary 1-2
1.1.1 High Level Languages . 1-2
1.1.2 Compact Program Representation . 1-2
1.1.3 Compact Data Representation . 1-3
1.1.4 Read Only Relocatable Code 1-3
1.1.5 Stack Machine . 1-3
1.1.6 Control Transfers . 1-3
1.1.7 Process Mechanism 1-3
1.1.8 Virtual Memory 1-4
1.1.9 Protection . 1-4
1.2 Terminology . ., 1-4
1.2.1 Architecture 1-4
1.2.2 Processor 1-4
1.2.3 Programmer 1-5
1.3 Conventions . 1-5
1.3.1 Type Checking. 1-6
1.3.2 Type Representation 1-6
1.3.3 Subrange Types 1-6
1.3.4 Enumerated Types. 1-6
1.3.5 Pointers 1-6
1.3.6 Arrays and Records 1-7
1.3.7 Type Conversion 1-7
1.3.8 Built-in Routines 1-7
1.3.9 Control Flow 1-7
1.3.10 Signals and Errors . 1-7
1.3.11 Instruction Descriptions 1-8
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2 Data Types
2.1 Basic Data Types 2-1
2.1.1 Unspecified 2-2
2.1.2 Bit, Nibble, Byte 2-2
2.1.3 Basic Operators 2-2
2.2 Numeric Types 2-3
2.2.1 Cardinal 2-4
2.2.2 Integer. 2-4
2.2.3 Real 2-4
2.3 Long and Pointer Types 2-4
2.3.1 Long Types 2-4
2.3.2 Pointer Types 2-5
2.4 Type Conversion . 2-6
2.4.1 Assignment 2-6
2.4.2 SignedIUnsigned Conversions . 2-6
2.4.3 ShortiLong Conversions 2-7
2.4.4 Pointer Conversions 2-7
3 Memory Organization
3.1 Virtual Memory 3-1
3.1.1 Virtual Memory Mapping 3-2
3.1.2 Memory Map Instructions . 3-5
3.1.3 Virtual Memory Access 3-6
3.1.4 Virtual Memory Data Structures 3-7
3.2 Main Data Spaces. 3-10
3.2.1 Main Data Space Access 3-11
3.2.2 Main Data Space Data structures 3-12
3.2.3 Frame Overhead Access 3-15
3.3 Processor Memories 3-16
3.3.1 Control Registers 3-16
3.3.2 Evaluation Stack 3-18
3.3.3 Data and Status Registers . 3-20
3.3.4 Register Instructions 3-21
4 Instruction Interpreter
4.1 Interpreter 4-1
4.2 Instruction Formats 4-2
J.
4.3 Instruction Fetch . 4-2
4.4 Address Calculation 4-3
4.5 Instruction Execution. 4-4
4.6 Exceptions 4-5
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Mesa Processor Principles of Operation
4.6.1 Traps and Faults 4-5
4.6.2 Interrupts . 4-7
4.7 Initial State 4-7
5 Stack Instructions
5.1 Stack Primitives . 5-1
5.2 Check Instructions 5-3
5.3 Unary Operations 5-4
5.4 "Logical Operations 5-5
5.5 Arithmetic Operations 5-7
5.6 Comparison Operations 5-11
5.7 Floating Point Operations 5-11
6 Jump Instructions
6.1 Unconditional Jumps . 6-1
6.2 Equality Jumps 6-2
6.3 Signed Jumps. 6-5
6.4 Unsigned Jumps . 6-5
6.5 Indexed Jumps 6-6
7 Assignment Instructions
7.1 Immediate Instructions 7-1
7.2 Frame Instructions 7-2
7.2.1 Local Frame Access 7-3
7.2.2 Global Frame Access 7-6
7.3 Pointer Instructions 7-7
7.3.1 Direct Pointer Instructions. 7-8
7.3.2 Indirect Pointer Instructions 7-12
7.4 String Instructions 7-14
7.4.1 Read String 7-15
7.4.2 Write String 7-16
7.5 Field Instructions 7-16
7.5.1 ReadField. 7-18
7.5.2 Write Field. 7-19
7.5.3 Put Swapped Field . 7-21
8 Block Transfers
8.1 Interpreter 8-1
8.2 Bit Boundary Block Transfers 8-4
8.3 Byte Boundary Block Transfers 8-6
8.4 Bit Boundary Block Transfer . 8-7
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8.4.1 Bit Transfer Utilities 8-8
8.4.2 Bit Block Transfer . 8-8
8.4.3 Text Block Transfer 8-16
9 Data Types
9.1 Control Links. 9-1
9.1.1 Frame Control Links 9-2
9.1.2 Indirect Control Links . 9-3
9.1.3 Procedure Descriptors . 9-3
9.2 Frame Allocation. 9-4
9.2.1 Frame Allocation Vector 9-4
9.2.2 Frame Allocation Primitives 9-6
9.2.3 Frame Allocation Instructions . 9-7
9.3 Control Transfer Primitive 9-7
9.4 Control Transfer Instructions. 9-10
9.4.1 Local Function Calls 9-10
9.4.2 External Function Calls 9-11
9.4.3 Nested Function Calls. 9-13
9.4.4 Returns 9-13
9.4.5 Coroutine Transfers 9-14
9.4.6 Link Instructions 9-18
9.5 Traps 9-19
9.5.1 Trap Routines . 9-19
9.5.2 Trap Processing 9-21
9.5.3 Trap Handlers . 9-23
9.5.4 Breakpoints 9-25
9.5.5 XferTraps. 9-26
10 Processes
10.1 Data Structures 10-2
10.1.1 Process Data Area . 10-2
10.1.2 Process State Blocks 10-4
10.1.3 Monitor Locks . 10-6
10.1.4 Condition Variables 10-6
10.1.5 Process Queues. 10-6
10.2 Process Instructions . 10-7
10.2.1 Monitor Entry . 10-7
10.2.2 Monitor Exit 10-9
10.2.3 Monitor Wait 10-10
10.2.4 Monitor Reentry 10-11
10.2.5 Notify and Broadcast 10-12
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Mesa Processor Principles of Operation
10.2.6 Requeue 10-13
10.2.7 SetProcessPriority . 10-14
10.3 Queue Management . 10-14
10.3.1 Queuing Procedures 10-14
10.3.2 Cleanup Links . 10-16
10.4 Scheduling 10-18
10.4.1 Scheduler. 10-18
10.4.2 Process State 10-20
10.4.3 Faults. 10-23
10.4.4 Interrupts . 10-24
10.4.5 Timeouts 10-28
Appendices
A Values of Constants A-l
B Opcodes . B-1
References. R-1
Indexes
Primary Index. P-l
Mesa Code Index. MC-l
Opcode Names ON-1
Opcode Mnemonics . OM-l
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Table of contents
IDustrations
2.1 Sixteen Bit Word . 2-1
2.2 Thirty-two Bit Double Word 2-5
2.3 Double Word in Memory . 2-5
3.1 ' Virtual Memory Mapping. 3-3
3.2 Virtual Memory Structure