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Schematic Diagrams

System Block Diagram

5 in 1
CLICK BOARD
6-71-W1302-D02 Huron River System Block Diagram VDD3,VDD5
AUDIO BOARD 5V,3V,5VS,3VS,1.5VS,
USB Charger+HP+MIC+SPK
6-71-W1308-D02 1.5VS_CPU
Memory Termination
POWER SWITCH BOARD Sandy Bridge 800/1067 MHz 1.5V,0.75VS(VTT_MEM)
POWER SWITCH DDR3 / 1.5V 1.8VS
6-71-W130S-D02 37.5*37.5 mm DDRIII
DE-BUG BOARD PROCESSOR SO-DIMM0 1.05VS, 1.05VS_VTT
DeBug SYSTEM SMBUS
rPGA989B 0.1"~13 DDRIII
B.Schematic Diagrams




6-71-P180D-D02
SO-DIMM1 VCORE, 0.85VS
MAIN BOARD
6-71-W1300-D02 FDI DMI*4
0.5"~6.5" <=8" VGFX_CORE
HDMI
Sheet 1 of 48 DOCKING CONNECTOR
AUDIO BOARD
USB PORT2
System Block CLICK BOARD CRT CONNECTOR
<15"
INTERNAL
CougarPoint MIC HP MIC HEADPHONE
USB Charger
CRT SWITCH
Diagram TOUCH PAD GRAPHICS
Platform RJ-11 IN OUT (USB9)


LCD CONNECTOR, <8"
Controller SHEET 44
INTERNAL
LVDS SWITCH
GRAPHICS Hub (PCH) AZALIA
INT SPK R
25x25x0.6 mm MDC
EC Azalia Codec
SPI TPM MODULE
ITE 8518E 989 Balls FCBGA ALC269Q
128pins LQFP INT SPK L
MDC CON
14*14*1.6m m 33 MHz
non-VPRO:HM65
LPC VPRO:QM67
0.5"~11" BIOS AZALIA LINK 24 MHz
SPI
INT. K/B EC SMBUS
BIOS PCIE 100 MHz <12"
THERMAL SMART SMART SPI
SENSOR FAN BATTERY
32.768KHz
W83L771AWG
Mini PCIE Mini PCIE
ESATA+USB INTEL JMICRO
SOCKET SOCKET
USB2.0 SOCKET JMC261 C
<12" 3G CARD WLAN non-VPRO:82579V
SATA I/II 3.0Gb/s 480 Mbps (USB1) (USB3) (USB2) VPRO:82579LM
CARD READER 25
1"~16" (Optional)
MHz


RJ-45
7IN1
SOCKET
FINGER NEW CARD CCD USB3.0 PORT1
SATA HDD TI
(USB11) (USB10) (USB5)
TUSB7320
USB3.0 IC USB3.0 PORT2




B - 2 System Block Diagram

http://hobi-elektronika.net
Schematic Diagrams

Processor 1/7
Sandy Bridge Processor 1/7
( DMI,PEG,FDI )
1.05VS_VTT

U 23A 20 mil
J22 PEG_COMP R107 24.9_1%_04
PEG_ICOMPI J21
B27 PEG_ICOMPO H 22
16 DMI_TXN0 B25 DMI_RX#[0] PEG_RCOMPO
16 DMI_TXN1 A25 DMI_RX#[1]
16 DMI_TXN2 B24 DMI_RX#[2] K33
16 DMI_TXN3 DMI_RX#[3] PEG_RX#[0] M35
B28 PEG_RX#[1] L34
16 DMI_TXP0 B26 DMI_RX[0] PEG_RX#[2] J35
16 DMI_TXP1 A24 DMI_RX[1] PEG_RX#[3] J32
16 DMI_TXP2 B23 DMI_RX[2] PEG_RX#[4] H 34
16 DMI_TXP3 DMI_RX[3] PEG_RX#[5] H 31




DMI
G21 PEG_RX#[6] G33
16 DMI_RXN0 E22 DMI_TX#[0] PEG_RX#[7] G30
16 DMI_RXN1 F21 DMI_TX#[1] PEG_RX#[8] F35
16 DMI_RXN2 D21 DMI_TX#[2] PEG_RX#[9] E34
16 DMI_RXN3 DMI_TX#[3] PEG_RX#[10] E32
G22 PEG_RX#[11] D 33
16 DMI_RXP0 D22 DMI_TX[0] PEG_RX#[12] D 31
16 DMI_RXP1 F20 DMI_TX[1] PEG_RX#[13] B33




B.Schematic Diagrams
16 DMI_RXP2 C21 DMI_TX[2] PEG_RX#[14] C 32
16 DMI_RXP3 DMI_TX[3] PEG_RX#[15]




PCI EXPRESS* - GRAPHICS
J33
PEG_RX[0] L35
PEG_RX[1] K34
A21 PEG_RX[2] H 35
16 FDI_TXN0 H19 FDI0_TX#[0] PEG_RX[3] H 32
16 FDI_TXN1 E19 FDI0_TX#[1] PEG_RX[4] G34
16 FDI_TXN2 F18 FDI0_TX#[2] PEG_RX[5] G31
16 FDI_TXN3 B21 FDI0_TX#[3] PEG_RX[6] F33
16 FDI_TXN4 C20 FDI1_TX#[0] PEG_RX[7] F30




Intel(R) FDI
16 FDI_TXN5 D18 FDI1_TX#[1] PEG_RX[8] E35
16 FDI_TXN6 E17 FDI1_TX#[2] PEG_RX[9] E33
16 FDI_TXN7 FDI1_TX#[3] PEG_RX[10] F32
PEG_RX[11] D 34
A22 PEG_RX[12] E31

CAD NOTE: DP_COMPIO and ICOMPO signals
16
16
16
FDI_TXP0
FDI_TXP1
FDI_TXP2
G19
E20
G18
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
C 33
B32 Sheet 2 of 48
16 FDI_TXP3
should be shorted near balls and routed with
- typical impedance < 25 mohms
16
16
16
FDI_TXP4
FDI_TXP5
FDI_TXP6
B20
C19
D19
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
M29
M32
M31
Processor 1/7
F17 L32
16 FDI_TXP7 FDI1_TX[3] PEG_TX#[3] L29
1.05VS_VTT 1.05VS_VTT J18 PEG_TX#[4] K31
16 FDI_FSY NC0 J17 FDI0_FSY N C PEG_TX#[5] K28
16 FDI_FSY NC1 FDI1_FSY N C PEG_TX#[6] J30
H20 PEG_TX#[7] J28
16 FDI_INT FDI_INT PEG_TX#[8] H 29
J19 PEG_TX#[9] G27
16 FDI_LSY N C0 H17 FDI0_LSY NC PEG_TX#[10] E29
R383 R382
16 FDI_LSY N C1 FDI1_LSY NC PEG_TX#[11] F27
1K_04 24.9_1%_04 PEG_TX#[12]
EDP Function Disable D 28
PEG_TX#[13] F26
EDP_HPD: Pull-up10K- DISABLED PEG_TX#[14] E25
EDP_COMP A18 PEG_TX#[15]
A17 eDP_C OMPIO M28
DP Compensation Signal eDP_ICOMPO PEG_TX[0]
EDP_HPD# B16 M33
eDP_H PD # PEG_TX[1] M30
PEG_TX[2] L31
C15 PEG_TX[3] L28
D15 eDP_AUX PEG_TX[4] K30
eDP_AUX# PEG_TX[5] K27
PEG_TX[6] J29
C17 PEG_TX[7] J27
eDP
F16 eDP_TX[0] PEG_TX[8] H 28
C16 eDP_TX[1] PEG_TX[9] G28
G15 eDP_TX[2] PEG_TX[10] E28
eDP_TX[3] PEG_TX[11] F28
C18 PEG_TX[12] D 27
E16 eDP_TX#[0] PEG_TX[13] E26
3.3V D16 eDP_TX#[1] PEG_TX[14] D 25
F15 eDP_TX#[2] PEG_TX[15]
eDP_TX#[3]

47989-0732
1




PTH 1

*100K_NTC_06_B
2




3.3V
Q28
2 1 1:2 (4mils:8mils)
VCC OUT THERM_VOLT 27

C362 3
GND C372 R269
0.1u_10V_X7R_04
G711ST9U 0.1u_10V_X7R _04 3,8,11,14,15,18,23,24,26,28,29,30,32,33,36,37,39,40 3.3V
1 *10K_1%_04
3,5,19,20,21,39,41 1.05VS_VTT
3

9/20 2
EVT
PLACE NEAR U3




Processor 1/7 B - 3

http://hobi-elektronika.net
Schematic Diagrams

Processor 2/7

Processor Pullups/Pull downs
1.05VS_VTT

PU/PD for JTAG signals
1.05VS_VTT
Sandy Bridge Processor 2/7 H_PROCHOT#


H_CPUPWRGD_R R332
R35 62_04


10K_04

R322
R320
R321
51_04
51_04
*51_04
XDP_TMS
XDP_TDI_R
XDP_PREQ#
( CLK,MISC,JTAG ) C289 *0.1u_10V_X7R_04


R323 51_04 XDP_TDO_R
R324 51_04 XDP_TCLK U23B
R319 51_04 XDP_TRST# TRACE WIDTH 10MIL, LENGTH <500MILS

A28
H_SNB_IVB# C26 BCLK A27 CLK_EXP_P 15 DDR3 Compensation Signals
19 H_SNB_IVB# PROC_SELECT# BCLK# CLK_EXP_N 15




MISC

CLOCKS
3.3VS
AN34 SM_RCOMP_0 R339 140_1%_04
R338 1K_04 XDP_DBR_R SKTOCC# A16
DPLL_REF_SSCLK A15 CLK_DP_P 15 SM_RCOMP_1 R379 25.5_1%_04
DPLL_REF_SSCLK# CLK_DP_N 15
SM_RCOMP_2 R375 200_1%_04
B.Schematic Diagrams




H_CATERR# AL33
CATERR#


H_PECI_R AN33 R8 CPUDRAMRST#




THERMAL
R334 *10mil_04
19,27 H_PECI PECI SM_DRAMRST#




DDR3
MISC
R47 56_1%_04 H_PROCHOT#_D AL32 AK1 SM_RCOMP_0
41 H_PROCHOT#
Sheet 3 of 48 If PROCHOT# is not used, then it must
be terminated with a 68-O +-5% pull-up AN32
PROCHOT# SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
A5
A4
SM_RCOMP_1
SM_RCOMP_2
S3 circuit:- DRAM PWR GOOD logic

Processor 2/7 resistor to 1.05VS_VTT . THERMTRIP#


R331 *10mil_04 H_THRMTRIP#_R
19 H_THRMTRIP# AP29 XDP_PRDY # 3.3V 1.5VS_CPU
PRDY # AP27 XDP_PREQ#
PREQ#
AR26 XDP_TCLK
TCK AR27 XDP_TMS R310 R328
PM_SY NC_R AM34 TMS AP30 XDP_TRST#




PWR MANAGEMENT
R335 *10mil_04




JTAG & BPM
16 H_PM_SY NC PM_SYNC TRST# *200_1%_04 10K_04
AR28 XDP_TDI_R D20
TDI AP26 XDP_TDO_R 1 A
H_CPUPWRGD_RAP33 TDO 16 PM_DRAM_PWRGD C 3 PMSY S_PWRGD_BUF
R333 *10mil_04
19 H_CPUPWRGD UNCOREPWRGOOD 2 A
16,37 1.8VS_PWRGD
AL35 XDP_DBR_R *BAT54AWGH R314
PMSY S_PWRGD_BUF R327 130_1%_04 VDDPWRGOOD_R V8 DBR#
SM_DRAMPWROK *39_04
AT28 XDP_BPM0_R
BPM#[0] AR29 XDP_BPM1_R
BPM#[1] AR30 XDP_BPM2_R R316 0_04
Buffered reset to CPU




D
1.05VS_VTT BUF_CPU_RST# AR33 BPM#[2] AT30 XDP_BPM3_R Q24
RESET# BPM#[3] AP32 XDP_BPM4_R
R318 75_1%_04 R317 43.2_1%_04 BPM#[4] AR31 XDP_BPM5_R G
BPM#[5] AT31 XDP_BPM6_R 36,37,39 SUSB
*MTN7002ZHS3
6-13-43R21-28C




S
6 BPM#[6] AR32 XDP_BPM7_R
3.3VS D BPM#[7]
Q25A
R313 10K_04 2 G MTDN7002ZHS6R
S
3 1 47989-0732
D

5 G Q25B
S3 circuit:- DRAM_RST# to memory
S MTDN7002ZHS6R H_PROCHOT# should be high during S3
4




D
Q6 1.5V
R325 *1.5K_1%_04
18,25 PLT_RST# G
27 H_PROCHOT_EC
R330 MTN7002ZHS3 C76




S
R315 C286 R204 *0_04 R208
*750_1%_04 47p_50V_NPO_04
100K_04 68p_50V_NPO_04 10/1 R39 100K_04 1K_04

CAD Note: Capacitor