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5 4 3 2 1
PCB STACK UP
PS-Note (AMD) Block Diagram LAYER 1 : TOP
LAYER 2 : GND
LAYER 3 : IN1
LAYER 4 : VCC
D
AMD ASB1r2 DDR2 SO-DIMM 1 LAYER 5 : IN2 D
Clock Thermal PAGE-16 LAYER 6 : IN3
Gengerator Sensor Conesus LAYER 7 : GND
PAGE-06 DDR2 SO-DIMM 2
PAGE-03 PAGE-16 LAYER 8 : BOT
27mmX27mm 812pin BGA
PAGE-04~07
HT-LINK 16X
Sideport Memory
PAGE-08 PCI-e #1 Mini PCIe Slot WLAN
13.3" HD NORTH BRIDGE PAGE-24
LVDS
(1366x768) LCD RS780MN A13 PCI-e #2 Mini PCIe Slot WWAN
PAGE-17 SIM Card
C PAGE-25 C
CRT RGB
21mmX21mm, 528pin BGA Ethernet / 1G
PAGE-18 PCI-e #3 RJ-45
PCIE Realtek
HDMI PAGE-08~10
RTL8111DL-VB-GR PAGE-21
PAGE-19
PAGE-21
A_LINK 4X
HP/Mic HDA CODEC HD
USB-0~2 USB PORT X 3
Audio
Combo Jack Conexant PAGE-23
PAGE-28
CX20582 SOUTH BRIDGE USB-3 Bluetooth (BDC-2)
/ FUNCTION BOARD PAGE-20
PAGE-26
SB710 A14
Internal Internal USB-4
WWAN
B
MIC SPK PAGE-24 B
PAGE-20 PAGE-20
21mmX21mm, 528pin BGA USB-5 WLAN
SATA
2.5" HDD PAGE-11~15
PAGE-25
PAGE-22
Card Reader 4 in 1 Socket
LPC BUS USB-6 Realtek RTL5159
SD/MMC/MS/MS-Pro
PAGE-28
/ FUNCTION BOARD
SPI
ITE8502E Flash USB-7 Camera Conn. Camera Module
PAGE-17 LCD MODULE
PAGE-29 PAGE-29
G-SENSOR INT. TOUCH TRACK
A K/B PAD POINT Charger Battery A
PAGE-26 PAGE-27 PAGE-27 PAGE-27
PAGE-32 PAGE-32
Quanta Computer Inc.
PS-Note (AMD)
Size Document Number Rev.
C Block Diagram < MP >
Date: 10/28/2009, 03:15 PM Sheet : 1 of 43
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INDEX
PAGE# DESCRIPTION NOTE
Power Sequence 02
AC IN
1 SCHEMATIC BLOCK DIAGRAM
3V/5VPCU
2 SYSTEM INFORMATION
3 CLOCK GENERATOR_SLG8SP628 NBSWON#
D D
4 K8G BGA HT I/F 1/4
DNBSWON#
5 K8G BGA DDR2 MEMORY I/F 2/4
S5_ON/S5
6 K8G BGA CTRL & DEBUG 3/4
7 K8G BGA PWR & GND 4/4 RSMRST#
8 RS780-HT LINK/PCIE/MEM I/F 1/3
PCIE_WAKE#
9 RS780-SYSTEM/STRAPS I/F 2/3
10 RS780-POWER/GND 3/3 SUSC
11 SB710-PCIE/PCI/CPU/LPC 1/4
SUSB
12 SB710-ACPI/GPIO/USB 2/4
SUSON
13 SB710-SATA/IDE/HWM/SPI 3/4
14 SB710-PWR/DECOUPLING 4/4 MAINON
RS780 SM BUS
15 SB710-STRAPS & TERMINATOR RS780 I2C (S0) I2C and AUX Function Define
VR_ON
16 SB710-STRAPS & PWRGD DAC_SCL
C
CRT (+5V) C
CPU_CORE DAC_SDA
17 LCD/CAMERA
I2C_CLK
LVDS (+3V)
18 CRT CONN VRM_PWRGD I2C_DATA
DDC_CLK0/AUX0N
19 HDMI CONN HDMI (+5V)
1.2_ON DDC_DATA1/AUX0P
20 AUDIO (CX20582)
DDC_CLK1/AUX1N
NB_CORE not used
21 LAN (RTL8111DL-VB-GR) DDC_DATA1/AUX1P
22 SATA & FAN CONTROL HWPG
23 USB
ECPWROK SB710 SM BUS
24 WLAN
SB_PWRGD_IN SB710 SMBUS SMBUS Function Define
25 WWAN
26 BT, G-SENSOR NB_PWRGD_IN SMBCLK0
DDR / DDR THER / CLOCK GEN
SMBDAT0
27 KB, Touch Pad, Track Point
CPU CLK IN
(+3V)
28 Audio & Function CONN
B CPU RESET SMBCLK1 B
29 KBC IT8502E LAN IC//WI-FI
SMBDAT1
30 Screw Hole / EMI CPU POWER OK (+3V_S5)
31 Discharge SMBCLK2
CPU_LDTSTOP#
SMBDAT2 not used
32 Charger
(+3V_S5)
33 1.8VSUS, +SMDDR_VTERM, +1.5V
34 +1.2V, +1.1V
35 3VPCU, 5VPCU
KBC(EC) SM BUS
36 CPU_CORE, +2.5V KBC SMBUS SMBUS Function Define
(+3VPCU)
37 +1.8V, +1.2V_S5 MBCLK
BATTERY (+3VPCU)
MBDAT
38 +NB_CORE
39 POWER BLOCK DIAGRAM 2ND_MBCLK CPU THER SENSOR(+3V)
2ND_MBDATA EC EEPROM (+3VPCU)
40 HISTORY ( Pre A )
41 HISTORY ( A --> C ) 3ND_MBCLK
A
G-SENSOR(+3VS5) A
3ND_MBDATA
42 HISTORY ( C --> C2 )
43 HISTORY ( C2 --> MP )
Quanta Computer Inc.
PS-Note (AMD)
Size Document Number Rev.
C SYSTEM INFORMATION < MP >
Date: 10/28/2009, 03:15 PM Sheet : 2 of 43
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5 4 3 2 1
CLK_GEN +1.2V +1.2V_CLK_VDDIO
03
+3V +3V_CLK_VDD
L35 1.2V(53mA)
L36 3.3V(250mA) BLM18AG601SN1D_6
HCB1608KF-601T10_6
C294 C327 C299 C296 C447 C313
C298 C338 C330 C317 C303 C295 C297 C324
D 22U/6.3V/X5R_8 2200P/50V/X7R_4 2200P/50V/X7R_4 0.1U/16V/Y5V_4 0.1U/16V/Y5V_4 0.1U/16V/Y5V_4 D
22U/6.3V/X5R_8 0.1U/16V/Y5V_4 2200P/50V/X7R_4 0.1U/16V/Y5V_4 0.1U/16V/Y5V_4 0.1U/16V/Y5V_4 0.1U/16V/Y5V_4 0.1U/16V/Y5V_4
EC-20091028A-3
EC-20091028A-3
Clock chip has internal serial terminations for differencial pairs,
ICS9LPRS480 P/N : ALPRS480000 external resistors are reserved for debug purpose.
SLG8SP628 P/N : AL8SP628000 Place within 0.5" of CLKGEN
Differential clock damping resistors
RTM880N-796-VB-GRT P/N : AL000880001 EC-20090903A-3
EC-20090917A-2 Delete after EA PASS.
U17 R206
RTM880N-796-VB-GRT
+3V_CLK_VDD
*261/F_4
4 50 CLK_CPUP_R
VDDDOT CPUK8_0T CLK_CPUP (6)
16 49 CLK_CPUN_R To CPU Diff 200MHz
VDDSRC CPUK8_0C CLK_CPUN (6)
26
VDDATIG
35
VDDSB_SRC CLK_NBGFXP_R
40 30 CLK_NBGFXP (9)
VDDSATA ATIG0T CLK_NBGFXN_R To NB Diff 100MHz
48 29 CLK_NBGFXN (9)
+3V +3V_CLK_48 VDDCPU ATIG0C
55 28
VDDHTT ATIG1T
3.3V(53mA) 56
VDDREF ATIG1C
27
L40 BLM18AG601SN1D_6 63
VDD48
C336 37 CLK_SBREFP_R
C SB_SRC0T CLK_SBREFP (9) C
11 36 CLK_SBREFN_R To NB Diff 100MHz
+1.2V_CLK_VDDIO VDDSRC_IO0 SB_SRC0C CLK_SBREFN (9)
2.2U/6.3V/X5R_6 17 32 CLK_SBSRCP_R
VDDSRC_IO1 SB_SRC1T CLK_SBSRCP (11)
25 31 CLK_SBSRCN_R To SB Diff 100MHz
VDDATIG_IO SB_SRC1C CLK_SBSRCN (11)
34
VDDSB_SRC_IO
47
VDDCPU_IO NBGPP_CLKP_R
22 T55
SRC0T NBGPP_CLKN_R
21 T57
SRC0C CLK_PCIE_NEW_R
1 20 T56
GND48 SRC1T CLK_PCIE_NEW#_R
7 19 T58
C339 GNDDOT SRC1C CLK_PCIE_WLANP_R
10 15 CLK_PCIE_WLANP (24)
33P/50V/COH_4 GNDSRC0 SRC2T CLK_PCIE_WLANN-R To Mini PCIE Slot (WLAN)
18 14 CLK_PCIE_WLANN (24)
CG_XIN GNDSRC1 SRC2C CLK_PCIE_WANP_R
24 QFN64 13 CLK_PCIE_WANP (25)
GNDATIG SRC3T CLK_PCIE_WANN_R To Mini PCIE Slot (WWAN)
33 12 CLK_PCIE_WANN (25)
GNDSB_SRC SRC3C
2
43 9 CLK_PCIE_LANP_R
GNDSATA SRC4T CLK_PCIE_LANN_R CLK_PCIE_LANP (21)
Y3 46 8 To LAN Controller
GNDCPU SRC4C CLK_PCIE_LANN (21)
C340 14.318MHZ 52
33P/50V/COH_4 GNDHTT
60
1
CG_XOUT GNDREF
42 T67
SRC6T/SATAT
41 T61
CG_XIN SRC6C/SATAC
EC-20090914A-4 61 6 T63
CG_XOUT X1 SRC7T/27M_SS
62
X2 SRC7C/27M_NS
5 T66 EC-20091022A-1
EC-20090727C
2 54 NBHT_REFCLKP_R
(12,16,26) PCLK_SMB SMBCLK HTT0T/66M NBHT_REFCLKN_R HT_REFCLKP (9)
3 53 To NB Diff 100MHz
(12,16,26) PDAT_SMB SMBDAT HTT0C/66M HT_REFCLKN (9)
R204 8.2K_4 CLK_PD# 51 64 CLK_48M_USB_R R374 NBQ100505T-121Y-N_4 To SB 48MHz 20090720A-T103 / Cancel for Card Reader frequency.
+3V_CLK_VDD PD# 48MHz_0 CLK_48M_USB (12)
R369 *22_4 CLK_48M_USB_CR To RTS5159 48MHz
T103
CLKREQ0# 23 59 SEL_HTT66
T54 CLKREQ0# REF0/SEL_HTT66
T65 CLKREQ1# 45 58 SEL_SATA R381 NBQ100505T-121Y-N_4 To SB 14.318MHz
CLKREQ1# REF1/SEL_SATA EXT_SB_OSC (11)
B CLKREQ2# 44 57 SEL_27 To NB 14.318MHz B
T64 CLKREQ2# REF2/SEL_27 EXT_NB_OSC (9)
T60 CLKREQ3# 39 NB CLOCK INPUT TABLE
CLKREQ4# CLKREQ3#
T59 38
CLKREQ4# NB CLOCKS RX780 RS780
TGND0
TGND1
TGND2
TGND3
TGND4
TGND5
TGND6
TGND7
TGND8
TGND9
R377 158/F_4
HT_REFCLKP 100M DIFF 100M DIFF
R376 90.9/F_4
HT_REFCLKN 100M DIFF 100M DIFF
65
66
67
68
69
70
71
72
73
74
+3V_CLK_VDD R4004/R4005 (value may change)
EC-20090910B-1
EC-20090727C REFCLK_P 14M SE (1.8V) 14M SE (1.1V)
NB_OSC
REFCLK_N NC vref
R190 RES CHIP 82.5 1/16W +-1%(0402) --> CS08252FB11
8.2K_4 RX780 1.8V 82.5R/130R RES CHIP 130 1/16W +-1%(0402)L-F --> CS11302FB15 GFX_REFCLK 100M DIFF 100M DIFF(IN/OUT)*
RES CHIP 158 1/16W +-1%(0402) --> CS11582FB00 GPP_REFCLK 100M DIFF NC or 100M DIFF OUTPUT
CLKREQ4# RS780 1.1V 158R/90.9R RES CHIP 90.9 1/16W +-1%(0402) --> CS09092FB15
(21) PCIE_REQ_LAN#
GPPSB_REFCLK 100M DIFF 100M DIFF
+3V_CLK_VDD
+3V_CLK_VDD
CLK_48M_USB_R C331 *10P/50V/C0G_4
R195
8.2K_4 EC-20091022A-1
R380 SEL_SATA C468 10P/50V/C0G_4
*8.2K_4
CLKREQ3# EC-20091028A-3
(25) PCIE_REQ_WWAN#
SEL_SATA 1 66 MHz 3.3V single ended HTT clock SEL_27 C467 10P/50V/C0G_4
SEL_HTT66
SEL_HTT66 0* 100 MHz differential HTT clock
+3V_CLK_VDD
A A
SEL_27 1 100 MHz non-spreading differential SRC clock EMI Cap placement close IC
SEL_SATA
0 * 100 MHz spreading differential SRC clock
R200 R379 R382 R378
8.2K_4 8.2K_4 8.2K_4 *8.2K_4 1 27MHz and 27M SS outputs
SEL_27
0* 100 MHz SRC clock
(24) PCIE_REQ_WLAN#
CLKREQ2# Quanta Computer Inc.
EC-20090727C * default
PS-Note (AMD)
Size Document Number Rev.
Custom CLOCK GEN SLG8SP628 < MP >
Date: 10/29/2009, 04:46 PM Sheet : 3 of 43
5 4 3 2 1
5 4 3 2 1
04
+1.2V_VLDT
D U24A D
AL4 F4
VLDT_B4 VLDT_A4
AL3 F3
VLDT_B3 VLDT_A3
AL2 F2
VLDT_B2 VLDT_A2 C25 4.7U/6.3V/X5R_6
AL1 F1
VLDT_B1 VLDT_A1
(8) HT_CADINP15 Y6 Y9 HT_CADOUTP15 (8)
L0_CADIN_H15 L0_CADOUT_H15
(8) HT_CADINN15 Y5 Y8 HT_CADOUTN15 (8)
L0_CADIN_L15 L0_CADOUT_L15
(8) HT_CADINP14 W7 AB6 HT_CADOUTP14 (8)
L0_CADIN_H14 L0_CADOUT_H14
(8) HT_CADINN14 W6 AB5 HT_CADOUTN14 (8)
L0_CADIN_L14 L0_CADOUT_L14
(8) HT_CADINP13 U6
L0_CADIN_H13 L0_CADOUT_H13
AC7 HT_CADOUTP13 (8) EC-20091005A-4
(8) HT_CADINN13 U5 AC6 HT_CADOUTN13 (8)
L0_CADIN_L13 L0_CADOUT_L13
R7 AE6 HT_CADOUTP12 (8)
(8)
(8)
(8)
HT_CADINP12
HT_CADINN12
HT_CADINP11
R6
M8
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
AE5
AE9
HT_CADOUTN12
HT_CADOUTP11
(8)
(8)
+1.2V +1.2V_VLDT Place close to socket
(8) HT_CADINN11 M7 AE8 HT_CADOUTN11 (8)
L0_CADIN_L11 L0_CADOUT_L11 L2
(8) HT_CADINP10 L6 AH3 HT_CADOUTP10 (8)
L0_CADIN_H10 L0_CADOUT_H10
(8) HT_CADINN10 L5 AH4 HT_CADOUTN10 (8)
L0_CADIN_L10 L0_CADOUT_L10 HCB2012KF-600T30_8
(8) HT_CADINP9 J6 AK3 HT_CADOUTP9 (8)
L0_CADIN_H9 L0_CADOUT_H9
(8) HT_CADINN9 J5 AK4 HT_CADOUTN9 (8)
L0_CADIN_L9 L0_CADOUT_L9 C15 C14 C29 C16 C24 C33
(8) HT_CADINP8 H4 AK1 HT_CADOUTP8 (8)
L0_CADIN_H8 L0_CADOUT_H8
(8) HT_CADINN8 H3 AK2 HT_CADOUTN8 (8)
L0_CADIN_L8 L0_CADOUT_L8
HT LINK
T3 Y1 HT_CADOUTP7 (8) 4.7U/6.3V/X5R_6 4.7U/6.3V/X5R_6 0.22U/6.3V/X5R_4 0.22U/6.3V/X5R_4 180P/50V/NPO_4 180P/50V/NPO_4
C (8) HT_CADINP7 L0_CADIN_H7 L0_CADOUT_H7 C
(8) HT_CADINN7 T4 Y2 HT_CADOUTN7 (8)
L0_CADIN_L7 L0_CADOUT_L7
(8) HT_CADINP6 T2 Y4 HT_CADOUTP6 (8)
L0_CADIN_H6 L0_CADOUT_H6
(8) HT_CADINN6 T1 Y3 HT_CADOUTN6 (8)
L0_CADIN_L6 L0_CADOUT_L6
(8) HT_CADINP5 P3 AB1 HT_CADOUTP5 (8)
L0_CADIN_H5 L0_CADOUT_H5
(8) HT_CADINN5 P4 AB2 HT_CADOUTN5 (8)
L0_CADIN_L5 L0_CADOUT_L5
(8) HT_CADINP4 P2 AB4 HT_CADOUTP4 (8)
L0_CADIN_H4 L0_CADOUT_H4
(8) HT_CADINN4 P1 AB3 HT_CADOUTN4 (8) DESIGN NOTE:
L0_CADIN_L4 L0_CADOUT_L4
(8) HT_CADINP3 M2 AD4 HT_CADOUTP3 (8)
M1
L0_CADIN_H3 L0_CADOUT_H3
AD3 HT_CADOUTN3 (8)
VLDT must be routed as a pour or a trace at least 200 mils wide.
(8) HT_CADINN3 L0_CADIN_L3 L0_CADOUT_L3
(8) HT_CADINP2 K3
L0_CADIN_H2 L0_CADOUT_H2
AF1 HT_CADOUTP2 (8)