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LG2/4 (14"/15.6") MUXLESS and Dis. BLOCK DIAGRAM
VRAM DDR3*4/*8
DDR3 800,1066,1333 MT/s
(512b / 1Gb / 2Gb)
DDR3-SODIMM1 PAGE 19-20
A
PAGE 12
Intel A
Sandy Bridge
DDR3-SODIMM2 DDR3 800,1066,1333 MT/s AMD CRT
CPU 45Watt
PAGE 13 35Watt LVDS
Whistler-Pro 128bit
4 Core Seymour-XT 64bit
( rPGA 989 ) HDMI
29mm X 29mm
PAGE 2-5 FDI PAGE 14-18
BCLK133M 32.768KHz
27MHz
DMI*4 DMI100M
100M PCIE
IGPU CRT
CRTPAGE 23
PAGE 30 PCH 3.5Watt
B LCD CONN for B
Platform IGPU LVDS dual channel
PAGE 30
Controller IGPU HDMI PAGE 22
Hub HDMI CON
PAGE 30 (1920*1200)
USB2.0 48M PAGE 21
PAGE 6-11 (11) (1) (2) (8) (9)
PAGE 29
Fingerprint USB2.0 Port USB2.0 Port BlueTooth Webcam w/ Mic
PAGE 31 PAGE 28 PAGE 28 PAGE 31 PAGE 22
PCI-E 100M
Charger (OZ8681) LPC Azalia (2) (3) (4) (1)
PAGE 33
PAGE 22 32.768KHz half size
LAN USB3.0 Controller Card Reader
3/5VS5 (RT8223M) mini-card
C LPC Atheros AR8151 Realtek RTS5209 Wireless LAN C
PAGE 34 Audio
ITE KBC PAGE 27 PAGE 24 PAGE 29
DDR III (RT8207)
PAGE 25
PAGE 35 ITE 8518/CX 7-in-1
PAGE 31 25MHz flash media
PAGE 32 slot(SD/ SDHC /
VCCSA (RT8241A)
SDXC(UHS 104) /
PAGE 36 RJ45 MS/MMC/ XD/MSP)
PAGE 27 PAGE 24
+1.05V_VTT(RT8240B)
PAGE 32
PAGE 37 PAGE 26 PAGE 26
+1.05V/+1.8V (G5173) Dis-charge IC (G5934)
PAGE 38 PAGE 41
D D
PAGE 25 PAGE 26
CPU Core1 (NCP6132)QC +VGACORE (RT8208)
PAGE 39 PAGE 42
CPU Core2 (NCP5911)QC +VGA POWER
PAGE 40 PAGE 43 Size Document Number Rev
Custom BLOCK DIAGRAM 3A
Date: Wednesday, May 18, 2011 Sheet 1 of 47
1 2 3 4 5 6 7 8
5 4 3 2 1
Sandy Bridge Processor (DMI,PEG,FDI) Sandy Bridge Processor (CLK,MISC,JTAG)
U25A U25B
J22 PEG_COMP PEG_COMP connect to PIN H22&J22 W:4mils/S:15mils/L: 500mils.
PEG_ICOMPI
PEG_ICOMPO J21 PEG_COMP connect to PIN J21 W:12mils/S:15mils/L: 500mils.
[6] DMI_TXN0 B27 DMI_RX#[0] PEG_RCOMPO H22
[6] DMI_TXN1 B25 DMI_RX#[1] PEG_RX#[0..15] [14] BCLK A28 CLK_CPU_BCLKP [8]
A25 C26 A27
MISC
CLOCKS
[6] DMI_TXN2 DMI_RX#[2] [7] H_SNB_IVB# SNB_IVB# BCLK# CLK_CPU_BCLKN [8]
B24 K33 PEG_RX#0
[6] DMI_TXN3 DMI_RX#[3] PEG_RX#[0]
M35 PEG_RX#1
PEG_RX#[1] PEG_RX#2 SKTOCC#
[6] DMI_TXP0 B28 DMI_RX[0] PEG_RX#[2] L34 SNB_IVB# N.A at SNB EDS #27637 0.7v1 TP8203 AN34 SKTOCC#
D B26 J35 PEG_RX#3 A16 CLK_DPLL_SSCLKP_R R8215 1K_4 D
[6] DMI_TXP1 DMI_RX[1] PEG_RX#[3] DPLL_REF_SSCLK
A24 J32 PEG_RX#4 A15 CLK_DPLL_SSCLKN_R R10862 1K_4 +1.05V_VTT
[6] DMI_TXP2 DMI_RX[2] PEG_RX#[4] PEG_RX#5 DPLL_REF_SSCLK#
DMI
[6] DMI_TXP3 B23 DMI_RX[3] PEG_RX#[5] H34
H31 PEG_RX#6
PEG_RX#[6] PEG_RX#7 TP_CATERR#
[6] DMI_RXN0 G21 DMI_TX#[0] PEG_RX#[7] G33 TP8200 AL33 CATERR#
E22 G30 PEG_RX#8
[6] DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PEG_RX#9 Placement close to EC.
[6] DMI_RXN2 DMI_TX#[2] PEG_RX#[9] PEG_RX#10
D21 E34
THERMAL
[6] DMI_RXN3 DMI_TX#[3] PEG_RX#[10]
E32 PEG_RX#11 R8463 43_4 H_PECI AN33 R8 CPU_DRAMRST#
PEG_RX#[11] [32] EC_PECI PECI SM_DRAMRST#
G22 D33 PEG_RX#12
[6] DMI_RXP0 DMI_TX[0] PEG_RX#[12] PEG_RX#13
D22 D31 PROCTHOT# with two VR topology ..75ohm R8219 Change to 25.5 ohm for intel DG.
DDR3
MISC
[6] DMI_RXP1 DMI_TX[1] PEG_RX#[13]
F20 B33 PEG_RX#14
[6] DMI_RXP2 DMI_TX[2] PEG_RX#[14] PEG_RX#15
PROCTHOT# with one VR topology ..56 ohm R8217 56.2/F_4 H_PROCHOT#_R SM_RCOMP_0 R8218 140/F_4
[6] DMI_RXP3 C21 DMI_TX[3] PEG_RX#[15] C32 PEG_RX[0..15] [14] [32,39] H_PROCHOT# AL32 PROCHOT# SM_RCOMP[0] AK1
PCI EXPRESS* - GRAPHICS
A5 SM_RCOMP_1 R8219 25.5/F_4
PEG_RX0 C462 43P/50V_4 SM_RCOMP[1] SM_RCOMP_2 R8220 200/F_4
PEG_RX[0] J33 SM_RCOMP[2] A4
L35 PEG_RX1
PEG_RX[1] PEG_RX2 R8221 *0_4/S PM_THRMTRIP#_R AN32
PEG_RX[2] K34 [9,32] PM_THRMTRIP# THERMTRIP# SM_RCOMP[0] W:20mils/S:20mils/L: 500mils,
A21 H35 PEG_RX3
[6] FDI_TXN0 FDI0_TX#[0] PEG_RX[3] PEG_RX4
SM_RCOMP[1] W:20mils/S:20mils/L: 500mils,
[6] FDI_TXN1 H19 FDI0_TX#[1] PEG_RX[4] H32
E19 G34 PEG_RX5 SM_RCOMP[2] W:15mils/S:20mils/L: 500mils,
[6] FDI_TXN2 FDI0_TX#[2] PEG_RX[5]
F18 G31 PEG_RX6
[6] FDI_TXN3 FDI0_TX#[3] PEG_RX[6]
B21 F33 PEG_RX7 AP29 XDP_PRDY# TP9008
[6] FDI_TXN4
Intel(R) FDI
FDI1_TX#[0] PEG_RX[7] PEG_RX8 PRDY# XDP_PREQ#
[6] FDI_TXN5 C20 FDI1_TX#[1] PEG_RX[8] F30 PREQ# AP27 TP9009 CPU XDP
D18 E35 PEG_RX9
[6] FDI_TXN6 FDI1_TX#[2] PEG_RX[9]
E17 E33 PEG_RX10 AR26 XDP_TCLK TP9010
[6] FDI_TXN7 FDI1_TX#[3] PEG_RX[10] PEG_RX11 TCK XDP_TMS
F32 AR27 TP9011
PWR MANAGEMENT
PEG_RX[11] TMS
JTAG & BPM
D34 PEG_RX12 R8222 *0_4/S PM_SYNC_R AM34 AP30 XDP_TRST#
PEG_RX[12] [6] PM_SYNC PM_SYNC TRST# TP9012
A22 E31 PEG_RX13
[6] FDI_TXP0 FDI0_TX[0] PEG_RX[13]
G19 C33 PEG_RX14 AR28 XDP_TDI_R
[6] FDI_TXP1 FDI0_TX[1] PEG_RX[14] TDI TP9013
E20 B32 PEG_RX15 AP26 XDP_TDO TP9014
C [6] FDI_TXP2 FDI0_TX[2] PEG_RX[15] TDO C
G18 [9] H_PWRGOOD R8225 *0_4/S H_PWRGOOD_R AP33
[6] FDI_TXP3 FDI0_TX[3] UNCOREPW RGOOD
B20 M29 C_PEG_TX#0 R9029 *1K_4
[6] FDI_TXP4 FDI1_TX[0] PEG_TX#[0] +3V
C19 M32 C_PEG_TX#1 R8226 10K_4
[6] FDI_TXP5 FDI1_TX[1] PEG_TX#[1]
D19 M31 C_PEG_TX#2 AL35 XDP_DBRST# XDP_DBRST# [6]
[6] FDI_TXP6 FDI1_TX[2] PEG_TX#[2] DBR#
F17 L32 C_PEG_TX#3 PM_DRAM_PWRGD_R V8
[6] FDI_TXP7 FDI1_TX[3] PEG_TX#[3] C_PEG_TX#4 SM_DRAMPW ROK
PEG_TX#[4] L29
J18 K31 C_PEG_TX#5 AT28
[6] FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5] C_PEG_TX#6 BPM#[0]
J17 K28 +1.05V_VTT R8229 *75_4 AR29
[6] FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] BPM#[1]
J30 C_PEG_TX#7 U8204 AR30
H20
PEG_TX#[7]
J28 C_PEG_TX#8 CPU RESET# 3 4 CPU_PLTRST# R8252 *43_4 CPU_PLTRST#_R AR33
BPM#[2]
AT30
[6] FDI_INT FDI_INT PEG_TX#[8] C_PEG_TX#9 GND OUT RESET# BPM#[3]
PEG_TX#[9] H29 BPM#[4] AP32
J19 G27 C_PEG_TX#10 2 +3VS5 AR31
[6] FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10] [8,14,22,24,27,28,29,32] PLTRST# IN C8236 BPM#[5]
H17 E29 C_PEG_TX#11 R9113 AT31
[6] FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] BPM#[6]
F27 C_PEG_TX#12 1 5 AR32
PEG_TX#[12] C_PEG_TX#13 NC VCC BPM#[7]
PEG_TX#[13] D28
F26 C_PEG_TX#14 *74LVC1G07GW 750/F_4
PEG_TX#[14] C_PEG_TX#15 *0.1U/10V_4 Sandy Bridge_rPGA_Rev0p61
PEG_TX#[15] E25
eDP_COMP A18 rpga989-47989-socket
eDP_COMPIO C_PEG_TX0 R9114 1.5K/F_4 DGG^9000023
A17 eDP_ICOMPO PEG_TX[0] M28
INT_eDP_HPD_Q B16 M33 C_PEG_TX1 IC SOCKET RPGA 989P(P1.0,M/H3.0)
eDP_HPD PEG_TX[1]
PEG_TX[2] M30
L31
C_PEG_TX2
C_PEG_TX3
SM_DRAMPWROK Processor Input. DDR3 DRAM RESET
PEG_TX[3] C_PEG_TX4 +3VS5 +3VS5
C15 eDP_AUX PEG_TX[4] L28
D15 K30 C_PEG_TX5 R8250 1K_4 R8251 *0_4
eDP_AUX# PEG_TX[5] +1.5V_CPU +1.5VSUS
K27 C_PEG_TX6
PEG_TX[6] C_PEG_TX7
eDP
PEG_TX[7] J29
C17 J27 C_PEG_TX8 R9031 1K_4 3 1 CPU_DRAMRST#
eDP_TX[0] PEG_TX[8] [12,13] DDR3_DRAMRST#
F16 H28 C_PEG_TX9 R8560 U8203 C8235
eDP_TX[1] PEG_TX[9] C_PEG_TX10 *10K_4 *0.1U/10V_4
C16 eDP_TX[2] PEG_TX[10] G28 1 NC VCC 5
G15 E28 C_PEG_TX11 R8232 CPU_DRAMRST#_R Q8205
2
B eDP_TX[3] PEG_TX[11] C_PEG_TX12 PM_DRAM_PWRGD_PU 200/F_4 2N7002 B
PEG_TX[12] F28 2 IN
C18 D27 C_PEG_TX13 [8,12,13] DRAMRST_CNTRL_PCH R8254 *0_4/S
eDP_TX#[0] PEG_TX[13] C_PEG_TX14 PM_DRAM_PWRGD_C R8233 130/F_4 PM_DRAM_PWRGD_R R8255
E16 eDP_TX#[1] PEG_TX[14] E26 3 GND OUT 4
D16 D25 C_PEG_TX15 R9030 C8245 4.99K/F_4
eDP_TX#[2] PEG_TX[15] R9051 *74LVC1G07GW 0.047U/10V_4
F15 eDP_TX#[3] *0_4
3
*39_4
Sandy Bridge_rPGA_Rev0p61
rpga989-47989-socket PM_DRAM_PWRGD [6]
DGG^9000023 2 MAIN_ONG [4,41]
IC SOCKET RPGA 989P(P1.0,M/H3.0)
R9115 PM_DRAM_PWRGD_C
eDP_COMP connect to PIN A18 W:4mils/S:15mils/L: 500mils. *0_4/S Q8200 [6,7,8,9,10,12,13,14,17,21,22,23,24,25,26,27,28,29,30,31,32,37,39,41,42] +3V
R9116 *2N7002
eDP_COMP connect to PIN A17 W:12mils/S:15mils/L: 500mils. [6,7,8,9,10,27,29,32,34,37,38,41,43] +3VS5
1
*3K/F_4 [4,10,29] +1.5V_CPU
[4,6,7,8,10,28,32,37,38,39] +1.05V_VTT
Processor pull-up (CPU)
FDI disable PEG x16 disable (UMA only remove) DP & PEG Compensation PROCTHOT# with two VR topology ..100ohm
PROCTHOT# with one VR topology ..62 ohm
(DIS only stuff) [14] PEG_TX[0..15] [14] PEG_TX#[0..15]
+1.05V_VTT R9016 10K_4 INT_eDP_HPD_Q +1.05V_VTT
C_PEG_TX0 C8227 0.1U/10V_4 PEG_TX0 C_PEG_TX#0 C8212 0.1U/10V_4 PEG_TX#0 H_PROCHOT# R8239 62_4
FDI_INT C_PEG_TX1 C8228 0.1U/10V_4 PEG_TX1 C_PEG_TX#1 C8213 0.1U/10V_4 PEG_TX#1 +1.05V_VTT R8243 24.9/F_4 eDP_COMP XDP_TDO R9022 51_4
C_PEG_TX2 C8229 0.1U/10V_4 PEG_TX2 C_PEG_TX#2 C8214 0.1U/10V_4 PEG_TX#2 XDP_TMS R8241 51_4
R8235 0_4 FDI_FSYNC0 C_PEG_TX3 C8230 0.1U/10V_4 PEG_TX3 C_PEG_TX#3 C8215 0.1U/10V_4 PEG_TX#3 XDP_TDI_R R8242 51_4
R8236 0_4 FDI_FSYNC1 C_PEG_TX4 C8231 0.1U/10V_4 PEG_TX4 C_PEG_TX#4 C8216 0.1U/10V_4 PEG_TX#4 eDP_COMPIO and ICOMPO signals should be shorted XDP_PREQ# R8245 *51_4
A R8237 0_4 FDI_LSYNC0 C_PEG_TX5 C8232 0.1U/10V_4 PEG_TX5 C_PEG_TX#5 C8217 0.1U/10V_4 PEG_TX#5 XDP_TCLK R8246 51_4 A
FDI_LSYNC1 C_PEG_TX6 C8233 0.1U/10V_4 PEG_TX6 C_PEG_TX#6 C8218 0.1U/10V_4 PEG_TX#6 near balls and routed with typical impedance <25 mohms XDP_TRST# R8247 51_4
C_PEG_TX7 C8237 0.1U/10V_4 PEG_TX7 C_PEG_TX#7 C8219 0.1U/10V_4 PEG_TX#7
R8240 1K_4 C_PEG_TX8 C8234 0.1U/10V_4 PEG_TX8 C_PEG_TX#8 C8220 0.1U/10V_4 PEG_TX#8 R8244 24.9/F_4 PEG_COMP
+1.05V_VTT
R8234 1K_4 C_PEG_TX9 C8238 0.1U/10V_4 PEG_TX9 C_PEG_TX#9 C8221 0.1U/10V_4 PEG_TX#9
C_PEG_TX10 C8239 0.1U/10V_4 PEG_TX10 C_PEG_TX#10 C8222 0.1U/10V_4 PEG_TX#10
C_PEG_TX11 C8240 0.1U/10V_4 PEG_TX11 C_PEG_TX#11 C8223 0.1U/10V_4 PEG_TX#11 PEG_ICOMPI and RCOMPO signals
FDI_FSYNC can gang all these 4 C_PEG_TX12 C8241 0.1U/10V_4 PEG_TX12 C_PEG_TX#12 C8224 0.1U/10V_4 PEG_TX#12
C_PEG_TX13 C8242 0.1U/10V_4 PEG_TX13 C_PEG_TX#13 C8225 0.1U/10V_4 PEG_TX#13 should be routed within 500 mils typical
signals together and tie them C_PEG_TX14 C8243 0.1U/10V_4 PEG_TX14 C_PEG_TX#14 C8226 0.1U/10V_4 PEG_TX#14 impedance = 43 mohms PEG_ICOMPO
with only one 1K resistor to GND C_PEG_TX15 C8244 0.1U/10V_4 PEG_TX15 C_PEG_TX#15 C8200 0.1U/10V_4 PEG_TX#15
signals should be routed within 500 mils
(DG V0.5 Ch2.2.9). Size Document Number Rev
0.22uF AC coupling Caps for PCIE GEN1/2/3 0.22uF AC coupling Caps for PCIE GEN1/2/3 typical impedance = 14.5 mohms