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Agilent EEsof EDA
PLL's using a Charge Pump, High Divide-by-N
Factors, and Decimation before Plotting
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Application Note AN126E Mar 20, 2001
Phase Locked Loops (PLL) using a Charge Pump,
PLL's with High Divide-by-N Factors, and
Decimation Before Plotting
By Stephen H. Kratzet
Introduction PLL Example 1 -- The Charge Pump
A spreadsheet approach will be shown for designing a The 1st example is taken directly from a National
phase locked loop (PLL) that uses a charge pump. Semiconductor application note (Ref. 1). Figure 1 shows
Although the spreadsheet is specific to SystemView by what the PLL looks like in SystemView. To simulate the
ELANIX, it may be used for other PLL systems using a 5.0 ma current sources in the charge pump, two step
charge pump. In SystemView, PLL's with a high divide- source tokens are used at the input to the charge pump:
by-N factor (greater than ~1000) will result in very long +5000 volts and -5000 volts Inside the charge pump,
plotting times. In these cases, decimation of the sink data there is a resistor in series with each of the 5000 volt
can dramatically speed up the plotting times. inputs. Each of the series resistors is set to 1.0 e6 ohms.
Figure 1. A divide by 4,500 PLL with a charge pump, followed by a low pass RC filter.
AN126E Mar 20, 2001 SystemView by ELANIX Page 1 of 10
Other parameter values can be used for the current partial solution is to use a limit token from the Function
source that have almost no effect on the VCO control library at the output of the RC_Cpump token. Although
waveform. A 50.0 volt source with a 10.0 k resistor and the limit token is not used here, its parameters could be set
a 5.0 volt source with a 1.0 k resistor each worked fine. as follows:
However, there is a difference in each of the Bode plots Input Max (+/- v): 5
for the various voltage/resistor combinations. The -3dB Output Max (+/- v): 5
point for the lowpass cutoff frequency tracks the resistor
value. When 5000 volts and a 1.0 Meg resistor are used, Reference Sideband Spur Filter
the lowpass -3dB point is moved far away from the point Additional filtering, is done by a RC-PLL token
of inflection in the gain plot. (Figure 6) to help in the rejection of the reference
sidebands, or spurs. The circuit in Figure 6 is also
Charge Pump Filter simplified by setting some component values to near zero
The filter in the charge pump token in (Figure 2) is or infinity.
simplified by setting some of the component values to
near zero or infinity. The SystemView charge-pump In SystemView, these two filters (charge-pump and
circuit consists of an external voltage applied to an input spur-filter) are represented by two separate tokens. This
resistor, followed by an R/C filter. means that the two filters are buffered or isolated from
each other, and that the RC components don't interact with
each other as they do in the circuit in National
Semiconductor's app note AN-1001 about the LMX2315.
This is not a problem because the cutoff frequencies in the
two filters are widely separated. AN-1001 indicates that
the pole of the spur filter should be at least 5 times the
loop bandwidth. In this example the point of inflection of
the gain plot of the charge pump is 15.9 kHz, and the -3
dB cutoff point of the spur filter is 73 kHz (Figure 5).
Figure 2. The RC_Cpump parameter window.
(divide by 4,500 Charge pump)
Figure 4. The Bode plot of the charge pump filter.
(divide by 4,500)
Figure 3. The select circuit condition window.
Again, the combination of an external voltage
applied to the input resistor, is the current source for the
SystemView model. To see the Bode plot of this token,
select the "Closed (top switch), Open (bottom switch),
Input 0 (top input)" circuit condition (Figure 3). The
resulting Bode plot in Figure 4 shows a local peak in the
phase plot at 15.9 kHz (the gain plots' point of inflection).
With a real-world part, the voltage excursion inside of
the RC_Cpump would be limited to values between the
two limits of the power supply to the chip. This lack of
voltage limiting in the SystemView model does not seem Figure 5. Bode plot of the sideband spur filter.
to cause any problems because within the PLL, the (divide by 4,500)
relatively slowly changing capacitor voltage is inside the
control loop. If some sort of voltage limiting is desired, a
AN126E Mar 20, 2001 SystemView by ELANIX Page 2 of 10
now provides a logic signal that is not 50% duty cycle for
an odd divide factor. The output changes state only on a
LOW-to-HIGH transition of the input frequency. Either
output may be used in this PLL example.
Application note AN127A describes a dual modulus
divider that may be used in place of the Comm library
divider.
Each particular divider will produce its own unique
initial lock-in waveform when used in a PLL circuit. To
minimize the simulation time, the phase of the reference
frequency may be adjusted to reduce the initial overshoot,
or undershoot of the simulation.
Figure 6. The RC_PLL parameter window. The 98 pF
includes the VCO's 30 pF input cap. (divide by 4,500)
PLL Calculations using a Spreadsheet
National Semiconductor's application note AN1001
(Ref. 1) shows the calculations for the charge pump. A
VCO or FM token
Microsoft ExcelTM spreadsheet was created to perform
The loop reference is 200 kHz. A division ratio of
similar calculations. (There is a small, disagreement
4,500 gives a locked in frequency of 900 MHz
between the Application Information in the data sheet and
(Figure 7). The 900 MHz FM token (or VCO) has been
the spreadsheet, but it is far less than the variation of 5%
set 50 MHz low to 850 MHz. The VCO has a gain of
component values. The difference is apparently due to the
20 MHz/Volt. Therefore, when locked in the control
spreadsheet carrying the full numerical precision through
voltage to the VCO will be 2.5 volts (Figure 1).
all the calculations, verses the application note that starts
each calculation with a rounded-off number.) The
SystemView
spreadsheet is located at the end of this application note.
The SystemView file and spreadsheet are saved as
850e+6 875e+6 900e+6 925e+6 950e+
10 follows:
0
-10
The 1st example with N = 4,500 is saved as:
-20
Power dBm
PLL charge_pump div_by_n ns_an1001 e.svu
-30
PLL charge pump ns_an1001.xls
-40
-50
-60 The magnified view in Figure 8 (using twice as many
850e+6 875e+6 900e+6 925e+6 950e+
samples) shows the PLL settling time as about 150 uSec.
Frequency in Hz (dF = 6e+3 Hz)
This is close to the settling time shown in the National
Figure 7. The 900 MHz frequency out of the Semiconductor app note AN1001, Figure 10. (The
FM token in the 1st example. SystemView plot seems to have a larger overshoot and
(Scale: 849 e6 to 951 e6, 11 dBm to -61 dBm) smaller undershoot preceding the lock-in.)
Comm Library Divide by N Token
In March 1999, the Comm library divide-by-N token
was given a 2nd input that is a control that selects one of
the following modes of operation:
divide-by-N divide-by-N+1
In these examples, the control threshold is set above the
fixed value of the control input (Step source) to cause the
token to always divide-by-N.
In May 1999, the Comm library divide-by-N token
was given an additional output signal. The original token Figure 8. A magnified view of the VCO control voltage.
always had a 50% duty cycle output with either an even
or odd divide number. The additional output connection
AN126E Mar 20, 2001 SystemView by ELANIX Page 3 of 10
The SystemView Voltage Driven Charge-Pump Real Time sink. Without the decimation the plotting time
verses a Current-driven Charge-Pump would take many minutes as the computer software
The SystemView charge-pump circuit (Figure 2) prepares hard disk space for the 524,288 samples. Also,
consists of an external voltage applied to an input resistor, with the 256 decimation the system run time is about 6%
followed by two capacitors and a resistor to ground. faster and the plotting time is very rapid.
Decimation can't always be used. In each system, the
1.0 e6 ohms, 10 e-9 F with 3.3e3 ohms in series, 1.0e-9 F signal at the FM token is about 900 MHz. Since the
system sample rate is 3,145,728,000 samples/sec, even a
The external voltage applied to the input resistor, is decimation by 2 will violate the Nyquist rule for sampled
the current source for the SystemView model. systems. (The system sample rate should be at least twice
the signals rate.)
In National Semiconductor's application note (Page
2, Figure 3) the charge-pump circuit has the same two PLL Example 2
capacitors and a resistor to ground, but there is no input The 2nd PLL example with a divide factor of 35,440
resistor or voltage source. This is because National is shown in Figure 9. National Semiconductor's data
Semiconductor's 2nd order filter is driven by a current sheet for the LMX1511 (Ref. 2) shows the calculations
source, "Do". The two different circuits give almost for the charge pump. A 2nd Microsoft ExcelTM
exactly the same answer. However, the Bode plots for the spreadsheet was created to perform similar calculations.
two circuits will be different because of the extra input (Again, there is a small, disagreement between the
resistor in the SystemView model, (or the missing input Application Information in the data sheet and the
resistor in the current mode model.) spreadsheet.)
Decimating Sink Data The 2nd example with N = 35,440 is saved as:
Notice that the system in Figure 1 has the output of
the filter decimated by 256 before it is applied too the sink PLL charge_pump div_by_n ns_ds1995 e.svu
for viewing. This allows the full plot to appear in the PLL charge pump ns_ds1995.xls
Figure 9. The divide by 35,440 PLL example with a charge pump, followed by a low pass RC filter.
AN126E Mar 20, 2001 SystemView by ELANIX Page 4 of 10
The circuit values for the 2nd PLL example with a The magnified view in Figure 14 (using twice as
divide factor of 35,440 are shown in Figures 10 and 11. many samples) shows the PLL settling time as about 1.0
The Bode plots for the charge pump and the sideband mSec. This is close to the settling time shown in the
filter are shown in Figures 12 and 13. National Semiconductor data sheet, page 18.
Figure 10. The divide by 35,400 charge pump filter. Figure 12. The divide by 35,400 Bode plot.
Figure 11. The divide by 35,400 sideband filter. Figure 13. The divide by 35,400 sideband filter.
Figure 14. A magnified view of the divide by 35,400
VCO control voltage.
AN126E Mar 20, 2001 SystemView by ELANIX Page 5 of 10
Adding Noise to the model
It is not the intent of this application note to cover Noise Sources Used in Figure 13
the topic of PLL phase noise. However, Figure 15 shows Type of Noise Token Number Amplitude
a PLL with noise added to various points in the system. (volts)
The PLL is the same one used in Figure 1, but with eight Reference 13 50.0 e-3
noise sources which are documented in Table 1. Divider 19 50.0 e-3
If token 13 or 19 is raised to 110.0 e-3 v, every once Phase detector 21 and 23 50.0 e-3
in awhile, the loop will jump out of it's locked state, and Loop filter 25 and 27 1.0 e-3
then re-lock. For more information on this model with its FM 15 1.0 e-3
noise sources, please see to Ref. 3.
VCO 17 1.0 e-3
Table 1.
Figure 15. The PLL in Figure 1 with eight noise sources added to the system.
AN126E Mar 20, 2001 SystemView by ELANIX Page 6 of 10
Adding Reference Frequency Leakage to the model
Figure 17 shows a PLL with some reference
frequency leakage. The PLL is the same one used in
Figure 1, but an attenuator reduces the reference
frequency by 30 dB, and then adds the signal to the input
of the second loop filter. This leakage would normally
find its way into the loop through various ways, such as:
1. The power supply for the charge pump.
2. The power supply for the VCO.
3. The printed circuit board layout.
Figure 16. Plus and minus 200 kHz spurs on either side
of the 900 MHz PLL frequency.
Figure 17. The PLL in Figure 1 with some reference frequency leakage added to the system.
AN126E Mar 20, 2001 SystemView by ELANIX Page 7 of 10
References
Ref. 1 An Analysis and Performance Evaluation of a For more information on SystemView simulation
Passive Filter Design Technique for Charge Pump Phase- software please contact:
Locked Loops, National Semiconductor, AN1001,
May 1996, Available on their Web site: ELANIX, Inc.
http://www.national.com/search/corp_search_tools.html 5655 Lindero Canyon Road, Suite 721
Westlake Village CA 91362
Ref. 2 National Semiconductor data sheet for the Tel: (818) 597-1414
LMX1501A/LMX1511 PLLatinumTM IC. Fax: (818) 597-1427
Feb 1995, pages 15, 16, and 17
Visit our web home page (www.elanix.com) to download
Ref. 3 Philip J. Rezin, Microwaves & RF, Mar 2000, an evaluation version of the software that can run this
pages 63 - 72 (specifically, pages 66 and 71). simulation as well as other user entered designs.
AN126E Mar 20, 2001 SystemView by ELANIX Page 8 of 10
PLL charge pump ns_an1001.xls March 10, 1999 by Stephen Kratzet
Calculation of Parts Values for a Charge Pump style PLL
Values Entered from the Keyboard
Kvco 20.00E+6 Hz/Volt VCO gain (FM Mod gain).
Kcp 5.00E-3 Amp Phase-detector/Charge-pump gain.
RFopt 900.00E+6 Hz/Volt VCO frequency when optimized.
Fref 200.00E+3 Hz/Volt Reference frequency.
BWhz 20.00E+3 Hz/Volt Loop bandwidth in Hertz.
PhMar 45.0 degrees Phase margin in degrees.
ATTEN 20.0 dB Attenuation of reference spurs by the additional RC filter.
Lpf_R3 22,000 Ohms RC-PLL filter series resistor (R3)
Calculated Charge Pump Filter and Low Pass Filter Circuit Values
N 4,500 Divide ratio = (RFopt / Fref)
Ctog 1.076E-9 Farads Capacitor only to ground. (Charge pump)
Cwsr 10.50E-9 Farads Capacitor with series resistor. (Charge pump)
Rwsc 3.38E+3 Ohms Resistor with series capacitor. (Charge pump)
Lpf_C3 108.51E-12 Farads RC-PLL filter capacitor to ground (C3). (RC-PLL filter)
Calculated Charge Pump Current Source Parameters
To keep the current source relitively linear, use +500.0 and -500.0 voltage sources (Step Source) at the input
to the charge pump token. Then calculate the current source series resistor as follows:
Rcp 100,000 ohms Charge pump resistor (2 places). (Rcp = 500 / Kcp)
The resistor after the switches (feeding the charge pump filter) is set to zero ohms.
Intermediate Calculations
BWrad 125,664 Radians Loop bandwidth in Radians = (2 pi x BWhz)
T1calc 3.296E-06 Seconds T1 = secPhMar - tanPhMar / BWrad = (1/cosPhMar) - tanPhMar / BWrad
T3calc 2.387E-06 Seconds T3 = sqrt( (10 exp( (ATTEN / 20) - 1) / (2 x PI() x Fref) x 2 )
Calculated loop bandwidth
BWcalcLT 5.6835E-06 BWcalcLT = tanPhMar x (T1calc + T3calc)
BWcalcLB 4.0172E-11 BWcalcLB = ( (T1calc + T3calc) ^ 2 ) + (T1calc x T3calc)
BWcalcRT 4.0172E-11 BWcalcRT = BWcalcLB
BWcalcRB 3.2303E-11 BWcalcRB = BWcalcLT ^ 2
BWcalc 7.0439E+04 Hz BWcalc = (BWcalcLT / BWcalcLB) x [ (sqrt(1 + ( BWcalcRT / BWcalcRB) ) - 1]
T2calc 3.5461E-05 Seconds T2calc = 1 / [ (BWcalc ^ 2) x (T1calc + T3calc) ]
C1 (Ctog -- Cap to ground in charge pump) Calculations
CtogLT 1.0000E+05 CtogLT = Kcp x Kvco
CtogLB 2.2327E+13 CtogLB = ( BWcalc ^ 2 ) x N
CtogRT 7.2393E+00 CtogRT = ( 1 + (BWcalc ^ 2) x (T2calc ^ 2) )
CtogRB 1.0837E+00 CtogRB = ( 1 + (BWcalc ^ 2) x (T1calc ^ 2) ) x ( 1 + (BWcalc ^ 2) x (T3calc ^ 2) )
Ctog 1.08E-9 Farads Ctog = (T1calc / T2calc) x (CtogLT / CtogLB) x sqrt[CtogRT / CtogRB]
C2 (Cwsr -- Cap with series resistor in charge pump) Calculations
Cwsr 10.50E-9 Farads Cwsr = Ctog x ( (T2calc / T1calc) - 1)
R2 (Rwsc -- Resistor with series cap in charge pump) Calculations
Rwsc 3,377.3 Ohms Rwsc = T2calc / Cwsr
C3 (LPF_C3 RC-PLL filter) Calculations
Lpf_C3 108.51E-12 Farads Lpf_C3 = T3calc / Lpf_R3
The equations above are from National Semiconductor's application note AN1001 (May 1996)
AN126E Mar 20, 2001 SystemView by ELANIX Page 9 of 10
PLL charge pump ns_ds1995.xls March 10, 1999 by Stephen Kratzet
Calculation of Parts Values for a Charge Pump style PLL
Values Entered from the Keyboard
Kvco 19.30E+6 Hz/Volt VCO gain (FM Mod gain).
Kcp 5.00E-3 Amp Phase-detector/Charge-pump gain.
RFopt 886.00E+6 Hz/Volt VCO frequency when optimized.
Fref 25.00E+3 Hz/Volt Reference frequency.
BWhz 5.00E+3 Hz/Volt Loop bandwidth in Hertz.
PhMar 43.0 degrees Phase margin in degrees.
ATTEN 10.0 dB Attenuation of reference spurs by the additional RC filter.
Lpf_R3 120,000 Ohms RC-PLL filter series resistor (R3)
Calculated Charge Pump Filter and Low Pass Filter Circuit Values
N 35,440 Divide ratio = (RFopt / Fref)
Ctog 2.163E-9 Farads Capacitor only to ground. (Charge pump)
Cwsr 18.47E-9 Farads Capacitor with series resistor. (Charge pump)
Rwsc 7.15E+3 Ohms Resistor with series capacitor. (Charge pump)
Lpf_C3 78.0E-12 Farads RC-PLL filter capacitor to ground (C3). (RC-PLL filter)
Calculated Charge Pump Current Source Parameters
To keep the current source relitively linear, use +500.0 and -500.0 voltage sources (Step Source) at the input
to the charge pump token. Then calculate the current source series resistor as follows:
Rcp 100,000 ohms Charge pump resistor (2 places). (Rcp = 500 / Kcp)
The resistor after the switches (feeding the charge pump filter) is set to zero ohms.
Intermediate Calculations
BWrad 31,416 Radians Loop bandwidth in Radians = (2 pi x BWhz)
T1calc 1.384E-05 Seconds T1 = secPhMar - tanPhMar / BWrad = (1/cosPhMar) - tanPhMar / BWrad
T3calc 9.361E-06 Seconds T3 = sqrt( (10 exp( (ATTEN / 20) - 1) / (2 x PI() x Fref) x 2 )
Calculated loop bandwidth
BWcalcLT 2.1636E-05 BWcalcLT = tanPhMar x (T1calc + T3calc)
BWcalcLB 6.6789E-10 BWcalcLB = ( (T1calc + T3calc) ^ 2 ) + (T1calc x T3calc)
BWcalcRT 6.6789E-10 BWcalcRT = BWcalcLB
BWcalcRB 4.6812E-10 BWcalcRB = BWcalcLT ^ 2
BWcalc 1.8070E+04 Hz BWcalc = (BWcalcLT / BWcalcLB) x [ (sqrt(1 + ( BWcalcRT / BWcalcRB) ) - 1]
T2calc 1.3200E-04 Seconds T2calc = 1 / [ (BWcalc ^ 2) x (T1calc + T3calc) ]
C1 (Ctog -- Cap to ground in charge pump) Calculations
CtogLT 9.6500E+04 CtogLT = Kcp x Kvco
CtogLB 1.1572E+13 CtogLB = ( BWcalc ^ 2 ) x N
CtogRT 6.6891E+00 CtogRT = ( 1 + (BWcalc ^ 2) x (T2calc ^ 2) )
CtogRB 1.0930E+00 CtogRB = ( 1 + (BWcalc ^ 2) x (T1calc ^ 2) ) x ( 1 + (BWcalc ^ 2) x (T3calc ^ 2) )
Ctog 2.16E-9 Farads Ctog = (T1calc / T2calc) x (CtogLT / CtogLB) x sqrt[CtogRT / CtogRB]
C2 (Cwsr -- Cap with series resistor in charge pump) Calculations
Cwsr 18.47E-9 Farads Cwsr = Ctog x ( (T2calc / T1calc) - 1)
R2 (Rwsc -- Resistor with series cap in charge pump) Calculations
Rwsc 7,147.7 Ohms Rwsc = T2calc / Cwsr
C3 (LPF_C3 RC-PLL filter) Calculations
Lpf_C3 78.01E-12 Farads Lpf_C3 = T3calc / Lpf_R3
The equations above are from National Semiconductor's data sheet for the LMX1501A PLLatinnumTM (Feb 1995)
AN126E Mar 20, 2001 SystemView by ELANIX Page 10 of 10
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