Text preview for : Compal_LA-3041.pdf part of Compal Compal LA-3041 Compal Compal_LA-3041.pdf
Back to : Compal_LA-3041.pdf | Home
5 4 3 2 1
COMPAL CONFIDENTIAL
MODEL NAME : HDL75/76
D D
COMPAL P/N :
PCB NO :
Revision : 0.1
HDL75/76 Schematics Document
C
uFCBGA/uFCPGA Mobile Dothan C
Intel Alviso + ICH6M
2005-07-14
REV : 1B
B B
A A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HDL75 LA3041 0.1
Date: Thursday, July 28, 2005 Sheet 1 of 60
5 4 3 2 1
5 4 3 2 1
Compal confidential
Model : HDL75
FAN Thermal(CPU) Pentium-M
Dothan
+3VS G781
+5VS page 8 page 8 uFCPGA CPU
+VCCP (1.05V)
Clock Generator
+CPU_CORE 478pin page 5,6,7 ICS954226
D D
+3VS page 17
H_A#(3..31) H_D#(0..63)
System Bus
+VCCP 400/533 MHz
TV OUT
page 25 INTEL
Memory BUS DDRII-DIMM X2
+1.5VS Alviso 1.8V 533 MHz BANK 0, 1, 2, 3
CRT CONN +1.8VS +1.5VS
(DDRII)
page 25 CRT Signal
PCI-E 16X 1257BGA
+VGA_CORE ATI M24P +2.5V +0.9VS
Internal LVDS
+3VS +VCCP +1.8V page 14,15
LVDS CONN +2.5VS +3VS
page 24 page 9,10,11,12,13
+1.2VS page 18,19,20,21 +2.5VS
Frame Buffer
64/128 Thermal(VGA)
DMI
C page 22,23 +3VS G781-1 page 26 C
+1.5VS
IDSEL:AD18
100MHz
(PIRQG#,PIRQH#,GNT#1,REQ#1)
+3VALW 33MHz
IDSEL:AD19
(PIRQH#,PIRQG#,GNT#4,REQ#4)
IDSEL:AD20
(PIRQA,B#,GNT#2,REQ#2),SIRQ PCI BUS 48MHz USB[0,2,4,6] USB Ports X4
INTEL
IDSEL:AD16 IDSEL:AD17 +3VS +5VALW page 40
(PIRQE#,GNT#0,REQ#0) (PIRQF#,GNT#3,REQ#3) +3V ICH6-M 24.576MHz AC-LINK
+1.5VS
Minipci CONN X2 609 BGA
VT6301S CardBus Controller RTL8110SBL +1.5V ATA100
WIRELESS ENE CB712
1394 Controller +S1_VCC /8100CL +2.5VS
page 27,28,29,30 MDC
+3VS page 32 +5VS
TV Turner page 34 +3VS
+3VALW page 35 +3VS
page 37,38 +3V
Port DEBUG LPC BUS page 39
+5VS +3VALW
1394 Card PCMCIA
+3VS page 43 33MHz Cable
B CONN RJ45 Parallel ATA AC97 Codec B
page 34 Reader Slot +5VS page 31 ALC250
+VCC_5IN1 +S1_VCC
+S1_VPP
page 36 KB910 +5VAMP
RJ11
page 33
page 33 +3VS page 44
X BUS IDE
page 36
+1.5VS/+VCCP +5VS CD-ROM
+3VALW page 41
page 53 RTC BATT SST39VF040 +5VCD
page 42 page 31
+1.8VS/ page 50 Int.KBD
DC IN page 43
+VGA_CORE AMP & INT. HeadPhone &
page 54 page 48
Power On/Off Speaker MIC CONN
CPU_CORE 2.5V/+1.2VS/ SW & LED +5VAMP page 45 +5VAMP page 45
page 55
+1.25VS page 52
page 43
Touch Pad &
A LID SW A
CHARGER 3V/5V/12V DC/DC Interface +5VS
page 43
page 49 page 51 page 47
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HDL75 LA3041 0.1
Date: Thursday, July 28, 2005 Sheet 2 of 60
5 4 3 2 1
5 4 3 2 1
D D
AC VIN MAINPWON LM358
Adapter Thermal
VS
in Protector
P48
P50
SWITCH
ADPPWR
VL FAN5234
P49
DC/DC
RUN +3VALWP (2.5V) +2.5V 7.106A
B+ MAX1902 P53 SUSP B+ VR_ON
+5VS
DC/DC +12VALWP
(3V/5V/12V)
MB3887 VCC SHDN#
BATT+ Charger +5VALWP +1.25V 1A MAX1532
C C
SHDN# P52 DC/DC
P50 (CPU_CORE)
VS
2.5VP
2.5VREF ALP5331
Vcc DC/DC P55
MAX8743 +1.5VP 5A 3VALW (1.25V)
51_ON# TPO610T SUSP
DC/DC P53 EN
SWITCH
VMB (1.5V/VCCP)
P50 B+ CPU_CORE
(+1.308V 25A)
CHGRTC VS_ON1/VS_ON2
ON1/ON2 P54
G920 +VCCP 6.420A
RTC BATT
Charger P50
Battery A
8 Cell
B B+ B
Battery
CHG/DIS
Connector
A P48
BATT+ SWITCH
BATT
P48
LM393
VS BATT OVP
P49 BATT_OVP
A A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Rail
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HDL75 LA3041 0.1
Date: Thursday, July 28, 2005 Sheet 3 of 60
5 4 3 2 1
5 4 3 2 1
Board ID Table for AD channel
Vcc 3.3V +/- 5%
Voltage Rails Ra
Board ID
100K +/- 5%
Rb V AD_BID min V AD_BID typ V AD_BID max
Power Plane Description S0-S1 S3 S5 0 0 0 V 0 V 0 V
VIN Adapter power supply (19V) N/A N/A N/A
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
D
B+ AC or battery power rail for power circuit. N/A N/A N/A
2 18K +/- 5% 0.436 V 0.503 V 0.538 V D
+CPU_CORE Core voltage for CPU ON OFF OFF
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+PCIE_1.2VS +PCIE_1.2VS power rail for VGA PCIExpress ON OFF OFF
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+0.9VS 0.9VS for DDR2 Termination ON OFF OFF
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+VGA_CORE VGA Core Power ON OFF OFF
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+1.5VS MCH & ICH Core Power ON OFF OFF
7 NC 2.500 V 3.300 V 3.300 V
+1.8VS 1.8V switched power rail ON OFF OFF
+2.5VS 2.5VS switched power rail ON OFF OFF
Board ID PCB Revision
+3VALW 3.3V always on power rail ON ON ON*
0 0.1
+3V 3.3V power rail ON ON OFF
1 0.2
+3VS 3.3V switched power rail ON OFF OFF
2 0.3
+5VALW 5V always on power rail ON ON ON*
3 0.4
+5VS 5V switched power rail ON OFF OFF
4 0.5
+12VALW 12V always on power rail ON ON ON*
5 0.6
C +RTCVCC RTC power ON ON ON
6 1.0 C
* 7 1.B
SKU ID Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Vcc 3.3V +/- 5%
Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
0 0 0 V 0 V 0 V
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
External PCI Devices 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
Device IDSEL# REQ#/GNT# Interrupts 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
VGA PIRQA 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
1394 AD16 0 PIRQE 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
B B
LAN AD17 3 PIRQF 7 NC 2.500 V 3.300 V 3.300 V
C ardBus AD20 2 PIRQA,B
Mini-PCI AD18 1 PIRQG/PIRQH
SKU ID EDL71 SKU
Mini-PCI II for TV Turnner AD19 4 PIRQH/PIRQG * 0 EDL71 10/100 LAN WO/TV TUNER
1 EDL71 GIGA LAN W/TV TURNER
EC SM Bus1 address EC SM Bus2 address 2 EDL71 10/100LAN W/TV TUNER
Device Address Device Address
3 EDL71 GIGA WO/TV TUNER
Smart Battery 0001 011X b G781 1001 100X b
4 EDL71 10/100 LAN WO/TV TUNER
EEPROM(24C16/02) 1010 000X b
5 EDL71 10/100LAN W/TV TUNER
G781-1 1001 101X b
6 EDL71 GIGA WO/TV TUNER
7 EDL71 GIGA LAN W/TV TURNER
ICH6 SM Bus address NOTE1:
Device Address SWDJ@ : SWDJ
TV@ : TV Tunner
Clock Generator NOSWDJ@ : W/O SWDJ
( ICS954206) 1101 001Xb
A
100@ : 10/100M LAN A
DDRII DIMM0 1010 000Xb @XX : Depop component
GIGA@ : 10/100M/1000M LAN
DDRII DIMM1 1010 001Xb
1@XX : Pop for Integrated Graphic
Compal Electronics, Inc.
2@XX : Pop for External Graphic Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HDL75 LA3041 0.1
Date: Thursday, July 28, 2005 Sheet 4 of 60
5 4 3 2 1
5 4 3 2 1
<9> H_A#[3..31] H_D#[0..63] <9>
JP1A
Dothan
H_A#3 P4 A19 H_D#0
H_A#4 A3# D0# H_D#1
U4 A4# D1# A25
H_A#5 V3 A22 H_D#2
H_A#6 A5# D2# H_D#3
R3 A6# D3# B21
H_A#7 V2 A24 H_D#4
H_A#8 A7# D4# H_D#5
W1 A8# D5# B26
H_A#9 T4 A21 H_D#6 +3V
H_A#10 A9# D6# H_D#7 R63
W2 A10# D7# B20
H_A#11 Y4 C20 H_D#8 150_0603_1%
H_A#12 A11# D8# H_D#9 ITP_DBRESET#
Y1 A12# D9# B24 1 2
D H_A#13 U1 D24 H_D#10 D
H_A#14 A13# D10# H_D#11
AA3 A14# D11# E24
H_A#15 Y3 C26 H_D#12 +VCCP
H_A#16 A15# D12# H_D#13 R64
AA2 A16# D13# B23
H_A#17 AF4 E23 H_D#14 54.9_0603_1%@
H_A#18 A17# D14# H_D#15 ITP_TDO
AC4 A18# D15# C25 1 2
H_A#19 AC7 H23 H_D#16 R65
H_A#20 A19# D16# H_D#17 @ 54.9_0603_1%
AC3 A20# D17# G25
H_A#21 AD3 L23 H_D#18 1 2 H_RESET#
H_A#22 A21# D18# H_D#19
AE4 A22# D19# M26
H_A#23 AD2 H24 H_D#20
H_A#24 A23# D20# H_D#21 +VCCP R66
AB4 A24# D21# F25
H_A#25 AC6 ADDR GROUP DATA GROUP G24 H_D#22 39.2_0603_1%
H_A#26 A25# D22# H_D#23 ITP_TMS
AD5 A26# D23# J23 1 2
H_A#27 AE2 M23 H_D#24 R68
H_A#28 A27# D24# H_D#25 150_0603_1%
AD6 A28# D25# J25
H_A#29 AF3 L26 H_D#26 1 2 ITP_TDI
H_A#30 A29# D26# H_D#27 This shall place near CPU
AE1 A30# D27# N24
H_A#31 AF1 M25 H_D#28 R70
<9> H_REQ#[0..4] A31# D28#
H26 H_D#29 680_0402_5%
H_REQ#0 D29# H_D#30 ITP_TRST#
R2 REQ0# D30# N25 1 2
H_REQ#1 P3 K25 H_D#31 R71
H_REQ#2 REQ1# D31# H_D#32 27.4_0603_1%
T2 REQ2# D32# Y26
H_REQ#3 P1 AA24 H_D#33 1 2 ITP_TCK
H_REQ#4 REQ3# D33# H_D#34
T1 REQ4# D34# T25
U23 H_D#35
H_ADSTB#0 D35# H_D#36
<9> H_ADSTB#0 U3 ADSTB0# D36# V23
H_ADSTB#1 AE5 R24 H_D#37
<9> H_ADSTB#1 ADSTB1# D37#
R26 H_D#38
C
D38# H_D#39 C
D39# R23
@ R801 2 0_0402_5%
1 CPU_ITTP A16 AA23 H_D#40
<16> CLK_CPU_ITP ITP_CLK0 D40#
2 1 CPU_ITTP# A15 U26 H_D#41
<16> CLK_CPU_ITP# ITP_CLK1 D41#
@ R802 0_0402_5% V24 H_D#42
CLK_CPU_BCLK D42# H_D#43
<16> CLK_CPU_BCLK B15 BCLK0 D43# U25
CLK_CPU_BCLK# B14 HOST CLK V26 H_D#44
<16> CLK_CPU_BCLK# BCLK1 D44#
Y23 H_D#45
D45# H_D#46
D46# AA26
Y25 H_D#47
H_ADS# D47# H_D#48
<9> H_ADS# N2 ADS# D48# AB25
H_BNR# L1 AC23 H_D#49
<9> H_BNR# BNR# D49#