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5 4 3 2 1
Model Name:945GM-DS2 Revision 2.0
SHEET TITLE SHEET TITLE
01 COVER SHEET 28 REAR AUDIO JACK
D
02 BLOCK DIAGRAM 29 DISCRETE POWER D
03 BOM & PCB MODIFY HISTORY 30 VCORE PWM_ISL6312
04 P4_LGA775_A 31 ATX, OTHERS POWER
05 P4_LGA775_B,D 32 FRONT PANEL
06 P4_LGA775_C 33 TI TSB43AB23 1394
07 P4_LGA775_E,F,G,H 34 REALTEK RTL8111B
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08 945G_HOST
09 945G_DDRII
C C
10 945G_PCI E, DMI
11 945G_VGA
12 945G_GND
13 945G_PWR
14 PCI EXPRESS*16 SLOT Digitally signed by dd
15 DDRII CHANNEL A DN: cn=dd, o=dd,
16 DDRII CHANNEL B ou=dd,
B
17 DDRII TERMINATION
email=dddd@yahoo. B
18 ICH7 PCI, USB, DMI, LAN
19 ICH7 IDE, GPIO, SATA, CTRL
com, c=US
20 ICH7 VCC, GND Date: 2010.01.19
21 CK410M CLOCK. 19:11:14 +07'00'
22 PCI SLOT 1,2,PCIE*1
23 IDE/FLOPPY
24 ITE 8718 GB/KX
25 COM_LPT
A A
26 CI,HWM,KB/MS,BIOS
27 ALC888 Gigabyte Technology
Title
Cover Sheet
Size Document Number Rev
Custom 945GM-DS2 2.0
Date: Wednesday, November 08, 2006 Sheet 1 of 34
5 4 3 2 1
5 4 3 2 1
BLOCK DIAGRAM
INTEL Pentium4
LGA775
D
CLOCK GENERATOR D
VCORE = 1.4V
VCC3
CKVDD = 3.3V
PCI EXPRESS X16
VDDQ = 1.5V (AGP POWER 4X)
CHANNEL A
VCC3 = 3.3V
+12V = 12V DDRII DIMM X 2
3VDUAL = 3.3V
VCC = 5V 945G 1.8VSTR = 1.8V(MEMORY,SUSPEND POWER)
VTT_DDR = 0.9V
MAA0~14
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MAA_CPC1~5
MAB_CPC1~5
MDD0~63 CHANNEL B
-DQSD0~7
DM0~7
DDRII DIMM X 2
1.8VSTR = 1.8V(MEMORY,SUSPEND POWER)
VCORE = 1.75V / SLEEP : 1.3V VTT_DDR = 0.9V
2_5VSTR = 2.5V(MEMORY)
VDDQ = 1.5V (AGP POWER 4X, HUBLINK)
C C
PCI EXPRESS X1
IDE Primary
ICH7
VCC = 5V
USB PORTS 0~7 SERIAL ATA
VCC25 = 2.5V(I/O,MEMORY/I,VLINK/I)
VCC = 5V 3VDUAL = 3.3V(SUSPEND POWER)
5VSB = 5V VCC3 = 3.3V
5VUSB = 5V RTCVDD = 3.3V VCC = 5V
PCI BUS
B FWH/HWMO B
PCI SLOT 1,2
VCC = 5V
+12 = 12V VCC3 = 3V
-12 = -12V
VCC = 5V
VCC3 = 3V
3VDUAL = 3V
LPC BUS
ALC888 LPC I/O ITE8718
+12V = 12V
VCC3 = 3.3V VCC = 5V
VCC = 5V 5VSB = 5V
AVDD = 5V VBAT = 3V
A AUDIO PORTS : FRONT AUDIO FRONT PANEL /CPU FAN I/O PORTS : A
LIN_ OUT LINE_IN MIC VCC = 5V
5VSB = 5V
CD_IN +12 = 12V
PVCC = 5V
COMA COMB LPT PS2 FDD
Gigabyte Technology
Title
BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom 945GM-DS2 2.0
Date: Wednesday, November 08, 2006 Sheet 2 of 34
5 4 3 2 1
5 4 3 2 1
Model Name: 945GM-DS2 Circuit or PCB layout change
for next version
Version: 2.0
DATE Change Item Reason
D D
Component value change history
2006/11/08
Data Change Item Reason
2006/05/29 modify LAN 8056-->RTL8111B
2006/06/28 R1.0 MODIFY(LAN LED)
2006/07/03 R1.0 MODIFY VTT_PWRGD# DELAY TIME
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R1.0 COMP8 CHANGE 30/6/1 FOR CONROE CPU
PCB R2.0:AUDIO(VISTA)+SB_HS+SMD
2006/08/29 FUSE+VCORE(8C CAP)+CHOKE+
VCORE 5PCS E-CAP
2006/09/05 MODIFY AUDIO 1X3-->2X3 JACK.
C 2006/09/14 R2.0 GERBER OUT C
2006/09/15 R2.0 GERBER OUT DS2
2006/09/18 100UF-->6X8
2006/10/11 ALC883-->ALC888 PBOM
2006/10/18 F_ECN REMOVE R56 FOR PCB IMPEDANCE
2006/11/08 CHANGE Q289 LOW THRESOLD MOS
CHANGE U89 2.8V FIX KVM SWITCH BOM:9M945GMD2R-00-20C
B B
A A
Gigabyte Technology
Title
BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom 945GM-DS2 2.0
Date: Wednesday, November 08, 2006 Sheet 3 of 34
5 4 3 2 1
5 4 3 2 1
VCORE
R1 124/6/1 GTLREF1
VTT_OR
R3 C1
BC5 BC6 BC7 BC8 210/6/1 1u/6/Y5V/10V/Z
10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K
D D
R5 124/6/1 GTLREF0
VTT_OR
VCORE R7 C2
210/6/1 1u/6/Y5V/10V/Z
+
+
+
+
EC1 EC2 EC3 EC4
100u/2V/SPCAP/X 100u/2V/SPCAP/X 100u/2V/SPCAP/X 100u/2V/SPCAP/X
SP-CAP-MASK VTT_OR
R8 62/6 -IERR
VCORE R10 62/6 -BR0
VTT_OL
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R12 62/6 -CPURST
VTT_OR
BC1 BC2 BC3 BC4
10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K RN1
C 7 8 C
5 6 TESTHI10
3 4 TESTHI9
1 2 TESTHI8
VTT_OL
HA[3..16] LGA775A 62/8P4R/6
[8] HA[3..16]
HA3 L5 D2 -HADS
A<3>* ADS* -HADS [8]
A<4>* LGA775
HA4 P6 C2 -BNR
BNR* -BNR [8]
HA5 M5 D4 -HIT
A<5>* HIT* -HIT [8]
A<6>* (1/8)
HA6 L4 H4
HA7 RSP* -BPRI
M4 A<7>* BPRI* G8 -BPRI [8]
HA8 R4 B2 -DBSY CR
A<8>* DBSY* -DBSY [8]
HA9 T5 C1 -DRDY CPU RETAINTION/X
A<9>* DRDY* -DRDY [8]
HA10 U6 E4 -HITM
A<10>* HITM* -HITM [8]
HA11 T4 AB2 -IERR
HA12 A<11>* IERR* -HINIT
U5 A<12>* INIT* P3 -HINIT [19]
HA13 U4 C3 -HLOCK
A<13>* LOCK* -HLOCK [8]
HA14 V5 E3 -HTRDY
A<14>* TRDY* -HTRDY [8]
HA15 V4 AD3
HA16 A<15>* BINIT* -DEFER
W5 A<16>* DEFER* G7 -DEFER [8]
N4 RSVD_3
P5 RSVD_4 MCERR* AB3
-HREQ0 K4
[8] -HREQ0 REQ<0>*
-HREQ1 J5 U2
[8] -HREQ1 REQ<1>* AP<0>*
B -HREQ2 M6 U3 B
[8] -HREQ2 -HREQ3 REQ<2>* AP<1>*
[8] -HREQ3 K6 REQ<3>*
-HREQ4 J6 F3 -BR0
[8] -HREQ4 REQ<4>* BR<0>* -BR0 [8]
-HADSTB0 R6 G3 TESTHI8
[8] -HADSTB0 ADSTB<0>* TESTHI_8
HA[17..31] HA17 AB6 G4 TESTHI9
[8] HA[17..31] A<17>* TESTHI_9
HA18 W6 H5 TESTHI10
HA19 A<18>* TESTHI_10
Y6 A<19>*
HA20 Y4
HA21 A<20>*
AA4 A<21>* DP<0>* J16
HA22 AD6 H15
HA23 A<22>* DP<1>*
AA5 A<23>* DP<2>* H16
HA24 AB5 J17
HA25 A<24>* DP<3>*
AC5 A<25>*
HA26 AB4 H1 GTLREF0
HA27 A<26>* GTLREF0 GTLREF1
AF5 A<27>* GTLREF1 H2
HA28 AF4 E24 MCH_GTLREF
A<28>* GTLREF2 MCH_GTLREF [8]
HA29 AG6 H29
HA30 A<29>* GTLREF_SEL
AG4 A<30>*
HA31 AG5 A<31>* -CPURST
AH4 A<32>* RESET* G23 -CPURST [8]
AH5 A<33>*
AJ5 A<34>*
AJ6 B3 -RS0
A<35>* RS<0>* -RS0 [8]
AC4 F5 -RS1
RSVD_1 RS<1>* -RS1 [8]
A AE4 A3 -RS2 A
RSVD_2 RS<2>* -RS2 [8]
-HADSTB1 AD5
[8] -HADSTB1 ADSTB<1>*
CPU-SK/775/D/GF Gigabyte Technology
Title
P4_LGA775-A
Size Document Number Rev
B 945GM-DS2 2.0
Date: Wednesday, November 08, 2006 Sheet 4 of 34
5 4 3 2 1
5 4 3 2 1
HD[0..15] LGA775B HD[32..47] RN2 680/8P4R/6
[8] HD[0..15] HD[32..47] [8]
HD0 B4 G16 HD32 7 8 FSBSEL0
D<0>* D<32>* VTT_GMCH
HD1 C5 D<1>* LGA775 D<33>* E15 HD33 5 6 FSBSEL2
HD2 A4 E16 HD34 3 4 FSBSEL1
D<2>* D<34>*
HD3 C6 D<3>* (2/8) D<35>* G18 HD35 1 2
HD4 A5 G17 HD36
D HD5 D<4>* D<36>* HD37 RN3 62/8P4R/6 D
B6 D<5>* D<37>* F17
HD6 B7 F18 HD38 7 8 -BPM1
D<6>* D<38>* VTT_OR
HD7 A7 E18 HD39 5 6 -BPM0
HD8 D<7>* D<39>* HD40 -BPM5
A10 D<8>* D<40>* E19 3 4
HD9 A11 F20 HD41 1 2 -BPM4
HD10 D<9>* D<41>* HD42 -BPM2
B10 D<10>* D<42>* E21 7 8
HD11 C11 F21 HD43 C7 5 6 -BPM3
HD12 D<11>* D<43>* HD44 0.1u/6/Y5V/25V/Z TDI
D8 D<12>* D<44>* G21 3 4
HD13 B12 E22 HD45 1 2 TMS
HD14 D<13>* D<45>* HD46 RN4 62/8P4R/6
C12 D<14>* D<46>* D22
HD15 D11 G22 HD47
-DBI0 D<15>* D<47>* -DBI2 R20 62/6 TDO
[8] -DBI0 A8 DB1<0>* DBI<2>* D19 -DBI2 [8]
STBN0 C8 G20 STBN2 R593 680/6 VR_RDY
[8] STBN0 DSTBN<0>* DSTBN<2>* STBN2 [8]
HD[16..31] STBP0 B9 G19 STBP2 HD[48..63]
[8] HD[16..31] [8] STBP0 DSTBP<0> DSTBP<2> STBP2 [8] HD[48..63] [8]
HD16 G9 D20 HD48 R22 62/6 -TRST
HD17 D<16>* D<48>* HD49 R23 62/6 TCK
F8 D<17>* D<49>* D17
HD18 F9 A14 HD50
HD19 D<18>* D<50>* HD51
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E9 D<19>* D<51>* C15
HD20 D7 C14 HD52
HD21 D<20>* D<52>* HD53 FSBSEL0 R14 8.2K/4 BSEL0
E10 D<21>* D<53>* B15 [21] FSBSEL0 BSEL0 [11]
HD22 D10 C18 HD54 TO CLK GEN FSBSEL1 R15 8.2K/4 BSEL1 TO NB
D<22>* D<54>* [21] FSBSEL1 BSEL2 BSEL1 [11]
HD23 F11 B16 HD55 FSBSEL2 R16 8.2K/4
D<23>* D<55>* [21] FSBSEL2 BSEL2 [11]
HD24 F12 A17 HD56
HD25 D<24>* D<56>* HD57
C D13 D<25>* D<57>* B18 C
HD26 E13 C21 HD58
HD27 D<26>* D<58>* HD59
G13 D<27>* D<59>* B21
HD28 F14 B19 HD60
HD29 G14
D<28>*
D<29>*
D<60>*
D<61>* A19 HD61 CPU
HD30 F15 A22 HD62
HD31 D<30>* D<62>* HD63
G15 D<31>* D<63>* B22
[8] -DBI1
-DBI1 G11 DB1<1>* DBI<3>* C20 -DBI3
-DBI3 [8] NA FSB FSA
STBN1 G12 A16 STBN3
[8] STBN1 DSTBN<1>* DSTBN<3>* STBN3 [8]
[8] STBP1
STBP1 E12 DSTBP<1> DSTBP<3> C17 STBP3
STBP3 [8] FSBSEL3 FSBSEL1 FSBSEL0 Clock
1 0 1 100MHz X
CPU-SK/775/D/GF 0 0 1 133MHz
0 1 1 166MHz
VTT_GMCH 0 1 0 200MHz
LGA775D
VTT_1 A29 0 0 0 266MHz
TCK AE1 TCK LGA775 VTT_2 B25
TDI AD1 B29
TDI VTT_3
TDO AF1 TDO (4/8) VTT_4 B30
TMS AC1 C29
-TRST TMS VTT_5
B AG1 TRST* VTT_6 A26 B
-BPM0 AJ2 B27
-BPM1 BPM<0>* VTT_7
AJ1 BPM<1>* VTT_8 C28
-BPM2 AD2 A25
-BPM3 BPM<2>* VTT_9
AG2 BPM<3>* VTT_10 A28
-BPM4 AF2 A27
-BPM5 BPM<4>* VTT_11
AG3 BPM<5>* VTT_12 C30
-SYS_RST AC2 A30
[19,32] -SYS_RST DBR* VTT_13
AK3 ITPCLK<0> VTT_14 C25
AJ3 ITPCLK<1> VTT_15 C26
FSBSEL0 G29 C27
FSBSEL1 BSEL<0> VTT_16
H30 BSEL<1> VTT_17 B26
FSBSEL2 G30 D27
BSEL<2> VTT_18
N5 SPARE0 VTT_19 D28
C9 SPARE1 VTT_20 D25
E7 SPARE2 VTT_21 D26
R13 AE6 B28
1K/4/X SPARE4 VTT_22
D16 NC_DSS2 VTT_23 D29
A20 NC_DSS3 VTT_24 D30
E23 AM6 VR_RDY
NC VTT_PWRGD VR_RDY [30]
VTT_OUT_1 AA1 VTT_OR
VTT_OUT_2 J1 VTT_OL
VTT_SEL F27
EXTBGREF F23
A D14 A
SFRANAD
SFRANAC E6
DCLKPH E5
J3
ACLKPH
HFPLL D1 Gigabyte Technology
Title
P4_LGA775-B,D
Size Document Number Rev
CPU-SK/775/D/GF B 945GM-DS2 2.0
Date: Wednesday, November 08, 2006 Sheet 5 of 34
5 4 3 2 1
5 4 3 2 1
Place outside of CPU socket
R28 60.4/6/1 COMP5
VTT_OL
R30 60.4/6/1 COMP4
Note: R31 60.4/6/1 COMP2
R32 60.4/6/1 COMP3
VCCA & VCOREPLL C9 R33 60.4/6/1 COMP0
0.1u/6/Y5V/25V/Z R34 60.4/6/1 COMP1
define doesn't same as
VTT_GMCH old P4 design kit
D L1 10uH/8/155mA/0.5/S VCCA R36 60.4/6/1 COMP6 D
VTT_OR
R37 60.4/6/1 COMP7
R38 30/6/1 COMP8
C10 R35 C12
1u/6/Y5V/10V/Z 0/6/SHT/X 0.1u/6/Y5V/25V/Z FOR CONROE CPU
VSSA R1.0
Trace width doesn't
R39 130/6/1 -PROCHOT
less than 12 Mil VTT_GMCH
C11 R40 62/6 TESTHI2_7
1u/6/Y5V/10V/Z
L2 10uH/8/155mA/0.5/S VCOREPLL C8 R41 62/6 -THRMTRIP
0.1u/6/Y5V/25V/Z
As close as possible to VCC3 R42 62/6 -FERR
R1568
CPU socket 110/6/1 R29 62/6/X TESTHI0
R1916 TESTHI0
VCC3
249/6/1 RN5 62/8P4R/6
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7 8 TESTHI11
VTT_OL
3
R1569 C1883 5 6 TESTHI12
Q1 61.9/6/1 0.1u/6/Y5V/25V/Z 3 4 TESTHI1
D