Text preview for : Acer TravelMate 3010_3020_Quanta_ZH2_Rev1A.pdf part of acer Acer TravelMate 3010 3020 Quanta ZH2 Rev1A acer Acer TravelMate 3010_3020_Quanta_ZH2_Rev1A.pdf
Back to : Acer TravelMate 3010_3020 | Home
5 4 3 2 1
ZH2 Block Diagram PA@ PATA
SA@ SATA
HOST 133MHz/166MHz MP@ MINI PCI
X'TAL MC@ MINI CARD
14.318MHZ
PCI-E 100MHz GS@ G-SENSOR
CPU G9@ 5789
D VGA 96MHz Clock Generator Yonah/Merom Thermal Sensor G7@ 5787 D
CLOCK GEN P5
P2 INTEL Mobile_479 CPU
ICS954310BG USB 48MHz
Page : 3,4
DVI
PCI 33MHz
HOST BUS
Chrontel 7307 DVI
533/667 Page : 31
Docking
REF 14MHz
Page : 2 MHz
SDVO Page : 32
DDR2-SODIMM Channel A
Page : 12
+5VPCU TVOUT
DDR2 533/667 CALISTOGA-GM
5V / 3.3V / 10V +3V_PCU MHz 1466 CRT Switch CRT
Channel B
Page : 34 +3V_S5 DDR2-SODIMM FCBGA RGB SN74CBTLV3257PWR Page : 18
Page : 12 Page : 18
Page : 6 ~ 11
+5V_S5 LVDS LVDS
+3VSUS Page : 17
C
USB3 X'TAL24.576MHZ C
+5VSUS
DMI I/F
BT
IDE - HDD
+3V Page : 20 Page : 25 ATA 66/100 AD19 REQ2# / GNT2# INT C/D# AD25 REQ0# / GNT0# INT E/F/G# 1394
PCI BUS Page: 21
+5V USB0,1,2 TI
SYSTEM ICH7-M MINI PCI
+10V SATA - HDD SATA 652 BGA PCMCIA+1394 PCMCIA
ext Azalia
Page : 20
USB*3 Page : 25 +6 IN 1
Page: 22
USB7 PCI7412
+1.8VSUS
CCD USB 2.0 PCI-E Page :20 OSC Page :21~23
Page : 13~16 48MHZ 6 IN 1
+1.8V
1.8V / 0.9V Page : 17
X'TAL Page: 23
/ 2.5V +0.9VSUS 32.768KHZ
Page : 35 +0.9V LPC
+2.5V
X'TAL X'TAL AUDIO CODEC
32.768K 32.768K
USB4
MDC 1.5
B PCI-E CARD ALC883 AMP B
/ WLAN Page : 26 Page : 26
1.5V / 1.05V
Page : 36 NS NS MIC ECHO LINEIN HP INT
+1.5V G-SENSOR NEW CARD USB5 CANCELLATION OUT SPK
KXP84-0200 KBC(97551) TPM 1.2 SIO (87383) VP1020-G
+1.05V
Page : 29 Page : 27 Page : 26
Page : 25
X'TAL
25M
AUDIO/B
VCC_CORE BROADCOM
CPU CORE FIR
Touchpad Keyboard Page : 27 10/100/1G LAN LAN Switch
Page : 33 MAX4892 RJ45
Page : 30 Page : 30 COM LPT 5789M Page : 19
Page : 19
BATTERY
CHARGER PS2 Docking
A Page : 37 A
Page : 32 DOCKING AUDIO
PCI DEVICE IDSEL# REQ# / GNT# Interrupts
PROJECT : ZH2
PCI7412 AD25 REQ0# / GNT0# INT E/F/G# Quanta Computer Inc.
MINI PCI AD19 REQ2# / GNT2# INT C/D# Size Document Number Rev
BLOCK DIAGRAM 1A
Date: Monday, January 02, 2006 Sheet 1 of 38
5 4 3 2 1
A B C D E
FSC FSB FSA CPU SRC PCI
1 0 1 100 100 33
0 0 1 133 100 33 Default
0 1 1 166 100 33
0 1 0 200 100 33
0 0 0 266 100 33
1 0 0 333 100 33 VDD_A
4 Close to IC <500mils 4
1 1 0 400 100 33
1 1 1 200 100 33 C505 27P-50V_4 CG_XIN
Place these termination to close CK410M.
45
46
2
U37
L49 25 mils Y6 58 60 14M_REF R425 33_4
VDDA
GNDA
X1 REF0 14M_ICH 15
BK2125HS121-T_8 14.318MHZ RP34
+3V VDD_SRC_CPU C506 27P-50V_4 CG_XOUT 57 52 RHCLK_CPU 1 2 33_4P2R_S
X2 CPUCLKT0 CLK_CPU_BCLK 3
RHCLK_CPU# C498
1
CPUCLKC0 51 3 4 CLK_CPU_BCLK# 3
120 ohms@100Mhz C216 C199 C490 C481 C488 +3V R222 *10K_4 CK-410M RP29 *10P-50V_4
.1U-10V_4 10U-10V_8 15,33 VR_PWRGD_CK410# 10 49 RHCLK_MCH 1 2 33_4P2R_S
Vtt_PwrGd#/PD CPUCLKT1 CLK_MCH_BCLK 6
.1U-10V_4 .1U-10V_4 .1U-10V_4 15 PM_STPCPU# PM_STPCPU# 62 48 RHCLK_MCH# 3 4
CPU_STOP# CPUCLKC1 CLK_MCH_BCLK# 6
15 PM_STPPCI# PM_STPPCI# 63 RP24
R414 2.2/F_6 VDD_A PCI/PCIE_STOP# CLK_PCIE_MINI1_
CPUCLKT2/PCIET8 44 1 2 MC@33_4P2R_S CLK_PCIE_MINI1 20
CGCLK_SMB 54 43 CLK_PCIE_MINI1_# 3 4
12 CGCLK_SMB SCLK CPUCLKC2/PCIEC8 CLK_PCIE_MINI1# 20
C484 C487 CGDAT_SMB 55 RP19
12 CGDAT_SMB SDATA R_CLK_PCIE_EZ2
.1U-10V_4 10U-10V_8 R420 33_4 41 1 2 33_4P2R_S
15 CLKUSB_48 REQ1#/PCIET7 R_CLK_PCIE_EZ2# CLK_PCIE_EZ2 32
CLK_BSEL0 R421 4.7K_4 12 40 3 4
FSA/USB_48MHz REQ2#/PCIEC7 CLK_PCIE_EZ2# 32
CLK_BSEL1 16 RP15
CLK_BSEL2 R428 4.7K_4 FSB/TEST_MODE RSRC_MCH
61 REF1/FSLC/TEST_SEL PCIET6 39 1 2 33_4P2R_S CLK_PCIE_3GPLL 8
R427 33_4 38 RSRC_MCH# 3 4
28 SIO_14M PCIEC6 CLK_PCIE_3GPLL# 8
VDD_REF 56 RP13
VDD_SRC_CPU VDD_REF R_CLK_PCIE_EZ1
50 VDDCPU PCIET5 36 1 2 33_4P2R_S CLK_PCIE_EZ1 32
C240 35 R_CLK_PCIE_EZ1# 3 4
PCIEC5 CLK_PCIE_EZ1# 32
*10P-50V_4 VDD_PCI 1 VDD_PCI_1
7 VDD_PCI_2 PCIET4 30
25 mils PCIEC4 31
VDD_SRC_CPU 21 RP20
L51 VDD_PCI VDD_PCIE RSRC_SATA
3
+3V 28 VDDPCIE SATA_CKT 26 3 4 SA@33_4P2R_S CLK_PCIE_SATA 13
3
BK2125HS121-T_8 42 27 RSRC_SATA# 1 2
VDD_PCIE SATA_CKC CLK_PCIE_SATA# 13
C512 C513 C514 RP21
.1U-10V_4 .1U-10V_4 10U-10V_8 VDD_48 11 24 RSRC_ICH 3 4 33_4P2R_S
VDD_48 PCIET3 CLK_PCIE_ICH 14
25 RSRC_ICH# 1 2
PCIEC3 CLK_PCIE_ICH# 14
CLKGN_REQ3_PCIE 32 RP25
R433 2.2/F_6 VDD_48 CLKGN_REQ4_PCIE REQ3(PCIE) R_CLK_PCIE_LAN
33 REQ4(PCIE) PCIET2 22 3 4 33_4P2R_S CLK_PCIE_LAN 19
23 R_CLK_PCIE_LAN# 1 2
Iref=5mA, PCIEC2 CLK_PCIE_LAN# 19
C231 C508 R200 475/F_6 IREF 47
.1U-10V_4 10U-10V_8 IREF
Ioh=4*Iref
PCIET1 19
PCIEC1 20
RP31 RP30
DREFCLK 1 2 R_DOT96 14 17 R_DREFSSCLK 3 4 33_4P2R_S
8 DREFCLK DOT96MHz 27Mfix/LCD_SSCGT/PCIE0T DREFSSCLK 8
R424 1_6 VDD_REF DREFCLK# 3 4 R_DOT96# 15 18 R_DREFSSCLK# 1 2
8 DREFCLK# DOT96MHz# 27SS/LCD_SSCGC/PCIE0C DREFSSCLK# 8
RP33
C494 C500 33_4P2R_S 5 R_PCLK_SIO R429 33_4 CLK_CPU_BCLK 1 249.9_4P2R_S
selPCIEX0_LCD#/PCI5 PCI_CLK_SIO 28
.1U-10V_4 10U-10V_8 T140 34 4 R_PCLK_7412 R431 33_4 CLK_CPU_BCLK# 3 4
GND_PCI_1
GND_PCI_2
PWRSAVE# PCI4 PCI_CLK_7412 21
GND_SRC
3 R_PCLK_TPM R432 *33_4 RP28
PCI3 PCLK_TPM 30
GND_48
INTERNAL PULL HIGH 64 PCLK_MINI_LPC R430 33_4 CLK_MCH_BCLK 1 249.9_4P2R_S
del R408 PCICLK2/REQ_SEL PCLK_MINI 20
9 R_PCLK_ICH R423 33_4 CLK_MCH_BCLK# 3 4
GND
GND
GND
PCIF1/selLCD_27# PCLK_ICH 14
REQ3 Latched Select 8 R_PCLK_591 R426 33_4 RP23
PCIF0/ITP_EN PCLK_591 29
CLK_PCIE_MINI1 1 [email protected]_4P2R_S
"0" : CLK Enable ICS954310BGLF CLK_PCIE_MINI1# 3 4
53
13
59
29
37
"1" : CLK Disable Control : PCIE 2,4 C496 C507 C501 RP6
2
6
+3V R242 *10K_4 CLK_PCIE_LAN 3 449.9_4P2R_S
+3V
ITP/SRC7 SELECT *10P-50V_4 *10P-50V_4 *10P-50V_4 CLK_PCIE_LAN# 1 2
CLKGN_REQ3_PCIE R408 10K_4 R221 10K_4 C499 C502 C503 RP14
0: SRC7 1: ITP CLK_PCIE_3GPLL 49.9_4P2R_S
1 2
CLKGN_REQ4_PCIE R407 10K_4 R230 10K_4 CLK_PCIE_3GPLL# 3 4
2 32 EZ_CLKREQ# 2
*10P-50V_4 *10P-50V_4 *10P-50V_4 RP5
BSEL strappings need to be set for 533MHz Moby Dick (Intel?915GM - Calistoga Interposer) CLK_PCIE_SATA 3 [email protected]_4P2R_S
REQ4 Latched Select (if Calistoga is designed for 667MHz board). CLK_PCIE_SATA# 1 2
"0" : CLK Enable SELLCD_27# Select. (Pin 17,18)
"0" : 27MHzSS/27MHzSS# pair
"1" : CLK Disable +1.05V R223 *1K_4 "1" : LCD CLK pair
Default RP22
Control : PCIE R_PCLK_SIO R238 10K_4 CLK_PCIE_ICH 49.9_4P2R_S
3 4
3,5,7 3 CPU_BSEL0
R216 0_4 CLK_BSEL0 R231 1K_4 MCH_BSEL0 8 CLK_PCIE_ICH# 1 2
R210 *1K_4 Latched Select. (Pin 17,18)
"0" : LCD CLK
"1" : PCIEX CLK Default RP7
DREFSSCLK 3 449.9_4P2R_S
DREFSSCLK# 1 2
RP32
DREFCLK 3 449.9_4P2R_S
+3V +1.05V R207 *1K_4 DREFCLK# 1 2
RP18
CLK_PCIE_EZ2 1 249.9_4P2R_S
R203 0_4 CLK_BSEL1 R199 1K_4 MCH_BSEL1 8 CLK_PCIE_EZ2# 3 4
3 CPU_BSEL1
RP12
R201 *0_4 CLK_PCIE_EZ1 1 249.9_4P2R_S
Q20 R409 R410 CLK_PCIE_EZ1# 3 4
2
RHU002N06 10K_4 10K_4
3 1 CGDAT_SMB
15,19,20,32 PDAT_SMB
1 1
+3V
Q21 modify C: del R375,R384 R237 *1K_4
+1.05V PROJECT : ZH2
2
RHU002N06
3 1 CGCLK_SMB R243 0_4 CLK_BSEL2 R254 1K_4
15,19,20,32 PCLK_SMB 3 CPU_BSEL2 MCH_BSEL2 8 Quanta Computer Inc.
R248 *0_4
Size Document Number Rev
CLOCK GENERATOR 1A
Date: Monday, January 02, 2006 Sheet 2 of 38
A B C D E
5 4 3 2 1
T101
U42A
6 H_A#[31:3] +1.05V
H_A#3 J4 H1
A[3]# ADS# H_ADS# 6
H_A#4 L4 E2
A[4]# BNR# H_BNR# 6
H_A#5 M3 G5 +1.05V +1.05V 2,4,6,9,10,13,16,34,36
A[5]# BPRI# H_BPRI# 6
H_A#6 K5
H_A#7 M1 A[6]#
A[7]# DEFER# H5 H_DEFER# 6
ADDR GROUP 0
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# 6
H_A#9 J1 E1 R268 Near to MCH <500mils
A[9]# DBSY# H_DBSY# 6
H_A#10 N3