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SYSTEMS LOGIC/PERIPHERAL

WD16C451, WDl6C551

Enhanced Asynchronous

Communications Element (ACE)

with Parallel Port

9'}. WESTERN DIGITAL
WD16C4511WD16C551

TABLE OF CONTENTS
Section Title Page

1.0 INTRODUCTION 1-1
1.1 Description 1-1
1.2 Features 1-1

2.0 SIGNAL DESCRIPTIONS 1-4

3.0 SERIAL CHANNEL REGISTERS 1-10
3.1 Serial Port Register Addressing 1-10

4.0 ACE OPERATIONAL DESCRIPTION 1-11
4.1 Master Reset 1-11
4.2 ACE Accessible Registers 1-11
4.3 Line Control Register 1-14
4.4 ACE Programmable Baud Rate Generator 1-14
4.5 Line Status Register . . . . 1-17
4.6 Interrupt Identification Register 1-18
4.7 Interrupt Enable Register 1-20
4.8 Scratch Pad Register 1-20
4.9 FIFO Control Register . 1-20

5.0 MODEM CONTROL REGISTER 1-21

6.0 MODEM STATUS REGISTER 1-22
6.1 FIFO Interrupt Mode Operation Notes 1-22
6.2 FIFO Pointer Notes . . . . . . . 1-22
6.3 FIFO Polling Mode Operation Notes 1-23

7.0 PARALLEL PORT DESCRIPTION 1-24

8.0 TYPICALAPPLICATIONS ... 1-26

9.0 CRYSTAL MANUFACTURES (Partial List) 1-28

APPENDICES
Section Title Page

A.O DC OPERATING CHARACTERISTICS 1-30

B.O AC OPERATING CHARACTERISTICS AND TIMING DIAGRAMS 1-33

C.O PACKAGE DIAGRAM 1-45

11/15/90 1-i
WD16C4511WD16C551

LIST OF ILLUSTRATIONS
Figure Title Page
1-1 68-Pin QUAD 1-1
1-2 WD16C451IWD16C55A 810ck Diagram 1-3
2-1 WD16C451IWD16C551 68-Pin QUAD Assembly Pin Designations 1-4
5-1 Interrupt Signal Logic . . . . . . . . . . . . . . 1-21
8-1 Typical Interface for a High-Capacity Data Bus . . . . 1-26
8-2 Typical 16-Bit Microprocessor/RS-232 Terminal Interface
Using the WD16C551 . . . . . 1-27
9-1 External Clock Input 1-28
9-2 Typical Crystal Oscillator Networks 1-29
8-1 Receiver Timing 1-34
8-2 Transmitter Timing 1-35
8-3 MODEM Control Timing 1-36
8-4 Read Cycle Timing . . 1-37
8-5 Write Cycle Timing . . 1-37
8-6 RCVR FIFO Signaling Timing for First Byte 1-39
8-7 RCVR FIFO Signaling Timing after First Byte (RBR already set) 1-39
8-8 Receiver DMA Mode 0 Timing (FCRO = 0 or FCRO = 1 and
FCR3 = 0) ................. . 1-40
8-9 Receiver DMA Mode 1 Timing (FCRO = 1 and FCR3 = 1) 1-40
B-10 Transmitter DMA Mode 0 Timing (FCRO = 0 or FCRO =1
and FCR3 =0) . . . . . . . . . . . . . . . 1-41
B-11 Transmitter DMA Mode 1 (FCRO = 1 and FCR3 = 1) 1-41
B-12 Parallel Port Timing . . . . . . . . . . . . . 1-42
B-13 WD16C451/WD16C451A Parallel Port Interrupt Timing 1-43
8-14 WD16C551/WD16C451B Parallel Port InterruptTiming 1-43
C-1 68-Pin QUAD Plastic Package 1-45

Hi 11/15/90
VV"16~451/VV"16~551

LIST OF TABLES
Table Title Page
2-1 Signal Descriptions 1-5
3-1 Register Addressing 1-1
4-1 Reset Control of Registers and Pinout Signals 1-11
4-2 Accessible WD16C451/WD16C551 Register 1-12
4-3 Baud Rates Using 1.8432 MHz Clock 1-15
4-4 Baud Rates Using 3.072 MHz Clock 1-15
4-5 Baud Rates Using 8.0 MHz Clock 1-16
4-6 Interrupt Control Functions 1-19
7-1 Parallel Port Register Addresses 1-24
7-2 Accessible Parallel Port Registers 1-24
7-3 Parallel Port Operation Modes 1-25
7-4 Parallel Port Reset Control of Registers and Signals 1-25
A-1 DC Operating Characteristics 1-31
A-2 Capacitance 1-32
8-1 WD16C451IWD16C551 Timing Diagrams 1-33
B-2 Receiver Timing 1-34
B-3 Transmitter Timing 1-35
B-4 MODEM Control Timing 1-36
B-5 ReadIWrite Cycle Timing 1-38
8-6 Parallel Port Timing 1-44

11/15/90 1-iii
INTRODUCTION WD 16C4511WD16C551

1.0 INTRODUCTION
1.1 DESCRIPTION 1.2 FEATURES
The low-power CMOS WD16C451 IWD16C551 is a Fully programmable serial interface charac-
single-device solution for serving one serial I/O port teristics including:
and one bidirectional parallel port on the IBM PC,
PC XT, PC AT, PS/2, and compatible systems. The - 5-, 6-, 7-, or 8-bit characters
WD16C451IWD16C551 is an enhanced ACE with
a bidirectional parallel port. The ACE performs - Even, odd, or no parity bit generation/detection
parallel-to-serial conversion on output and serial-
- 1, 1-1/2, or 2 stop-bit generation
to-parallel conversion on input. It is programmable,
independent, and has a maximum recommended - DC to 512 Kbaud rate generation
data rate of 512K baud.
Tri-state TTL drive capabilities for bidirectional
TheWD16C451 family (WD16C451, WD16C451A, data bus and control bus
WD16C451 B) is a WD16C450 ACE plus a bidirec-
tional parallel data port. Loopback controls for communications link
fault isolation
The WD16C451 and WD16C451A parallel port
supports a Centronics-compatible printer interface. Line break generation and detection
The parallel port, together with the serial port,
provides IBM PC XT, PC AT and compatibles with False start-bit detection
a single-device solution for serving both ports. The
WD16C451 A is further enhanced by its crystal input
capability.

The WD16C451 B, also enhanced by its crystal
input capability, supports a PS/2-compatible printer
port interface. The parallel port, together with the
serial port, provides IBM PS/2 and compatibles with NC
NC
NC
INT2IM2"
a single-device solution for serving both ports. NC SLiN
vss iNti'
DBO AFD
The WD16C551 is a WD16C550 Enhanced ACE DBl 5Tii
DB2 vss
plus a compatible PS/2 bidirectional parallel port. DB3 PDO
After power-up and hardware reset, the ACE is DB4 POl
DBS PD2
functionally compatible with WD16C450 (Character DBS PD3
Mode). The ACE in the WD16C551 has been en- DB7 PD4
TxiiiiYo' PDS
hanced with 16-byte FIFO buffers on both the v"" PDS
receive and transmit lines, allowing an additional RTsO PD7
iiTAo INTO
mode of operation called FIFO Mode. The FIFO SOUTO BOO

Mode, only available in WD16C551, can be ac-
tivated through software, relieving CPU of interrupt
overhead. Buffering of data also allows greater
latency time in interrupt servicing, which is vital in
multitasking environments. The WD16C551 also