Text preview for : Schematic Diagram.pdf part of Samsung Schematic Diagram Samsung Plasma PS42 C 77 HD chassis F33B Schematic Diagram.pdf
Back to : Schematic Diagram.pdf | Home
Schematic Diagram
7. Schematic Diagram
7-1 Circuit Description
Logic Board Y Main Board X Main Board
Display Row PDP Panel
DRAM Data Driver 42" - 1024x768 Pixels
Input 1024x768x3 Cells (R,G,B) X-Pulse
Data 50" - 1365x768 Pixels
Data Display Generator
Controller Driver 1365x768x3 Cells (R,G,B)
Processor Timing Y-Pulse
Timing
Controller Generator
Scan
Timing
Address Buffer
SMPS Board
LVDS
Main SMPS
Main Board
LVDS Image Audio
Deinterlacer
Trans Enhancer Processor
Image CPU Video Speaker
Decoder Decoder Out
AC Power
Scaler
Tuner Source
TMDS A/D Video
Converter S/W Micom
Recever
SMPS Board
The SMPS used for the PDP has been designed to be efficient, compact and lightweight. For VS and VA outputs, a LLC converter
has been used. For the other outputs, a Flyback converter has been used.
LOGIC Board
The logic circuit consists of a Logic Main Board and an Address Buffer Board. The Logic Main Board decodes the video signal
encoded by the Video Board, outputs the ADDRESS data signal for each pattern and generates X and Y drive signals. The
Address Buffer Board buffers and transfers the ADDRESS data output signal using TCP IC.
- LVDS with built-in video signal processing (W/L, error diffusion, APC, FCR, etc.) applied and 1 ASIC chip.
- Outputs the address Drive IC control and data signals to the Buffer Board.
- Outputs the control signal for the X and Y Drive Boards.
- Monitors major drive voltages (Micom Circuit Block); detects if a surge voltage has been applied and protects the Drive Circuit.
- Temperature Adaptive Operating Mode (Low Temperature/Room Temperature/High Temperature); Discharge optimization for
each temperature level.
X-MAIN Board
Connects to the X terminal block, 1) provides maintaining voltage waveform (including ERC), and 2) maintains the Ve bias in the
Scan section.
Y-MAIN Board
Connects to the Y terminal block, 1) provides maintaining voltage waveform (including ERC), 2) provides Y Rising, Falling Ramp
waveforms, and 3) maintains the Vscan bias.
Address Buffer Board
It delivers the data signal and control signal to the TCP.
Samsung Electronics 7-1
MEMO
7-2 Samsung Electronics
Schematic Diagram
7-2 Schematic Diagram
7-2-1 Power
This Document can not be used without Samsung's authorization.
Power B13V B5V B12VS
(LCD : B12VS) B9V B5V_VCCT B9V
(PDP : B18VS) IC1101 IC1105
L1101
BA178M09FP MC33269DTRK-5.0
220uH
1 3 3 I O 2
IN OUT
1
1 1 ADJ
R1101 L1103
GND C1137 C1136
330ohm C1138 680uH
1
C1106 C1101
2 C1128 10nF 22uF C1139 47nF
100nF 10nF
C1131 C1123 100nF 16V 220pF
B33V
100uF C1127
16V 100uF C1104
100uF D1101
C1120 C1121 C1122 16V 16V
R1103
MMBD4148SE
1uF
100nF 10nF 100nF C
B 100Kohm 50V
PGND 2
E
C1105 3 R1104
2.2nF Q1104 22Kohm BZX84C33
C1107 1
KSC1623-Y D1105
4.7nF
24 PGND
23 C1173 C1174
22 10nF 10nF
21
PGND
1
20
19
18 IC1114_CPT A5V 1.2V Power suply
C1117
G78D12AT45U A1.2V_VDDC
1
17 100uF
16 16V 1 3
IN OUT L1102
15
C1118 C1116 22uH
CIB31P600NE
14 GND
100nF 10nF C1152_CPT
1
BD1120
13
22uF 2
CIB31P600NE
PGND
BD102_LCD
12 BD1109
16V R1112
11 150ohm ACB2012L-015-T
10 IC1113
AP1530SA R1113
1 1
9
C1153_CPT R1111 1.2Kohm
8 1 FB 8
100nF 100Kohm
7 D1107 A5V 2 EN
VS S
7
VSS
1
6 S1G 3 OCSET 6
5 PGND 4 OUTPUT
5 C1165
VCC
OUTPUT 1mF
1 1 1
4
5.6Kohm 10V
3
2 A5V R1114
5.6Kohm
5.1Kohm
MBRS340T3
1
R1125
R1115
C1167
C1132 1mF
C1129 C1130
D1103
SMW200-24C 10V
1uF 100nF 10nF
CN1101
CIB31P600NE
BD1130
C1142_DE
C1168
PANEL_VCC B5V_VCCA C1164
10V
1uF
100nF 10nF
PGND
SOUND_AMP IC1140
FDS9933A
C1170
SOUND_AMP 1 8 100nF
R108_LCD 2 7
47Kohm C169_LCD 3 6
1uF 4 5
25V
R1140 C1192
47Kohm 1uF
R110_LCD 10V
WATCH_DOG B3.3VD
10Kohm
R111_LCD L1104
47Kohm R1142 R1141_DE 22uH
Stand by Power 10Kohm 47Kohm
R150_OP BD1101 R1119
2SC2412K-Q CIB31P600NE 10Kohm
0ohm SW_PVCC
C 101_LCD
Q C1155
B SW_PVCC 1/10W R1121
Q1080 10nF IC1102
E R151_PDP 5.6Kohm
R113_LCD C
B 0ohm SW_5V