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ZZZ2 ZZZ1 ZZZ3 ZZZ4 ZZZ5 ZZZ6 ZZZ7 ZZZ8




PCB LA-6951P LS-6951P LS-6953P LS-6955P LS-6956P LS-6957P LS-6958P
DAZ@ DA2@ DA2@ DA2@ DA2@ DA2@ DA2@ DA2@




1 1




Compal Confidential
2


PLA00 LA6951P Schematics Document 2




Intel Sandy Bridge Processor with DDRIII + Cougar Point
AIO M/B

3 3



2011-02-24
REV:1.A



4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PLA00 M/B LA-6951P Schematic 1.A
Date: Thursday, February 24, 2011 Sheet 1 of 62
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5 4 3 2 1



Compal Confidential
VRAM 1/2 GB
*1* :2D Display
Model Name : PLA00
File Name : LA6951P
GDDR5 x8 *2* :3D Display
P.28~31 DDR3-SO-DIMM X2 DDR3-SO-DIMM X2
Intel CPU BANK 0, 1, 2, 3 BANK 0, 1, 2, 3
P.10 P.11
D
SPI ROM Sandy Bridge D


23 LCD MX25L1005
VGA 1066/1333MHz 1.5V 1066/1333MHz 1.5V
AMG-12G SOP8
P.21
PEGx16 Desktop Channel A Channel B
NVdia N12P-GT
38~43W
HDMI
OUT
95W F B-CAS
LVDS conn SPI ROM
W25X40BVSNIG 29mm x 29mm B LGA1155
RF IN
P.36 SOIC 8P 37.5mm x 37.5mm
P.21~27
P.35 P.4~9
Option
FDIx8 DMIx4 USB USB2.0 x2 Touch 3D IR TV Tuner
G Dual DVI 100 MHz 100 MHz WebCAM Side port A Screen
BT
Module On Mini Card
DVI P.36 P.46 P.36 P.49 P.49 P.44
C PCH PCIE
HDMI HDMI OUT USB2.0 x11 Port 7
IN
Scalar Cougar Point 3.3V 48MHz Port 5 Port 0,1 Port 2,3,6,9 Port 4 Port 10 Port 7 Port 11
C
AV-IN Realtek DVI HDMI Switch DVI from UMA
H67
C


D RTD2667 P.33
PCIEx4 100MHz 2.5/5.0 GT/S
Port 2 Port 6 Port 5 Port 1
HD_Audio
3.3V 24MHz
FCBGA-942 SATAx3 SATA 1.5/3.0 GT/S
P.35 Port 0 SATA3.0 Port 1 SATA3.0 Port 4 SATA2.0
27mm x 27mm Master1 Master2 Master3 USB
I2S HP conn Port 12
P.12~20
P.43 3.5"
SATA SSD SATA ODD Intel WLAN Card Reader
Conn SATA HDD Conn LAN On Mini Card RT5029
Connector 82579 7 in 1 or better
I2S 2 HP AMP P.37 P.37 P.37 P.41 P.44 P.39
H G1412RC1U Audio Codec SPI ROM
P.43 MX25L3206 Slim BD support 3D GIGA
ALC662 EM2I-12G LAN
P.41 (4MB) P.13
2 SPI ROM
DAC 5 MX25L1005
LPC
TI PCM1606
5 33MHz AMC-12G
P.46
A E F
B
P.47 IO Board P.38 B



AMP x3 INT EXT KBC
APA_106
P.42
MIC
P.36
MIC
P.43
E PS/2
ENE KB930-A1
P.45
RJ45 USB3.0 x2
NEC uPD720200A HDMI IN Antenna Jack
Conn
P.38 P.38

SPK 3W x5 USB2.0 AV-IN
USB3.0 PS/2

3D Scalar Board Dual USB2.0 x2 USB2.0/3.0 HDMI OUT
CVBS AIN-L AIN-R
Conn x2 Conn P.38
DVI
G
Dual DVI HDMI
IN
4 ch. LVDS C B C D-1 D-2
3D scalar Power ENE Touch D AV
IN
P.35 CVBS
A
D-1 Button SB3534 Button AIN SW AIN
A


TS5A23157
P.50 P.50 H P.47

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/20 2011/07/20 Title
23.6" LCD Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev
120Hz LCD AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom PLA00 M/B LA-6951P Schematic
1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 24, 2011 Sheet 2 of 62
5 4 3 2 1
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Voltage Rails
SIGNAL
Power Plane Description S1 S3 S5 STATE SLP_S3# SLP_S4# SLP_S5# +VALW +VSB +VS
+12V1 Adapter power supply (12V)(For V_5V;V_3.3V;1.5V;12VS) ON ON OFF
Full ON HIGH HIGH HIGH ON ON ON
Adapter power supply (12V)(For
+12V2 ON ON OFF
VGA_CORE;1.05VS;VRAM_1.5VS;CPU_CORE;VGFX_COREP) S1(Power On Suspend) HIGH HIGH HIGH ON ON ON
+CPU_CORE Core voltage for CPU ON OFF OFF
1
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF 1
+VGFX_CORE Graphics voltage for CPU ON OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF S4 (Suspend to Disk) LOW LOW HIGH ON ON OFF
+1.05VS 1.05V switched power rail for CPU ON OFF OFF
S5 (Soft OFF) LOW LOW LOW OFF ON OFF
+1.05VS_PCH 1.05V switched power rail for PCH ON OFF OFF
+1.5V 1.5V power rail for DDRIII ON ON OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8VS 1.8V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail once PS_ON# low ON ON OFF
+3VSB 3.3V power rail befor PS_ON# low ON ON ON
+3.3V_LAN 3.3V power rail for LAN ON ON ON
+3VS 3.3V switched power rail ON OFF OFF
+V_3.3V 3.3V power rail once Adapter plug-in ON ON OFF
+V_5V 5V power rail once Adapter plug-in ON ON OFF
+5VSB 5V power rail befor PS_ON# low ON ON ON
+5VALW 5V always on power rail once PS_ON# low ON ON ON
SKU ID(Project) Table
+5VS 5V switched power rail ON OFF OFF
2
+RTCVCC RTC power ON ON ON Project_ID2 Project_ID1 Project_ID0 2
BOARD ID Table (GPIO38) (GPIO37) (GPIO36) SKU
+3VS_DGPU 3.3V power rail for GPU ON OFF OFF
+VGA_CORE Graphics power rail for GPU ON OFF OFF Board ID Ra/Rb Vad-bid 0 0 0 UMA@
+1.05VS_DGPU 1.05VS switched power rail for GPU ON OFF OFF AV SKU R442 100K 3.3V 0 0 1 DIS@(VRAM:Hynix)
+VRAM_1.5VS 1.5VS power rail for VRAM ON OFF OFF NON AV SKU R445 0 ohm 0V 0 1 0 DIS@(VRAM:Samsung)
0 1 1 X
1 0 0 X
1 0 1 X
1 1 0 X
1 1 1 X
USB Port Table
6 External BTO Option Table
USB 2.0 USB 1.1 Port
USB Port BTO Item BOM Structure
EC SM Bus address 0 USB Conn. VGA VGA@
UHCI0
1 USB Conn UMA Only UMA@
3 3
Device Address DIS Only DIS@
VGA Thermal Sensor(Internal) 0*9E H
2 USB Conn
UHCI1 2D 2D@
VGA Thermal Sensor(External) 0*9A H 3 USB Conn 3D 3D@
EHCI1
4 Touch Screen VGA_2D VGA_2D@
UHCI2
5 Web Camera CRT CRT@
6 USB 2.0 PCM1606 1606@
UHCI3 Samsung
PCH SM Bus address 7 3D IR X76_SAM@
VRAM(1G)
8 Hynix
Device Address UHCI4 X76_HYN@
9 USB 2.0 VRAM(1G)
DDR(JDIMM1) 1010 0000 b
DDR(JDIMM2) 1010 0010 b
10 Blue Tooth Samsung
UHCI5 VRAM(2G) X76_SAM2G@
DDR(JDIMM4) 1010 0100 b
EHCI2 11 Mini Car(WLAN)
DDR(JDIMM3) 1010 0110 b
12 Mini Car(TV Tuner)
UHCI6 Hynix
13 VRAM(2G) X76_HYN2G@
AV-IN SKU AV@
4 No AV-IN SKU NON_AV@ 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2011/07/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PLA00 M/B LA-6951P Schematic 1.A
Date: Thursday, February 24, 2011 Sheet 3 of 62

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DMI_PTX_HRX_N[0..3] <14> PEG_GTX_C_HRX_P[0..15] <22>
DMI_PTX_HRX_P[0..3] <14> PEG_GTX_C_HRX_N[0..15] <22>

DMI_HTX_PRX_N[0..3] <14> PEG_HTX_C_GRX_P[0..15] <22>
DMI_HTX_PRX_P[0..3] <14> PEG_HTX_C_GRX_N[0..15] <22>
SKT_H2
JCPU1C Note:Use 0.1uF now; If need to support to Gen3, need change C1~C32 to 0.22uF.

PEG_GTX_C_HRX_P15 B11 C13 PEG_HTX_GRX_P15 C1 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P15
PEG_GTX_C_HRX_N15 PEG_RX[0] PEG_TX[0] PEG_HTX_GRX_N15 C2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N15
B12 PEG_RX#[0] PEG_TX#[0] C14 1 2
D PEG_GTX_C_HRX_P14 D12 E14 PEG_HTX_GRX_P14 C3 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P14 D
PEG_GTX_C_HRX_N14 PEG_RX[1] PEG_TX[1] PEG_HTX_GRX_N14 C4 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N14
D11 PEG_RX#[1] PEG_TX#[1] E13 1 2
PEG_GTX_C_HRX_P13 C10 G14 PEG_HTX_GRX_P13 C5 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P13
PEG_GTX_C_HRX_N13 PEG_RX[2] PEG_TX[2] PEG_HTX_GRX_N13 C6 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N13
C9 PEG_RX#[2] PEG_TX#[2] G13 1 2
PEG_GTX_C_HRX_P12 E10 F12 PEG_HTX_GRX_P12 C7 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P12
PEG_GTX_C_HRX_N12 PEG_RX[3] PEG_TX[3] PEG_HTX_GRX_N12 C8 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N12
E9 PEG_RX#[3] PEG_TX#[3] F11 1 2
PEG_GTX_C_HRX_P11 B8 J14 PEG_HTX_GRX_P11 C9 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P11
PEG_GTX_C_HRX_N11 PEG_RX[4] PEG_TX[4] PEG_HTX_GRX_N11 C10 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N11
B7 PEG_RX#[4] PEG_TX#[4] J13 1 2
PEG_GTX_C_HRX_P10 C6 D8 PEG_HTX_GRX_P10 C11 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P10
PEG_GTX_C_HRX_N10 PEG_RX[5] PEG_TX[5] PEG_HTX_GRX_N10 C12 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N10
C5 PEG_RX#[5] PEG_TX#[5] D7 1 2
PEG_GTX_C_HRX_P9 A5 D3 PEG_HTX_GRX_P9 C13 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P9
PEG_GTX_C_HRX_N9 PEG_RX[6] PEG_TX[6] PEG_HTX_GRX_N9 C14 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N9
A6 PEG_RX#[6] PEG_TX#[6] C3 1 2




PEG
PEG_GTX_C_HRX_P8 E2 E6 PEG_HTX_GRX_P8 C15 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P8
PEG_GTX_C_HRX_N8 PEG_RX[7] PEG_TX[7] PEG_HTX_GRX_N8 C16 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N8
E1 PEG_RX#[7] PEG_TX#[7] E5 1 2
PEG_GTX_C_HRX_P7 F4 F8 PEG_HTX_GRX_P7 C17 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P7
PEG_GTX_C_HRX_N7 PEG_RX[8] PEG_TX[8] PEG_HTX_GRX_N7 C18 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N7
F3 PEG_RX#[8] PEG_TX#[8] F7 1 2
PEG_GTX_C_HRX_P6 G2 G10 PEG_HTX_GRX_P6 C19 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P6
PEG_GTX_C_HRX_N6 PEG_RX[9] PEG_TX[9] PEG_HTX_GRX_N6 C20 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N6
G1 PEG_RX#[9] PEG_TX#[9] G9 1 2
PEG_GTX_C_HRX_P5 H3 G5 PEG_HTX_GRX_P5 C21 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P5
PEG_GTX_C_HRX_N5 PEG_RX[10] PEG_TX[10] PEG_HTX_GRX_N5 C22 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N5
H4 PEG_RX#[10] PEG_TX#[10] G6 1 2
PEG_GTX_C_HRX_P4 J1 K7 PEG_HTX_GRX_P4 C23 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P4
PEG_GTX_C_HRX_N4 PEG_RX[11] PEG_TX[11] PEG_HTX_GRX_N4 C24 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N4
J2 PEG_RX#[11] PEG_TX#[11] K8 1 2
PEG_GTX_C_HRX_P3 K3 J5 PEG_HTX_GRX_P3 C25 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P3
PEG_GTX_C_HRX_N3 PEG_RX[12] PEG_TX[12] PEG_HTX_GRX_N3 C26 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N3
K4 PEG_RX#[12] PEG_TX#[12] J6 1 2
PEG_GTX_C_HRX_P2 L1 M8 PEG_HTX_GRX_P2 C27 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P2
PEG_GTX_C_HRX_N2 PEG_RX[13] PEG_TX[13] PEG_HTX_GRX_N2 C28 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N2
L2 PEG_RX#[13] PEG_TX#[13] M7 1 2
PEG_GTX_C_HRX_P1 M3 L6 PEG_HTX_GRX_P1 C29 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P1
PEG_GTX_C_HRX_N1 PEG_RX[14] PEG_TX[14] PEG_HTX_GRX_N1 C30 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N1
M4 PEG_RX#[14] PEG_TX#[14] L5 1 2
PEG_GTX_C_HRX_P0 N1 N5 PEG_HTX_GRX_P0 C31 1 2 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_P0
C PEG_GTX_C_HRX_N0 PEG_RX[15] PEG_TX[15] PEG_HTX_GRX_N0 C32 VGA@ .1U_0402_16V7K PEG_HTX_C_GRX_N0 C
N2 PEG_RX#[15] PEG_TX#[15] N6 1 2

DMI_PTX_HRX_P0 W5 V7 DMI_HTX_PRX_P0
DMI_PTX_HRX_N0 DMI_RX[0] DMI_TX[0] DMI_HTX_PRX_N0
W4 DMI_RX#[0] DMI_TX#[0] V6
DMI_PTX_HRX_P1 V3 W7 DMI_HTX_PRX_P1
DMI_PTX_HRX_N1 DMI_RX[1] DMI_TX[1] DMI_HTX_PRX_N1
V4 DMI_RX#[1] DMI_TX#[1] W8
DMI_PTX_HRX_P2 Y3 Y6 DMI_HTX_PRX_P2
DMI_PTX_HRX_N2 DMI_RX[2] DMI_TX[2] DMI_HTX_PRX_N2
DMI


Y4 DMI_RX#[2] DMI_TX#[2] Y7
DMI_PTX_HRX_P3 AA4 AA7 DMI_HTX_PRX_P3
DMI_PTX_HRX_N3 DMI_RX_3 DMI_TX[3] DMI_HTX_PRX_N3
AA5 DMI_RX#[3] DMI_TX#[3] AA8

P3 PE_RX[0] PE_TX[0] P8
P4 PE_RX#[0] PE_TX#[0] P7
R2 PE_RX[1] PE_TX[1] T7
R1 PE_RX#[1] PE_TX#[1] T8 7/20 PE_TX[0~3]/PE_TX#[0~3] only use on
7/20 PE_RX[0~3]/PE_RX#[0~3] only use on T4 PE_RX[2] PE_TX[2] R6 Workstation.
GEN




Workstation. T3 PE_RX#[2] PE_TX#[2] R5
U2 PE_RX[3] PE_TX[3] U5
U1 PE_RX#[3] PE_TX#[3] U6
+1.05VS

24.9_0402_1% 2 1 R1 PEG_IRCOMP B5 PEG_ICOMPO H_FDI_TXN[0..7] <16>
C4 PEG_RCOMPO H_FDI_TXP[0..7] <16>
B4 PEG_ICOMPI SKT_H2
JCPU1D

LOTES_ACAZIF096P01_SANDYBRIDGE 3 OF 11
PEG_ICOMPI and RCOMPO signals should be shorted and CONN@ AC8 H_FDI_TXP0
FDI_TX[0] H_FDI_TXN0
FDI_TX#[0] AC7
B routed <16> H_FDI_FSYNC0 AC5 AC2 H_FDI_TXP1 B
FDI_FSYNC_0 FDI_TX[1] H_FDI_TXN1
with - max length = 500 mils - ;Width/Space= (4 mils/15mils) <16> H_FDI_LSYNC0 AC4 FDI_LSYNC_0 FDI_TX#[1] AC3
FDI_TX[0] AD2 H_FDI_TXP2
PEG_ICOMPO signals should be routed with - max length = FDI_TX[2] H_FDI_TXN2
FDI_TX#[2] AD1
AD4 H_FDI_TXP3
500 mils FDI_TX[3]
AD3 H_FDI_TXN3
FDI_TX#[3]
- Width/Space (12 mils/15mils)
AD7 H_FDI_TXP4
FDI_TX[4] H_FDI_TXN4
FDI_TX#[4] AD6
AE5 AE7 H_FDI_TXP5
<16> H_FDI_FSYNC1 FDI_FSYNC_1 FDI_TX[5]
AE4 AE8 H_FDI_TXN5
<16> H_FDI_LSYNC1 FDI_LSYNC_1 FDI_TX#[5]
AF3 H_FDI_TXP6
FDI_TX[6] H_FDI_TXN6
FDI_TX#[6] AF2