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A B C D E
1 1
QIQY6
2
Brandy3.0 (Y500) 2
LA-8692P Rev0.2 Schematic
3
Intel IVY Bridge Processor with DDRIII + Panther Point PCH 3
nVIDIA N13P GT-1 + 2nd VGA N13P GT-1
2012-02-05 Rev0.2
4 4
Security Classification LC Future Center Secret Data Title
Cover Page
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
P2968-AL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 1 of 66
A B C D E
A B C D E
Chief River
PCI-Express 16X Gen3 Intel
PEG 8~15 PEG 0~7 IVY Bridge Memory BUS (DDRIII)
Processor Dual Channel DDR3-SO-DIMM X2
2nd VGA N13P-GT1 N13P-GT1 BANK 0, 1, 2, 3
1 1
Socket-rPGA989 1.5V DDRIII 1066/1333/1600 MT/s
VRAM 64*32 VRAM 64*32 UP TO 16G
37.5mm*37.5mm
GDDR5*8 GDDR5*8
Sub/B (SLI) Page 32 Page 23,24,25,26,27,28,29,30,31
FDI *8 DMI *4
2.7GT/s 5GT/s
USB 2.0 1x USB Left
5V 480MHz USB 3.0 Port 2 TV
USB 2.0 Port 12
HDMI Conn. CRT Conn. LVDS Conn. USB 2.0 3x USB 3.0 Port 3
Page 38
USB Charger
Page 37 Page 36 Page 34 5V 480MHz Page 48 PS8710BT
HDMI1.4b Intel USB 3.0 3x Int. Camera
Page 50
BT
2 Panther Point 5V 5GT/s USB 3.0 Port 0
USB 2.0 Port 0
Page 50
USB 2.0 Port 13
Page 47
2
PCH
Atheros USB Right
FCBGA 989 Balls USB 2.0 2x
PCIe Gen1 1x PCIeMini Card mSATA SSD USB 2.0 Port 9, Cha
RJ45 Conn. AR8161 1G 1.5V 5GT/s
5V 480MHz
WLAN SATA Port 0
Page 40
AR8151 1G 25mm*25mm PCIe Port 2 page 38 Sub/B Page 50
PCIe Gen1 2x page 38
PCIe port 1 Page 39 5V 480MHz PCIeMini Card
PCIeMini Card
TV PCIe Port 3
SATA Gen3 Port 0 WLAN
USB Port 10 USB Port 12
5V 6GHz(600MB/s) page 38 page 38
CardReader
PCIe Gen1 1x
JMB389 1.5V 5GT/s
SD/MMC/MS/XD
PCIe port 4 Page 44 SATA Gen3 Port 1 SATA HDD
5V 6GHz(600MB/s) SATA Port 1
page 41
3 SPI ROM SPI BUS SATA Gen1 Port2 SATA ODD
3
(4MB+2MB) 3.3V 33MHz 5V 3GHz(300MB/s) SATA Port 1
page 41
Page 14
HD Audio
LPC BUS
3.3V 33MHz
3.3V 24MHz
EC Codec
SPK Conn.
ITE IT8580E ALC269Q-VC3 Page 43
Page 43
Page 45
Power Circuit DC/DC
Page 54,55,56,57,58,59,
60,61,62,63,64
Thermal Sensor Int. MIC Conn.
Touch Pad Int.KBD Ext. MIC Conn. HP Conn.
DC/DC Interface CKT. RTC CKT. (JCMOS Conn.)
4
Page 53 Page 54
EMC 1403 Page 50 Page 49 Page 49
4
Page 46 Page 46 Page 41 Sub/B Sub/B
POWER/B Conn. AUDIO, USB/B Conn.
Page 51 Page 49 Security Classification LC Future Center Secret Data Title
MB Block Diagram
Issued Date 2012/07/01 Deciphered Date 2014/07/01
ODD/B Conn. NOVO/B Conn. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
page 42 Page 51 DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
P2968-AL 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 2 of 66
A B C D E
A B C D E
Voltage Rails
SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+1.5VS
power +VCCSA S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
plane +V1.5S_VCCP
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1
+CPU_CORE 1
+5VALW +1.5V
+VGA_CORE S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+B
+GFX_CORE
+3VALW S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.8VS
+1.05VS
State
+0.75VS
+3.3VS_VGA
+1.5VS_VGA
+1.05VS_VGA
S0
O O O O
S3
O O O X
2 2
S5 S4/AC
O O X X USB Port Table
4 External BOM Structure Table
S5 S4/ Battery only USB 2.0 USB 3.0 Port
O X X X USB Port BOM Structure BTO Item
0 Camera HDMI@ HDMI part
S5 S4/AC & Battery
don't exist X X X X 1 Camera
TV@ TV module part
XHCI 1
2 CMOS@ CMOS Camera part
2 USB Port (Left Side) 8161@ AR8161 LAN part
elbaT lortnoC SUBMS EHCI1 3 USB Port (Left Side) 8151@ AR8151 LAN part
dn2 niaM lamrehT 3 USB Port (Left Side)
NALW rosneS 4 USB Port (Left Side) 8161S@ AR8161 LAN surge part
AGV AGV ECRUOS E0858TI TTAB NAWW MMIDOS HCP
4 8151S@ AR8151 LAN surge part
1KC_CE_BMS 5 SURGE@ AR8151&8161 LAN surge part
1AD_CE_BMS X W0L8A5V83T+
E I X V
WLAV3+
X X X X X 6 X76@ X76 Level part for VRAM
2KC_CE_BMS 7 GC6@ NV CG6 support part
2AD_CE_BMS X W0L8A5V83T+
E I X X X X X X V
SV3+ 8 NOGC6@ NV no CG6 support part
EHCI2
KLCBMS 9 USB Port (Right Side) AOAC@ AOAC support part
3 ATADBMS X WLAHC+
V3
P X X X V
SV3+
V
SV3+
X X 10 Mini Card(WLAN) KBL@ K/B Light part 3
KLC0LMS 11 ME@ ME part
ATAD0LMS X WLAH3+
V
CP X X X X X X X 12 Mini Card(TV) OPT@ For optimus function part
KLC1LMS 13 Blue Tooth SLI@ For SLI function part
ATAD1LMS V HCP
SV3+ WLAV3+
V
SV3+
X V
SV3+
X X V
SV3+
X DS3@ Deep S3 support part
PCIE PORT LIST GT@ NV chip part
Address Port Device @ Unpop
EC SM Bus1 address EC SM Bus2 address
1 LAN
Device Device Address
2 WLAN
Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_101xb
3 TV
Master VGA 0x9E
Slave VGA 0x9C
4 Card Reader
5
PCH SM Bus address 6
7
Device Address
8
DDR DIMM0 1001 000Xb
4 DDR DIMM2 4
1001 010Xb
ZZZ
Security Classification LC Future Center Secret Data Title
Notes List
Issued Date 2012/07/01 Deciphered Date 2014/07/01
DA80000T20J THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
P2968-AL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, June 05, 2012 Sheet 3 of 66
A B C D E
5 4 3 2 1
Hot plug detect for IFP link E
Performance Mode P0 TDP at Tj = 102 C* (GDDR5)
FBVDDQ PCI Express I/O and I/O and Other
VGA and GDDR5 Voltage Rails (N13Px GPIO) GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.8V) (1.05V) (3.3V)
GPIO I/O ACTIVE Function Description Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)
GPIO0 OUT - GPU VID4 N13X
128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
D
1GB D
GPIO1 OUT - GPU VID3 GDDR5
GPIO2 OUT - VGA_BL_PWM Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
GPIO3 OUT - VGA_ENVDD ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
GPIO4 OUT - VGA_ENBKL ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
GPIO5 OUT - GPU VID1
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
GPIO6 OUT - GPU VID2 STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
GPIO7 OUT - DPRSLPVR_VGA
STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO8 I/O - Thermal Catastrophic Over Temperature STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
CHANGE_GEN3
GPIO9 OUT - GPIO9
Device ID setting I2C Slave addrees ID
GPIO10 OUT - Memory VREF Control N13P-GT SMB_ALT_ADDR
(28nm) 0x0FDB 0 0x9E
(ROM_SO Bit 1)
GPIO11 OUT - GPU VID0
C C
1 0x9C
GPIO12 IN AC Power Detect Input (10K pull High)
GPIO13 OUT - GPU VID5
GPIO14 OUT - FB_CLAMP_TOGGLE_REQ#
GPU ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
GPIO15 IN N/A (100K pull low) PU 25K PU 5K
GC6@ SLI@
GPIO16 OUT - GPIO16 N13P-GT1
28nm PU 10K PU 45K PD 5K PD 10K PD 45K
PU 5K PD 5K
GPIO17 IN N/A GPIO17 OPT@
OPT@,SLI@
GPIO18 IN - dGPU_HDMI_HPD
GPIO19 IN - GPIO19
GPU N13P-GT
FB Memory (GDDR5) ROM_SI
Samsung K4G10325FD-FC04
B
+3VS_VGA 2500MHz B
32Mx32 PD 45K
+VGA_CORE
Hynix H5GQ1H24BFR-T2C
tNVVDD >0 2500MHz
+1.5VS_VGA 32Mx32 PD 35K
tFBVDDQ >0
Samsung K4G20325FD-FC04
+1.05VS_VGA 2500MHz
tPEX_VDD >0 64Mx32 PD 30K
1. all power rail ramp up time should be larger than 40us
Hynix H5GQ2H24AFR-T2C
2500MHz
64Mx32 PD 25K
Other Power rail
+3VS_VGA
A A
Tpower-off <10ms
Security Classification LC Future Center Secret Data Title
VGA Notes List
1.all GPU power rails should be turned off within 10ms
Issued Date 2012/07/01 Deciphered Date 2014/07/01
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
P2968-AL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, June 07, 2012 Sheet 4 of 66
5 4 3 2 1
5 4 3 2 1
D D
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
+1.05VS impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
1
max length = 500 mils
R1
24.9_0402_1%
- typical impedance = 14.5 mohms
JCPU1A
2
J22 PEG_COMP
PEG_ICOMPI J21
B27 PEG_ICOMPO H22
<16> DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO
B25
<16> DMI_CRX_PTX_N1 DMI_RX#[1]
A25
<16> DMI_CRX_PTX_N2 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] <23,32>
B24 K33 PCIE_CRX_GTX_N0
<16> DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0] M35 PCIE_CRX_GTX_N1
B28 PEG_RX#[1] L34 PCIE_CRX_GTX_N2
<16> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2]
B26 J35 PCIE_CRX_GTX_N3 PEG Static Lane Reversal - CFG2 is for the 16x
<16> DMI_CRX_PTX_P1 DMI_RX[1] PEG_RX#[3]
A24 J32 PCIE_CRX_GTX_N4
<16> DMI_CRX_PTX_P2
DMI
B23 DMI_RX[2] PEG_RX#[4] H34 PCIE_CRX_GTX_N5
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] H31 PCIE_CRX_GTX_N6 1: Normal Operation; Lane # definition matches
G21 PEG_RX#[6] G33 PCIE_CRX_GTX_N7
<16> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] CFG2 socket pin map definition
E22 G30 PCIE_CRX_GTX_N8
<16> DMI_CTX_PRX_N1 F21 DMI_TX#[1] PEG_RX#[8] F35 PCIE_CRX_GTX_N9
<16> DMI_CTX_PRX_N2 D21 DMI_TX#[2] PEG_RX#[9] E34 PCIE_CRX_GTX_N10 0:Lane Reversed
<16>
<16>
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
G22
D22
DMI_TX#[3]
DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
D33
D31
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_N12 *
PCIE_CRX_GTX_N13
C <16> DMI_CTX_PRX_P1 F20 DMI_TX[1] PEG_RX#[13] B33 PCIE_CRX_GTX_N14 C
<16> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
PCI EXPRESS* - GRAPHICS
C21 C32 PCIE_CRX_GTX_N15
<16> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_CRX_GTX_P[0..15] <23,32>
J33 PCIE_CRX_GTX_P0