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1 2 3 4 5 6 7 8
(17.3") Intel Shark Bay Platform Block Diagram 01
A A
Realtek RTD2136R
ILVDS LVDS Interface
DP to LVDS Converter LCD Conn
DDR3L SODIMM1 (STN 8H) CHA0 PAGE 24 PAGE 27 PCB 8L STACK UP
Maximam 4GBs
BOT Side PAGE 13 DDR3L CHA 1600MT/s LAYER 1 : TOP
eDP (5.4Gb/s) IEDP eDP Interface eDP Conn
LAYER 2 : SGND
DDR3L SODIMM2 (STN 4H) CHA1
Intel Proccesor N4K2K PAGE 27 LAYER 3 : IN1(High)
Maximam 4GBs LAYER 4 : SVCC
HDMI (5.4Gb/s)
TOP Side PAGE 14 LAYER 5 : IN2
Haswell PIHM PS8401A 4K2K Port B
HDMI Conn LAYER 6 : IN3(High)
HDMI Repeater
Processor : Daul / Quad Core PAGE 26 PAGE 26 LAYER 7 : SGND1
DDR3L SODIMM3 (STN 4H) CHB0
Power : 35 / 45 (Watt) LAYER 8: BOT
Maximam 4GBs
Package : rPGA947
BOT Side PAGE 15 DDR3L CHB 1600MT/s BPM Interface
Size : 37.5 x 37.5 (mm) CPU XDP TP
Power Source
PAGE 2-6 PAGE 2
DDR3L SODIMM4 (RUV 4H) CHB1
Intersil ISL88732C
Maximam 4GBs
DP SSC PLL CLK 135MHz
OEHM System Charger Power
TOP Side PAGE 16 dLVDS
DMI CLK 100MHz
DMI x 4 (2.5Gb/s)
FDI x 2 (2.7Gb/s)
DP PLL CLK 135MHz
PAGE 37
B B
PEG GEN3(8.0GT/S) 16-LANE N14P-GS
TPS51123A
dEDP
System 5V/3V Power
DIS VGA PAGE38
PAGE 17-23
TPS51211DSCR
DIS VGA +1.05V PCH Power
PCH VGA PAGE 40
CRT Conn Intel PCH USB3.0 (6Gb/s)
PAGE 27
TPS51216
Port1 Port2 Port3 Port4
+1.35V DDR3L Power
mSATA Conn.
PCH XDP TP
JTAG Interface Lynx Point USB3.0/2.0 Conn. USB3.0/2.0 Conn. USB3.0/2.0 Conn. USB3.0/2.0 Conn.
PAGE 39
Gen3 as HM87.
PAGE 28
*Port1
PAGE 8
SATA Gen3 (6Gb/s)
HM86/*HM87 USB2.0 (480Mb/s) Port0
PAGE 29
Port1
PAGE 29
Port2
PAGE 30
Port3
PAGE 30
Intersil ISL95812HRZ-T
Platform Controller Hub +VCCIN CPU Power
Port0 Port4 Port3 Power : 3.5 Watt Port10 Port11 Port 9 Port 8 PAGE 41
32.768MHz
25MHz
Package : FCBGA695
WLAN Conn.
ODD Conn.(Gen1) 2nd HDD Conn. 1st HDD Conn. Size : 20 x 20 (mm) CCD Camera 3D IR module TV TUNER RT8812A
mPCIe/TV
PAGE 30 PAGE 31 PAGE 31 PAGE 7-12 PAGE 28 PAGE 27 PAGE 27 PAGE 28 VGA_CORE
C C
PAGE 43
Port 12 Port 13
AZALIA
TPS51362RVER
PCIE Gen2 (2.5Gb/s) Port3 Touch Screen
8MB SPI ROM CS0# SPI Interface +1.5V_GFX
Realtek GL834L
PCH(ME+EC+BIOS) Port4 PAGE 27 PAGE 44
PAGE 8 LPC Interface Card Reader
Atheros 10/100 Power :
PWR SW
Giga LAN Package : QFN24
+3.3V_GFX /+1.05V_GFX
Nuvoton Conexant LAN Controller Size : 4 x 4 (mm)
PAGE 44
NPCE885LA0DX CX20755-11Z Power : PAGE 33
Embedded Controller Audio Codec Package : QFN40
Power : Power :2 Watt Size : 5 x 5 (mm)
NCT5605Y 3ND_SMBus
Package : LQFP128 Package : 40-QFN PAGE 26
Extenal GPIO
PAGE 34 Size : 14 x 14 (mm) Size : 5 x 5 (mm)
PAGE 34 PAGE 32 25MHz
APE8872M
CIR AMP(DFN-12)
Touch Pad Conn. Keyboard Conn. FAN Controller
RLC105-VE
PAGE 35 PAGE 35 PAGE 3 PAGE 35 PAGE 32
D D
Quanta Computer Inc.
PROJECT : BDBE
Size Document Number Rev
1A
Block Diagram
Date: Monday, December 17, 2012 Sheet 1 of 45
1 2 3 4 5 6 7 8
5 4 3 2 1
+5V_S5
S5_ON enable
AON7406
low switch +5V
(Peak 3.4A ,AVG 2.38A)
MAIND enable
02
AC (Peak 13.77A ,AVG 9.6A) OCP 16.5A
System SYSTEM POWER
Charger RT8223
D
DC ISL88732C PWM D
AON7406
PWM low switch +3V MAIND enable
+3V_S5
S5_ON enable (Peak 2.6A ,AVG 1.82A)
(Peak 9.56A ,AVG 6.69A) OCP 11.5A
G9661-25ADJ
LDO +1.5V MAINON enable
(Peak 1.49A ,AVG 1.05A)
+VTT_VREF AO6402 +3V_GFX DGPU_PWR_EN
SUSON enable low switch
(Peak 6.0A ,AVG 4.2A)
TPS51216 +VTT
PWM S3_1.35 enable
C
+1.35VSUS C
SUSON enable CONTROL Power States
(Peak 14.2A ,AVG 9.94A) OCP 17A POWER PLANE VOLTAGE SIGNAL ACTIVE IN
VIN 10V~+19V S0~S5
+VCCRTC +3.0V~+3.3V S0~S5
TPS51211 AON7406 +3V +3.3V MAIN_ON S0
PWM +1.05V low switch +1.05V_GFX MAIND enable
MAINON enable +3V_S5 +3.3V S5_ON S0~S5
(Peak 6.0A ,AVG 4.2A)
(Peak 6.52A ,AVG 4.57A) OCP 8A
+3V_HDP +3.3V MAIN_ON S0
+3VPCU +3.3V AC/DC Insert enable S0
+5V +5V MAIN_ON S0
ISL95812HRZ-T +5V_S5 +5V S5_ON S0~S5
PWM +VCC_CORE
VRON enable +5VPCU +5V AC/DC Insert enable S0~S5
B
(Peak 85A ,AVG 33A) OCP 120A B
WIMAX_P +3.3V WMAX_P for WLAN
+1.5V +1.5V MAIN_ON S0
+1.35V_SUS +1.35V SUSON S0~S3
RT8812A
PWM +VGPU_CORE +VCC_CORE VRON S0
DGPU_PWR_EN
+1.05V +1.05V MAIN_ON S0
(Peak 42A ,AVG 30A) OCP 50A
TPS51363 +1.5V_GFX
PWM
GPU_PWR_GD
(Peak 10A ,AVG 8A) OCP 12A
A A
Quanta Computer Inc.
PROJECT : BDBE
Size Document Number Rev
1A
POWER TREE TABLE
Date: Monday, December 17, 2012 Sheet 2 of 45
5 4 3 2 1
5 4 3 2 1
+1.05V VCCST
Haswell Processor (CLK,MISC,JTAG)
Haswell Processor (DMI,PEG,FDI)
03
R65 *0_4
Haswell rPGA EDS C73 Haswell rPGA EDS
U3A *0.1U/10V_4 U3B
E23 PEG_RCOMP TP118 SKTOCC# AP32 MISC AP3 SM_RCOMP_0 R147 100/F_4
PEG_RCOMP PEG_RX#[0..15] 17 SKTOCC SM_RCOMP_0
M29 PEG_RX#0 AR3 SM_RCOMP_1 R145 75/F_4
DDR3
PEG_RXN_0 SM_RCOMP_1
THERMAL
D21 K28 PEG_RX#1 TP119 CATERR# AN32 AP2 SM_RCOMP_2 R148 100/F_4
7 DMI_TXN0 DMI_RXN_0 PEG_RXN_1 CATERR SM_RCOMP_2
C21 M31 PEG_RX#2 10,34 EC_PECI EC_PECI AR27 AN3 CPU_DRAMRST# CPU_DRAMRST# 25
7 DMI_TXN1 DMI_RXN_1 PEG_RXN_2 PECI SM_DRAMRST
B21 L30 PEG_RX#3 TP6 AK31
7 DMI_TXN2 DMI_RXN_2 PEG_RXN_3 FC_AK31
A21 M33 PEG_RX#4 H_PROCHOT# R82 56_4 H_PROCHOT#_R AM30 AR29 XDP_PRDY#
7 DMI_TXN3 DMI_RXN_3 PEG_RXN_4 37,41 H_PROCHOT# PROCHOT PRDY TP15
L32 PEG_RX#5 PM_THRMTRIP# AM35 AT29 XDP_PREQ#
PEG_RXN_5 THERMTRIP PREQ TP1
D20 M35 PEG_RX#6 AM34 XDP_TCLK
PEG
7 DMI_TXP0 DMI_RXP_0 PEG_RXN_6 TCK
C20 L34 PEG_RX#7 AN33 XDP_TMS
JTAG
7 DMI_TXP1 DMI_RXP_1 PEG_RXN_7 TMS
D
B20 E29 PEG_RX#8 AM33 XDP_TRST# D
7 DMI_TXP2 DMI_RXP_2 PEG_RXN_8 TRST
A20 D28 PEG_RX#9 7 PM_SYNC R144 0_4 PM_SYNC_R AT28 AM31 XDP_TDI
7 DMI_TXP3
DMI
PWR
PWR
DMI_RXP_3 PEG_RXN_9 E31 PEG_RX#10 R158 0_4 H_PWRGOOD_R AL34 PM_SYNC TDI AL33 XDP_TDO
PEG_RXN_10 10 H_PWRGOOD PWRGOOD TDO TP5
D18 D30 PEG_RX#11 25 PM_DRAM_PWRGD_R PM_DRAM_PWRGD_R AC10 AP33 XDP_DBRST# XDP_DBRST# 7
7 DMI_RXN0 DMI_TXN_0 PEG_RXN_11 SM_DRAMPWROK DBR
C17 E35 PEG_RX#12 10 CPU_PLTRST# R139 0_4 CPU_RST#_R AT26
7 DMI_RXN1 DMI_TXN_1 PEG_RXN_12 PLTRSTIN
B17 D34 PEG_RX#13 AR30 XDP_BPM#0
7 DMI_RXN2 DMI_TXN_2 PEG_RXN_13 BPM_N_0 TP18
A17 E33 PEG_RX#14 AN31 XDP_BPM#1
7 DMI_RXN3 DMI_TXN_3 PEG_RXN_14 BPM_N_1 TP116
E32 PEG_RX#15 3 4 CLK_DPLL_NSCLKN_R G28 AN29 XDP_BPM#2
PEG_RX[0..15] 17 9 CLK_DPLL_NSCLKN TP115
CLOCK
D17 PEG_RXN_15 L29 PEG_RX0 1 2 CLK_DPLL_NSCLKP_R H28 DPLL_REF_CLKN BPM_N_2 AP31 XDP_BPM#3
7 DMI_RXP0 DMI_TXP_0 PEG_RXP_0 9 CLK_DPLL_NSCLKP DPLL_REF_CLKP BPM_N_3 TP114
C18 L28 PEG_RX1 RP3 3 4 0_4P2R CLK_DPLL_SSCLKN_R F27 AP30 XDP_BPM#4
7 DMI_RXP1 DMI_TXP_1 PEG_RXP_1 9 CLK_DPLL_SSCLKN SSC_DPLL_REF_CLKN BPM_N_4 TP16
B18 L31 PEG_RX2 1 2 CLK_DPLL_SSCLKP_R E27 AN28 XDP_BPM#5
7 DMI_RXP2 DMI_TXP_2 PEG_RXP_2 9 CLK_DPLL_SSCLKP SSC_DPLL_REF_CLKP BPM_N_5 TP13
A18 K30 PEG_RX3 RP2 3 4 0_4P2R CLK_CPU_BCLKN_R D26 AP29 XDP_BPM#6
7 DMI_RXP3 DMI_TXP_3 PEG_RXP_3 9 CLK_CPU_BCLKN