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5 4 3 2 1




VTERM(+0.9V) 2009.09.28.
VTT(+1.05V) Lenovo Caucasus 2 (Pine Trail) Block Diagram
+1.5VSUS VID[0:6]
+1.5V XDP CPU VCORE IMVP 6
D
+VCC18MEM +/- CPU_CLK
D




+1.8V Pineview +/- HCLK
+2.5V Thermal DOT96_CLK
Clock Gengerator
3VPCU Sensor LCD_CLK CK505M
+3.3V PE_CLK
+3VS5 RGB Micro-FCBGA8
LCD_3.3V CRT MEMCLK0,1
MEMCLK2,3
DDR2
LCD_5V LVDS
+5V 10.1" LCD CHA 533/667
C TS Panel SO-DIMM C


(Up to 2GB)
X2 DMI
USB

Ethernet LAN SATA
2.5" HDD/SSD
10/100/1000 Tigerpoint
RJ-45 PCI-e PCI-e
BCM57780 Mini PCIe Slot WLAN (Half)
B 360-MMAP PCI-e/USB WWAN / SIM (Fully)
B



Mini PCIe Slot
HDA CODEC HD Audio (Option DTV)
HP/Mic
CX20582-11Z USB Card Reader 6 in 1 Card
Int. DMic
LPC BUS
AU6433B52 Reader Socket
USBX2
APS X,Y,Z USB PORT X 2
SPDIF ITE SPI
LIS34ALTR USB
IT8502 Flash Camera Conn. Camera Module
Int. SPK 1.3M / VGA




[email protected]
A A


1.5W X 2 USB
BT Connector
Quanta Computer Inc.
Int. KB T/P Battery Charger PROJECT : FL2
Size Document Number Rev
1A
Block Diagram
Date: Thursday, November 05, 2009 Sheet 1 of 36
5 4 3 2 1
1 2 3 4 5 6 7 8


Table of Contents Voltage Rails & Power States
PAGE DESCRIPTION POWER PLANE DESCRIPTION VOLTAGE CONTROL SIGNAL S0 S3 S4 S5
1 Schematic Block Diagram
VA Adapter Power Pulg In 20V Y Y Y Y
2
VBAT Battery Power 12V ~ 10V Y Y Y Y
VIN System Power (Adapter or Battery Power) 10V ~ 20V Y Y Y Y
A A

5VPCU System Always Power 5V PWM IC Y Y Y Y
3VPCU System Always Power 3.3V PWM IC Y Y Y Y
+5V_S5 System Aux Power (Wake Up On LAN) 5V S5_ON Y Y N /(Y) N /(Y)
+3V_S5 System Aux Power (Wake Up On LAN) 3.3V S5_ON Y Y N /(Y) N /(Y)
+5VSUS System Aux Power 5V SUS_ON Y Y N N
+3VSUS System Aux Power 3.3V SUS_ON Y Y N N
+5V System Normal Power 5V Main_ON Y N N N
+3V System Normal Power 3.3V Main_ON Y N N N


B B




C C




GND PLANE PAGE DESCRIPTION

GND ALL




D D




Quanta Computer Inc.
PROJECT : FL2
Size Document Number Rev
1A
POWER MANAGER
Date: Thursday, November 05, 2009 Sheet 2 of 36
1 2 3 4 5 6 7 8
A B C D E




add at 7/20 a-shian for Intel
C130 27P/50V_4 CLK_XIN_CK505 3
U2
X1
CPUC0 60 HCLK_CPUN (4)
03


2
CPUT0 61 HCLK_CPUP (4)
+3.3V Y1
14.318MHZ/20P/20PPM CPUC1_F 57 HCLK_MCHN (4)
27P/50V_4 58 HCLK_MCHP (4)




1
R259 R96 0_4 CLK_XOUT_CK505 CPUT1_F
2 X2
*10K_4 C129 PM_STPCPU# 44 53
(11) PM_STPCPU# CPU_STOP# CPUC2_ITP/SRCC8 CLK_PCIE_DMIN (4)
4 PM_STPCPU# PM_STPPCI# 45 54 4
(11) PM_STPPCI# PCI_STOP# CPUT2_ITP/SRCT8 CLK_PCIE_DMIP (4)
PM_STPPCI#
(11,14,18,24) PCLK_SMB_M 7 SMBCLK 27MHz_NonSS/SRCT1/SE1 24 DREFSSCLKP (4)
R260 (11,14,18,24) PDAT_SMB_M 6 25
SMBDAT 27MHz_SS/SRCC1/SE2 DREFSSCLKN (4)
*10K_4
CLKEN 63 20
CK_PWRGD/PD# DOTT_96/SRCT0 DREFCLKP (4)
DOTC_96/SRCC0 21 DREFCLKN (4) CLK REQ
R79 33/F_4 CLKUSB_48_R 17 REQ Mapping
(8) CLKUSB_48
CPU_BSEL0 R80 2.2K/F_4 USB_48MHz/FSLA
31 PCIE_REQ_HD#_R Mapping
SRCT3/CR#_C T11
CPU_BSEL1 R232 1K/F_4 CLK_FSB_R 64 32 PCIE_REQ_CARD#_R R76 475/F_4 CR#_C SRC_0 or SRC_2
FSLB/TEST_MODE SRCC3/CR#_D PCIE_REQ_CARD# (24)
R95 33/F_4 14M_ICH_R 5 34 CR#_D LCCLK or SRC_4
(11) 14M_ICH REF0/FSLC/TEST_SEL SRCT4 CLK_PCIE_CRDP (24)
CPU_BSEL2 R94 10K/F_4 35
SRCC4 CLK_PCIE_CRDN (24)
116mA Swap pin define at 7/20 a-shian
CR#_E SRC_6
VCC3_CK505 4 47
+3.3V VDDREF SRCC6 CLK_PCIE_ICHN (8)
C299 0.1U/10V_4 9 48 CR#_F SRC_8
VDDPCI SRCT6 CLK_PCIE_ICHP (8)
C294 0.1U/10V_4 16
C305 C281 0.1U/10V_4 VDD48 CLK_PCIE_HDN SY3 --> Reserve for HD
23 VDD SRCC7/CR#_E 50 T12 CR#_G SRC_9
del R101 R196 by a-shian 9/18 10U/6.3V_8 C279 0.1U/10V_4 46 51 CLK_PCIE_HDP T13
C292 0.1U/10V_4 VDDSRC SRCT7/CR#_F
62 VDDCPU CR#_H SRC_10
C286 0.1U/10V_4 37
SRCT9 CLK_PCIE_MINIP (18)
SRCC9 38 CLK_PCIE_MININ (18)
VCCP_CK505 19 41
VCCP VDD96_IO SRCT10 CLK_PCIE_LANP (21)
C300 0.1U/10V_4 27 42
VDDPLL3_IO SRCC10 CLK_PCIE_LANN (21)
C301 0.1U/10V_4 33
C269 C287 0.1U/10V_4 VDDSRC_IO PCIE_REQ_MINI#_R R210 475/F_4
43 VDDSRC_IO SRCC11/CR#_G 39 PCIE_REQ_MINI# (18)
10U/6.3V_8 C277 0.1U/10V_4 52 40 PCIE_REQ_LAN#_R R207 475/F_4
VDDSRC_IO SRCT11/CR#_H PCIE_REQ_LAN# (21)
C282 0.1U/10V_4 56
3 C280 0.1U/10V_4 VDDCPU_IO 3
SRCT2/SATAT 28 CLK_PCIE_SATAP (9)
29 CLK_PCIE_SATAN (9)
1C: change Debug clk to same with EC(for layout)
SRCC2/SATAC

8 PCLK_EC_R R91 22_4
PCI0/CR#_A PCLK_EC (22)
CLKUSB_48_R 10 R92 22_4
PCI1/CR#_B PCLK_MP (18)
11 TME
PCI2/TME
1 GNDREF PCI3 12
C102 10P/50V_4 15 13 27_SEL R89 10K_4
GNDPCI PCI4/27_Select PCLK_ICH_MP_R R82 33/F_4
18 GND48 PCI_F5/ITP_EN 14 PCLK_ICH (10) 27 Select
14M_ICH_R 22 PIN 20/21 PIN 24/25
GND
26 GND PIN13
30 GNDSRC Thermal PAD 65
C125 *10P/50V_4 36 GNDSRC
49 GNDSRC * 0 DOT_96 / DOT_96# LCDCLK / LCDCLK#
+3.3V 59 GNDCPU NC 55 1B: add R22 for request pin
+3.3V
1 SRC_0 / SRC_0# 27M / 27M_SS
PCIE_REQ_HD#_R R77 *10K_4
R100 SLG8SP513VTR/ICS9LPRS365 PCIE_REQ_MINI#_R R209 10K_4
8.2K_4 PCIE_REQ_LAN#_R R206 10K_4
TME R208 10K_4
PCIE_REQ_CARD#_R R75 10K_4
CLKEN ITP_EN(PIN14) PIN53/54
CLKEN (11)
PCLK_ICH_MP_R R88 10K_4
3




add at 7/20 a-shian * 0 SRC8#/SRC8
1 ITP/ITP#
(27) VR_PW RGD_CK410# 2
2 Q20 2
Need to confirm with Tony that
2N7002E
R233 it is else pull high or down - ALF
100K_4
1




CPU_BSEL0
CPU_BSEL0 (4)
CPU_BSEL1
CPU_BSEL1 (4)
CPU_BSEL2
CPU_BSEL2 (4)
FSC FSB FSA Spread
BSEL2 BSEL1 BSEL0 CPU SRC PCI REF USB DOT % R78 R231 R93
*0_4 *0_4 0_4
0 0 0 266.66 100 33.33 14.318 48 96 0.5 Down
0 0 1 133.33 100 33.33 14.318 48 96 0.5 Down
0 1 0 200.00 100 33.33 14.318 48 96 0.5 Down
0 1 1 166.66 100 33.33 14.318 48 96 0.5 Down
1 0 0 333.33 100 33.33 14.318 48 96 0.5 Down
1 0 1 100.00 100 33.33 14.318 48 96 0.5 Down
1 1 0 400.00 100 33.33 14.318 48 96 0.5 Down
1 1 1 RESERVED




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1 1




Quanta Computer Inc.
PROJECT : FL2
Size Document Number Rev
1A
Clock Gen SLG8SP513VTR
Date: Thursday, November 05, 2009 Sheet 3 of 36
A B C D E
5 4 3 2 1




04
?
PINEVIEW_M
U16C
?
U16D PINEVIEW_M
D12 REV = 1.1
XDP_RSVD_00
A7 M30 VGA_HSYNC_R R183 10/F_4
VGA_HSYNC (15)
XDP_RSVD_01 CRT_HSYNC R182 10/F_4
D6 M29 VGA_VSYNC_R VGA_VSYNC (15) REV = 1.1
XDP_RSVD_02 CRT_VSYNC
C5 XDP_RSVD_03 (16) INT_TXLCLKN U25 LVD_A_CLKM SMI_B E7 H_SMI# (9)
C7 XDP_RSVD_04 (16) INT_TXLCLKP U26 LVD_A_CLKP A20M_B H7 H_A20M# (9)
T19 VGA_RED




VGA
C6 N31 VGA_RED (15) (16) INT_TXLOUTN0 R23 H6 H_FERR# (9)
PDC 4/24 XDP_RSVD_05 CRT_RED VGA_GRE LVD_A_DATAM_0 FERR_B
D8 P30 VGA_GRE (15) (16) INT_TXLOUTP0 R24 F10 H_INTR (9)
XDP_RSVD_06 CRT_GREEN LVD_A_DATAP_0 LINT00




ICH
B7 P29 VGA_BLU N26 F11
XDP_RSVD_07 CRT_BLUE VGA_BLU (15) (16) INT_TXLOUTN1 LVD_A_DATAM_1 LINT10 H_NMI (9)
A9 N30 (16) INT_TXLOUTP1 N27 E5 H_IGNNE# (9)
R162 1K/F_4 D9 XDP_RSVD_08 CRT_IRTN VGA_RED R185 150/F_4 LVD_A_DATAP_1 IGNNE_B
(16) INT_TXLOUTN2 R26 F8 H_STPCLK# (9)
XDP_RSVD_09 VGA_GRE R190 150/F_4 LVD_A_DATAM_2 STPCLK_B
C8 (16) INT_TXLOUTP2 R27
T21 XDP_RSVD_10 VGA_BLU R187 150/F_4 LVD_A_DATAP_2
D B8 D
XDP_RSVD_11
C10 L31 VGA_DDC_DAT (15) G6 ICH_DPRSTP# (11,27)
XDP_RSVD_12 CRT_DDC_DATA R66 2.37K/F_4 LIBG DPRSTP_B
D10 XDP_RSVD_13 CRT_DDC_CLK L30 VGA_DDC_CLK (15) R22 LVD_IBG DPSLP_B G10 H_DPSLP# (11)




LVDS
B11 XDP_RSVD_14 J28 LVD_VBG INIT_B G8 H_INIT# (9)
B10 XDP_RSVD_15 DAC_IREF P28 VGA_IREF R65 665/F_4 N22 LVD_VREFH PRDY_B E11
B12 XDP_RSVD_16 N23 LVD_VREFL PREQ_B F15 H_PREQ#
T20 C11 Y30 L27
XDP_RSVD_17 DPL_REFCLKINP DREFCLKP (3) (16) L_BKLT_EN LBKLT_EN
DPL_REFCLKINN Y29 DREFCLKN (3) (16) L_BKLTCTL L26 LBKLT_CTL
AA30 LCTLA_CLK L23 E13
DPL_REFSSCLKINP DREFSSCLKP (3) LCTLA_CLK THERMTRIP_B H_THERMTRIP# (9)
AA31 LCTLB_DATA K25
DPL_REFSSCLKINN DREFSSCLKN (3) LCTLB_CLK
LVDS_CLK K23
(16) LVDS_CLK LDDC_CLK
L11 LVDS_DATA K24
RSVD (16) LVDS_DATA LDDC_DATA
(16) L_VDD_EN H26 LVDD_EN
PROCHOT_B C18 H_PROCHOT_1#
W1 H_PWRGD H_PWRGD (11)
CPUPWRGOOD
K29 R188 0_4
PM_DPRSLPVR (11,27)
PM_EXTTS#_1/DPRSLPVR
J30 R45 10K/F_4
+3.3V
PM_EXTTS#_0
L5 IMVP_PWRGD (11,16,27)
PWROK H_GTLREF
AA3 PLT_RST# (11,18,21,24) A13
RSTINB GTLREF
+3.3V H27
MISC




VSS
W8 HCLK_MCHN (3)
HPL_CLKINN LCTLA_CLK R54 *2.2K/F_4
W9 HCLK_MCHP (3)
HPL_CLKINP LCTLB_DATA R53 *2.2K/F_4 L6
LVDS_CLK R160 2.2K/F_4 RSVD
AA7 RSVD_TP RSVD E17
AA6 LVDS_DATA R161 2.2K/F_4 G11
RSVD_TP BPM_1B_0
R5 E15 H10 HCLK_CPUN (3)
RSVD_TP BPM_1B_1 BCLKN
R6 G13 J10 HCLK_CPUP (3)
RSVD_TP BPM_1B_2 BCLKP
F13
BPM_1B_3 CPU_BSEL0




CPU
AA21 K5 CPU_BSEL0 (3)
RSVD_TP