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1 2 3 4 5 6 7 8
CPU CORE
MAXIM
VCC_CORE ZR3 X'TAL
MAX8774 Page:28 14.31818MHz
AMD S1
+1.2V Turion 64 Rev.F Dual-Core/
DDR-II SODIMM1 DDR-II 533/667MHz CPU THERMAL
A +1.2V +1.8VSUS Page: 7 Sempron Rev.F Single-Core A
Dual-Core 35W / Single-Core 25W SENSOR Clock generator
+1.8VSUS/+1.8V Page:5
+1.8V (638 S1g1 socket)
+0.9V_VTER DDR-II SODIMM2 Page:3, 4, 5, 6
ICS951462
TI +0.9V_VTER Page: 7
Page:12
TPS51116/51117
Page:29 HT_LINK
+3VPCU
+3VPCU/+5VPCU +3V_S5
+3VSUS
TV-OUT NB
+3V_S5 S-Video RGB CRT
+3V Page: 21 Page: 21
+3V/+5V ATi RS485
+5VPCU
+3VSUS/+5VSUS +5VSUS PCIE 465-Pins FCBGA Package LVDS
TI mini CARD LVDS
+5V Page: 21
TPS51120 Page: 20 Page: 8, 9 ,10, 11
Page:30
B B
+1.5V
+1.5V/+2.5V Manufacturing Option
+2.5V
2X PCIE
GMT REALTEK 8100SBL/CL
SATA HDD
G966/913-C Page:31
Page: 22
10/100 LAN
SATA RTC TRANSFORMER
SB AD18
Page: 17
BATTERY CHARGER Page: 14 REQ0# / GNT0#
MAXIM PATA HDD ATA 66/100 INTE# Page: 17
ATi SB460
ISL6251 Page: 22
Page:27 BATTERY RJ45
549-Pins BGA Package Page: 17
IDE-ODD PCI BUS 33MHZ ENE CB714/1410
Page: 22 Cardbus controller
Page: 13, 14, 15, 16
Azalia USB 2.0 PCMCIA
AD17
SLOT
Power State Table REQ3# / GNT3#
Page: 19
C Power Control Power INTH#,INTG# C
Name Signal State
MIC-IN X'TAL LPC 33MHZ Page: 18
CARD
+VCC_CORE VRON S0 Page: 24 AUDIO CODEC 32.768KHz READER
REALTEK- ALC883 Page: 19
+2.5V MAINON S0 48-pins Package KBC BIOS MINI-PCI
LINE-IN Page: 23
MODEM SST39VF080
+3VPCU N/A ALWAYS FOXCONN MDC NS PC97541V Wireless LAN
+3VS5 S5_ON S0-S5 Page: 24 176-Pins Package Page: 25 AD20
+3VSUS SUSD S0-S3 Page: 23 REQ2# / GNT2#
Audio AMP Audio AMP Page: 25 Bluetooth
+3V MAIND S0 INTG#,
MAX4411 MAX9710 USB
+5VPCU N/A ALWAYS INTE#
interface Page: 20
+5VSUS SUSD S0-S3 Page: 23 Page: 24 Page:20
+5V MAIND S0 USB6
SYSTEM
+1.2V MAINON S0 USB PORT*3
LINEOUT SPEAKER RJ11 Touchpad Keyboard FAN
+0.9V_VTER MAINON S0 Page: 20
D
Page: 24 Page: 24
(External) Page: 26 Page: 26 Page: 26 D
+1.8VS5 S5_ON S0-S5 USB0,1,4
+1.8VSUS SUSON S0-S3
+1.8V MAIND S0 USB CAMERA PROJECT : ZR3
+1.5V MAINON S0 Page: 20 Quanta Computer Inc.
USB2 Size Document Number Rev
BLOCK DIAGRAM 1A
Date: Wednesday, October 18, 2006 Sheet 1 of 31
1 2 3 4 5 6 7 8
5 4 3 2 1
POWER VOLTAGE ACTIVE SCOPE PAGE
TABLE OF CONTENTS POWER UP SEQUENCE
+12V +12V S0
+5VPCU
Page 01 : BLOCK DIAGRAM +5V +5V S0
Page 02 : TABLE OF CONTENTS +3V +3.3V S0 RSMRST#
Page 03 : ATHLON64 HT I/F +5VPCU +5V ALWAYS
SYSTEM
SUSB#, SUSC#
D Page 04 : ATHLON64 DDRII MEMORY I/F +3VPCU +3.3V ALWAYS
D
Page 05 : ATHLON64 CTRL & DEBUG +5VSUS +5V S0-S3 +12V,5V,3.3V
Page 06 : ATHLON64 PWR & GND +3VSUS +3.3V S0-S3
HWPG_1.2V
Page 07 : DDRII SODIMMX2 +3V_S5 +3.3V S0
Page 08 : RS485-HT LINK0 I/F HWPG_1.8V
Page 09 : RS485-PCIE LINK I/F VCCCORE VID[0..5] S0
VDDA_RUN +2.5V S0 CPU_COREPG
Page 10 : RS485-SYSTEM I/F & DVO
+1.2V S0
CPU
VLDT_RUN
Page 11 : RS485-POWER NB_PWRGD
Page 12 : External CLOCK GENERATOR +0.9V_VTER +0.9V S0
+1.8V +1.8V S0 EC_PWRGD
Page 13 : SB460M PCIE/PCI/CPU/LPC I/F
Page 14 : SB460M ACPI/GPIO/USB/AC97 +1.8VSUS +1.8V S0-S3
CPU_PWRGD
Page 15 : SB460M HDD/POWER/DECOUPLING +1.8V +1.8V S0
DDR2
PCI_RST#
Page 16 : SB460M STRAPS +1.8VSUS +1.8V S0-S3
Page 17 : LAN RTL8110SBL/CL +0.9V_VTER +0.9V S0 CPU_RST#
Page 18 : ENE CB714/1410
C Page 19 : CARD READ & CARDBUS SLOT +1.8V +1.8V S0 T1 T2 T3 C
Page 20 : MINI PCI & PCI-E,USB PORT,BLUETOOTH +1.8VSUS +1.8V S0-S3
Page 21 : CRT & LVDS & S-Video +3V +3.3V S0 T1>= 70 ms 1ms < T2 < 10ms
1ms < T3 < 5ms
Page 22 : HDD & CDROM & HOLES VDDC +1.2V S0
Page 23 : ALC883 & MDC & HP AMP VDD_HT +1.2V S0
RC485 NB
Page 24 : SPEAKER AMP / JACK VDDA12 +1.2V S0
Page 25 : 97551 & FLASH VDD18 +1.8V S0
Page 26 : T/P,FAN,SWITCH,LED,K/B VDDA18 +1.8V S0
Page 27 : BATTERY CHARGER VDD_DVO +1.8V S0
Page 28 : VCORE MAX8774 VDDR3 +3.3V S0
Page 29 : TPS51116/51117 1.8V/1.2V AVDD_NB +3.3V S0
Page 30 : TPS51120 3/5V AVDDQ +1.8V S0
Page 31 : +1.5V / 2.5V PLLVDD +1.8V S0
LPVDD +1.8V S0
LPVDD18A +1.8V S0
+3.3V S0
B B
+3V
+1.8V +1.8V S0
+3V_S5 +3.3V S0
+1.8V_S5 +1.8V S0
VDD +1.8V S0
AVDD_CK +1.8V S0
AVDD_SATA +1.8V S0
+1.8V S0
SB460 SB
XTLVDD_ATA
PLLVDD_ATA +1.8V S0
PCIE_PVDD +1.8V S0
PCIE_VDDR +1.8V S0
CPU-PWR +1.2V S0
VDDQ +3.3V S0
V5_VREF +5V S0
+1.8V_SUB_PHY +1.8V S0
+3.3V S0-S3
A A
+3VSUS
+SB_S5_3V +3.3V S0
+SB_S5_1.8V +1.8V S0
PROJECT : ZR3
Quanta Computer Inc.
Size Document Number Rev
TABLE OF CONTENTS 1A
Date: Wednesday, October 18, 2006 Sheet 2 of 31
5 4 3 2 1
5 4 3 2 1
D PROCESSOR HYPERTRANSPORT INTERFACE D
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
VLDT_RUN U16A
D4 VLDT_A3 VLDT_B3 AE5
D3 AE4 C21 4.7U/6.3V_6
VLDT_A2 VLDT_B2
D2 VLDT_A1 VLDT_B1 AE3
D1 VLDT_A0 VLDT_B0 AE2
(8) HT_CADIN15_P N5 L0_CADIN_H15 L0_CADOUT_H15 T4 HT_CADOUT15_P (8)
P5 L0_CADIN_L15 L0_CADOUT_L15 T3 HT_CADOUT15_N (8)
(8) HT_CADIN15_N
(8) HT_CADIN14_P M3 L0_CADIN_H14 L0_CADOUT_H14 V5 HT_CADOUT14_P (8)
M4 U5 +1.2V VLDT_RUN
(8) HT_CADIN14_N L0_CADIN_L14 L0_CADOUT_L14 HT_CADOUT14_N (8)
L5 V4 HT_CADOUT13_P (8) L45
(8) HT_CADIN13_P L0_CADIN_H13 L0_CADOUT_H13
(8) HT_CADIN13_N M5 L0_CADIN_L13 L0_CADOUT_L13 V3 HT_CADOUT13_N (8)
K3 Y5 FBJ3216HS800
C (8) HT_CADIN12_P L0_CADIN_H12 L0_CADOUT_H12 HT_CADOUT12_P (8) C
(8) HT_CADIN12_N K4 L0_CADIN_L12 L0_CADOUT_L12 W5 HT_CADOUT12_N (8)
H3 AB5 L47 8/17 Change 180pF to placed on the VLDT power fill.
(8) HT_CADIN11_P L0_CADIN_H11 L0_CADOUT_H11 HT_CADOUT11_P (8)
(8) HT_CADIN11_N H4 L0_CADIN_L11 L0_CADOUT_L11 AA5 HT_CADOUT11_N (8)
G5 AB4 FBJ3216HS800
(8) HT_CADIN10_P
H5
L0_CADIN_H10 L0_CADOUT_H10
AB3
HT_CADOUT10_P (8) 80 ohm(4A)
(8) HT_CADIN10_N L0_CADIN_L10 L0_CADOUT_L10 HT_CADOUT10_N (8)
(8) HT_CADIN9_P F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 HT_CADOUT9_P (8)
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5 HT_CADOUT9_N (8)
1
1
(8) HT_CADIN9_N
(8) HT_CADIN8_P E5 L0_CADIN_H8 L0_CADOUT_H8 AD4 HT_CADOUT8_P (8)
F5 AD3 C123 C116 C129 C128 C135 C134
(8) HT_CADIN8_N L0_CADIN_L8 L0_CADOUT_L8 HT_CADOUT8_N (8)
N3 T1 4.7U/6.3V_6 4.7U/6.3V_6 .22U/6V_4 .22U/6V_4 180P_4 180P_4
2
2
(8) HT_CADIN7_P L0_CADIN_H7 L0_CADOUT_H7 HT_CADOUT7_P (8)
(8) HT_CADIN7_N N2 L0_CADIN_L7 L0_CADOUT_L7 R1 HT_CADOUT7_N (8)
L1 L0_CADIN_H6 L0_CADOUT_H6 U2 HT_CADOUT6_P (8)
(8) HT_CADIN6_P
(8) HT_CADIN6_N M1 L0_CADIN_L6 L0_CADOUT_L6 U3 HT_CADOUT6_N (8)
(8) HT_CADIN5_P L3 L0_CADIN_H5 L0_CADOUT_H5 V1 HT_CADOUT5_P (8)
L2 L0_CADIN_L5 L0_CADOUT_L5 U1 HT_CADOUT5_N (8)
(8) HT_CADIN5_N
J1 W2
(8) HT_CADIN4_P
K1
L0_CADIN_H4 L0_CADOUT_H4
W3
HT_CADOUT4_P (8) LAYOUT: Place bypass cap on topside of board
(8) HT_CADIN4_N L0_CADIN_L4 L0_CADOUT_L4 HT_CADOUT4_N (8)
(8) HT_CADIN3_P G1 L0_CADIN_H3 L0_CADOUT_H3 AA2 HT_CADOUT3_P (8) NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
(8) HT_CADIN3_N H1 L0_CADIN_L3 L0_CADOUT_L3 AA3 HT_CADOUT3_N (8) TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
(8) HT_CADIN2_P
G3 L0_CADIN_H2 L0_CADOUT_H2 AB1 HT_CADOUT2_P (8) TO OTHER HT POWER PINS
(8) HT_CADIN2_N G2 L0_CADIN_L2 L0_CADOUT_L2 AA1 HT_CADOUT2_N (8) PLACE CLOSE TO VLDT0 POWER PINS
E1 L0_CADIN_H1 L0_CADOUT_H1 AC2 HT_CADOUT1_P (8)
(8) HT_CADIN1_P
(8) HT_CADIN1_N F1 L0_CADIN_L1 L0_CADOUT_L1 AC3 HT_CADOUT1_N (8)
B
(8) HT_CADIN0_P E3 L0_CADIN_H0 L0_CADOUT_H0 AD1 HT_CADOUT0_P (8) B
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1 HT_CADOUT0_N (8)
(8) HT_CADIN0_N
J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 HT_CLKOUT1_P (8)
(8) HT_CLKIN1_P
(8) HT_CLKIN1_N K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 HT_CLKOUT1_N (8)
(8) HT_CLKIN0_P J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 HT_CLKOUT0_P (8)
VLDT_RUN J2 W1
(8) HT_CLKIN0_N L0_CLKIN_L0 L0_CLKOUT_L0 HT_CLKOUT0_N (8)
R22 49.9/F_4 HT_CTLIN1_P P3 T5 HT_CPU_CTLOUT1_P
L0_CTLIN_H1 L0_CTLOUT_H1 T7
HT_CTLIN1_N P4 R5 HT_CPU_CTLOUT1_N
49.9/F_4 L0_CTLIN_L1 L0_CTLOUT_L1 T11
R23
(8) HT_CTLIN0_P N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 HT_CTLOUT0_P (8)
P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 HT_CTLOUT0_N (8)
(8) HT_CTLIN0_N
Athlon 64 S1
Processor Socket
A A
PROJECT : ZR3
Quanta Computer Inc.
Size Document Number Rev
ATHLON64 HT I/F 1A
Date: Wednesday, October 18, 2006 Sheet 3 of 31
5 4 3 2 1
A B C D E
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
+1.8VSUS
Processor DDR2 Memory Interface
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
R268 M_B_DQ[0..63] U16C M_A_DQ[0..63]
(7) M_B_DQ[0..63] M_A_DQ[0..63] (7)
M_B_DQ63 AD11 AA12 M_A_DQ63
1K/F_4 M_B_DQ62 MB_DATA63 MA_DATA63 M_A_DQ62
AF11 MB_DATA62 MA_DATA62 AB12
M_B_DQ61 AF14 AA14 M_A_DQ61
M_B_DQ60 MB_DATA61 MA_DATA61 M_A_DQ60
AE14 MB_DATA60 MA_DATA60 AB14
CPU_M_VREF M_B_DQ59 Y11 W11 M_A_DQ59
M_B_DQ58 MB_DATA59 MA_DATA59 M_A_DQ58
4 AB11 MB_DATA58 MA_DATA58 Y12 4
M_B_DQ57 AC12 AD13 M_A_DQ57
M_B_DQ56 MB_DATA57 MA_DATA57 M_A_DQ56
AF13 MB_DATA56 MA_DATA56 AB13
C448 C447 R269 M_B_DQ55 AF15 AD15 M_A_DQ55
.1U_4 1000p/50V_4 M_B_DQ54 MB_DATA55 MA_DATA55 M_A_DQ54
1K/F_4 AF16 MB_DATA54 MA_DATA54 AB15
M_B_DQ53 AC18 AB17 M_A_DQ53
M_B_DQ52 MB_DATA53 MA_DATA53 M_A_DQ52
AF19 MB_DATA52 MA_DATA52 Y17
M_B_DQ51 AD14 Y14 M_A_DQ51
+1.8VSUS M_B_DQ50 MB_DATA51 MA_DATA51 M_A_DQ50
AC14 MB_DATA50 MA_DATA50 W14
+0.9V_VTER M_B_DQ49 AE18 W16 M_A_DQ49
M_B_DQ48 MB_DATA49 MA_DATA49 M_A_DQ48
AD18 AD17
1
U16B M_B_DQ47 MB_DATA48 MA_DATA48 M_A_DQ47
AD20 MB_DATA47 MA_DATA47 Y18
R274 M_B_DQ46 AC20 AD19 M_A_DQ46
M_B_DQ45 MB_DATA46 MA_DATA46 M_A_DQ45
W17 MEMVREF VTT1 D10 AF23 MB_DATA45 MA_DATA45 AD21
39.2F_4 C10 M_B_DQ44 AF24 AB21 M_A_DQ44
VTT_SENSE VTT2 M_B_DQ43 MB_DATA44 MA_DATA44 M_A_DQ43
T3 Y10 B10 AF20 AB18
2
VTT_SENSE VTT3 M_B_DQ42 MB_DATA43 MA_DATA43 M_A_DQ42
VTT4 AD10 AE20 MB_DATA42 MA_DATA42 AA18
W10 M_B_DQ41 AD22 AA20 M_A_DQ41
M_ZN VTT5 M_B_DQ40 MB_DATA41 MA_DATA41 M_A_DQ40
AE10 MEMZN VTT6 AC10 AC22 MB_DATA40 MA_DATA40 Y20
M_ZP AF10 AB10 M_B_DQ39 AE25 AA22 M_A_DQ39
MEMZP VTT7 M_B_DQ38 MB_DATA39 MA_DATA39 M_A_DQ38
VTT8 AA10 AD26 MB_DATA38 MA_DATA38 Y22
A10 M_B_DQ37 AA25 W21 M_A_DQ37
VTT9 MB_DATA37 MA_DATA37
1
M_B_DQ36 AA26 W22 M_A_DQ36
R273 M_B_DQ35 MB_DATA36 MA_DATA36 M_A_DQ35
(7) M_A_CS#3 V19 MA0_CS_L3 MA0_CLK_H2 Y16 M_CLKOUT1 (7) AE24 MB_DATA35 MA_DATA35 AA21
J22 AA16 M_B_DQ34 AD24 AB22 M_A_DQ34
(7) M_A_CS#2 MA0_CS_L2 MA0_CLK_L2 M_CLKOUT1# (7) MB_DATA34 MA_DATA34
39.2F_4 V22 E16 M_B_DQ33 AA23 AB24 M_A_DQ33
(7) M_A_CS#1 MA0_CS_L1 MA0_CLK_H1 M_CLKOUT0 (7) MB_DATA33 MA_DATA33
T19 F16 M_B_DQ32 AA24 Y24 M_A_DQ32
2
(7) M_A_CS#0 MA0_CS_L0 MA0_CLK_L1 M_CLKOUT0# (7) MB_DATA32 MA_DATA32
M_B_DQ31 G24 H22 M_A_DQ31
M_B_DQ30 MB_DATA31 MA_DATA31 M_A_DQ30
(7) M_B_CS#3 Y26 MB0_CS_L3 MB0_CLK_H2 AF18 M_CLKOUT4 (7) G23 MB_DATA30 MA_DATA30 H20
J24 AF17 M_B_DQ29 D26 E22 M_A_DQ29
(7) M_B_CS#2 MB0_CS_L2 MB0_CLK_L2 M_CLKOUT4# (7) MB_DATA29 MA_DATA29
W24 A17 M_B_DQ28 C26 E21 M_A_DQ28
To SODIMM socket A (near)
(7) M_B_CS#1 MB0_CS_L1 MB0_CLK_H1 M_CLKOUT3 (7) MB_DATA28 MA_DATA28
U23 A18 M_B_DQ27 G26 J19 M_A_DQ27
To SODIMM socket B (Far)
(7) M_B_CS#0 MB0_CS_L0 MB0_CLK_L1 M_CLKOUT3# (7) M_B_DQ26 MB_DATA27 MA_DATA27 M_A_DQ26
G25 MB_DATA26 MA_DATA26 H24
H26 W23 M_B_DQ25 E24 F22 M_A_DQ25
(7) M_CKE3 MB_CKE1 MB0_ODT1 M_ODT3 (7) M_B_DQ24 MB_DATA25 MA_DATA25 M_A_DQ24
(7) M_CKE2 J23 MB_CKE0 MB0_ODT0 W26 M_ODT2 (7) E23 MB_DATA24 MA_DATA24 F20
3 PLACE THEM CLOSE TO J20 V20 M_B_DQ23 C24 C23 M_A_DQ23 3
(7) M_CKE1 MA_CKE1 MA0_ODT1 M_ODT1 (7) MB_DATA23 MA_DATA23
J21 U19 M_B_DQ22 B24 B22 M_A_DQ22
CPU WITHIN 1" (7) M_CKE0 MA_CKE0 MA0_ODT0 M_ODT0 (7)
M_B_DQ21 MB_DATA22 MA_DATA22 M_A_DQ21
(7) M_A_A[0..15] M_B_A[0..15] (7) C20 MB_DATA21 MA_DATA21 F18
M_A_A15 K19 J25 M_B_A15 M_B_DQ20 B20 E18 M_A_DQ20
M_A_A14 MA_ADD15 MB_ADD15 M_B_A14 M_B_DQ19 MB_DATA20 MA_DATA20 M_A_DQ19
K20 MA_ADD14 MB_ADD14 J26 C25 MB_DATA19 MA_DATA19 E20
M_A_A13 V24 W25 M_B_A13 M_B_DQ18 D24 D22 M_A_DQ18
M_A_A12 MA_ADD13 MB_ADD13 M_B_A12