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A B C D E
1 1
Compal Confidential
2
Schematics Document 2
INTEL AUBURNDALE with IBEX core logic
3
Cartier UMA 3
LA-4902P
2009-12-07
4
REV:1.0 4
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l.c
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Security Classification Compal Secret Data Compal Electronics, Inc.
tm
Issued Date 2008/09/15 2009/12/31 Title
ho
Deciphered Date
Cover Sheet
f@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
in
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom LA-4902P 0.3
xa
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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Date: Monday, December 14, 2009 Sheet 1 of 47
A B C D E
A B C D E
Compal Confidential
File Name : LA-4902P
Cartier UMA XDP Conn.
Page 4
Accelerometer
LIS302DLTR
Fan Control Mobile Page 26
Thermal Sensor Page 4
1
EMC2113 1
Page 4
CPU Dual Core DDR3 1066/1333MHz 1.5V DDR3-SO-DIMM X 2
BANK 0, 1, 2, 3 Page 9,10
eDP
DP Panel Socket-rPGA989 Dual Channel
Page 20
37.5mm*37.5mm
Page 4,5,6,7,8
VGA
Page 18 CK505
DP-D FDI DMI X4 Clock Generator
Display Port ICS9LPRS397
Page 19
DP X 2(Docking)
Page 28
USB2.0 Page 11
DP-C ; DP-B
USB x2(Docking)Page 28
2
Express Card 54 WWAN Card 2
PCIE X1 + USB X1 PCIE X1 USB2.0 FingerPrinter VFM451 daughter board
Audio Board Page 24
Intel Ibex Peak M USBx1 Page 31
Azalia
USB conn x 3(For I/O)
1071pins BT Conn USB x 1Page 26
25mm*27mm SATA0
PCI-E BUS
USB x1(Camara)
10/100/1000 LAN WLAN Card Rico R5C835 SATA1
Page 20
WLAN + PCIE X1 PCI BUS
Page 12,13,14,15,16,17
Intel Hansville GbE
PHY Controller MDC V1.5 RJ11
Page 21 Page 23 ONFI Interface Page 25 Page 25
Page 27
TPA6047A Audio Board
Braidwood Audio CKT
IDT 92HD75 AMP & Audio Jack
Page 24 Audio Board
RJ45 CONN
3
1394 port Smart Card SD/MMC Slot 3
Page 22 Page 27 Audio Board
SATA ODD Connector
Page 12 Page 36
Docking CONN.
NAND Flash Card (2) PS/2 Interfaces
Page 24
2.5" SATA HDD Connector (2) USB 2.channels
LPC BUS Page 12 (2) SATA Channels
(2) Display Port Channels
RTC CKT. (1) Serial Port
LED (1) Parallel Port
Page 12 Audio Board (1) Line In
(1) Line Out
(1) RJ45 (10/100/1000)
TPM1.2 SMSC Super I/O (1) VGA
Power OK CKT. SMSC KBC 1098 (1) 2 LAN indicator LED's
Page 32
SLB9635TT SMCS47N217N
Page 30 (1) Power Button
Page 31 page 29 (1) I2C interface
C OM1 LPT
4
Power On/Off CKT. Touch Pad CONN. Int.KBD ( Docking ) ( Docking )
4
Page 25 Page 30 Page 30
Page 25 Page 25
TrackPoint CONN.
Page 25
Security Classification Compal Secret Data Compal Electronics, Inc.
2008/09/15 2009/12/31 Title
DC/DC Interface CKT. Issued Date Deciphered Date
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Page 33 SPI ROM AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document Number
Custom LA-4902P
Rev
0.3
8 MB Page 31 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 09, 2009 Sheet 2 of 47
A B C D E
A
( O MEANS ON X MEANS OFF )
Voltage Rails Symbol Note :
+RTCVCC +B +5VALW +3VM +1.5V +5VS
+3VL +3VALW +1.05VM +0.75V +3VS
+1.5VS
: means Digital Ground
power
plane +VCCP
+CPU_CORE
+1.05VS : means Analog Ground
+1.8VS
State @ : means just reserve , no build
CONN@ : means ME part.
S0
O O O O O O Install below 45 level BOM structure for ver. 0.1
S1 45@ : means just put it in the BOM of 45 level.
O O O O O O
S3
O O O O O X
S5 S4/AC
O O O O X X
S5 S4/ Battery only
O O X X X X Install below 43 level BOM structure for ver. 0.1
S5 S4/AC & Battery
don't exist
O X X X X X DEBUG@ : means just build when PCIE port 80 CARD function enable. Remove before MP
1 1
N10M@ : Install for N10M Graphic controller
1098@ : Install for 1098 KBC controller
SMBUS Control Table Reserve below BOM structure for ver. 0.1
THERMAL 1091@ : Install for 1091 KBC controller
SOURCE BATT XDP SODIMM CLK CHIP MINI CARD DOCK NIC SENSOR G-SENSOR
SMB_EC_CK1
SMB_EC_DA1
SMSC1098 V X X X X X X X X
SMBCLK
SMBDATA
Calpella X V V V V V X X V
SML0CLK
SML0DATA
Calpella X X X X X X V X X
SML1CLK
SML1DATA
Calpella X X X X X X X V V
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l.c
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Compal Secret Data Compal Electronics, Inc.
tm
Security Classification
ho
Issued Date 2008/09/15 Deciphered Date 2009/12/31 Title
f@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
in
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
xa
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4902P 0.3
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 09, 2009 Sheet 3 of 47
A
1 2 3 4 5
Layout rule10mil width trace +VCCP
length < 0.5", spacing 20mil PM_EXTTS#0 1 2
JCPU1B R1 10K_0402_5%
20_0402_1% 1 R2 2COMP3 AT23 PM_EXTTS#1 1 2
COMP3 CLK_CPU_BCLK R3 10K_0402_5%
BCLK A16 CLK_CPU_BCLK 15
MISC
20_0402_1% 1 R5 2COMP2 AT24 B16 CLK_CPU_BCLK#
COMP2 BCLK# CLK_CPU_BCLK# 15 +VCCP
SI1 NO30
CLOCKS
49.9_0402_1% 1 R7 2COMP1 G16 AR30 CLK_CPU_XDP
COMP1 BCLK_ITP CLK_CPU_XDP# R14
BCLK_ITP# AT30
49.9_0402_1% 1 R9 2COMP0 AT26 COMP0
VDDPW RGOOD_R 1 2 1.5K_0402_1% VCCP_1.5VSPW RGD 32
XDP_TDO 1 2
E16 CLK_EXP R10 51_0402_5%
PEG_CLK CLK_EXP 13 This shall place near XDP
D16 CLK_EXP# 1 2 750_0402_1%
PEG_CLK# CLK_EXP# 13
TPC12 T1 TP_SKTOCC# AH24 R15
SKTOCC#
DPLL_REF_SSCLK A18 CLK_DP 13 09/07/02 HP
A A17 A
DPLL_REF_SSCLK# CLK_DP# 13
H_CATERR# AK14 CATERR# +1.5V
THERMAL
SM_DRAMRST# F6
2
15 H_PECI 1 R16 2 H_PECI_ISO AT15 PECI Q88
0_0402_5% AL1 SM_RCOMP0 R1133
SM_RCOMP[0] SM_RCOMP1 SSM3K7002F_SC59-3 1K_0402_5%
SM_RCOMP[1] AM1
to power; PU to VCCP at power side also AN1 SM_RCOMP2
SM_RCOMP[2]
S
D
41 H_PROCHOT# 1 R17 2 H_PROCHOT#_D AN26 3 1 DRAMRST# 9,10
1
0_0402_5% PROCHOT# PM_EXTTS#0
PM_EXT_TS#[0] AN15 T2 TPC12
DDR3
MISC
AP15 PM_EXTTS#1 1 2 from DDR
PM_EXT_TS#[1] PM_EXTTS#1_R 9,10
1
R18 0_0402_5%
G
PCH_DDR_RST 15
2
15 H_THERMTRIP# 1 R19 2 H_THERMTRIP#_R AK15 THERMTRIP#
R1989
0_0402_5% @ 100K_0402_5% 2 GPIO50 from PCH
AT28 XDP_PRDY# C1035
2
PRDY# XDP_PREQ# +VCCP
PREQ# AP27 0.1U_0402_16V4Z
1
AN28 XDP_TCK 10/09 HP S3 CPU Power Rail Change
TCK
2
H_CPURST# 1 R20 2 H_CPURST#_R AP26 AP28 XDP_TMS
RESET_OBS# TMS
PWR MANAGEMENT
0_0402_5% AT27 XDP_TRST# R846 @ 09/07/02 HP
TRST#
JTAG & BPM
1K_0402_5%
1 R21 2 H_PM_SYNC_R AL15 AT29 XDP_TDI
14 H_PM_SYNC
0_0402_5% PM_SYNC TDI
AR27 XDP_TDO CPU XDP Connector
1
TDO XDP_TDI_M PM_PWRBTN#_R
TDI_M AR29
H_CPUPW RGD 1 R22 2 SYS_AGENT_PWROK AN14 AP29 XDP_TDO_M JP1
0_0402_5% VCCPWRGOOD_1 TDO_M XDP_PREQ#
09/2/5 HP 1 GND0 GND1 2
AN25 XDP_DBRESET# XDP_PRDY# 3 4
DBR# OBSFN_A0 OBSFN_C0 CFG8 5
15 H_CPUPW RGD 1 R24 2 VCCPW RGOOD_0 AN27 VCCPWRGOOD_0
XDP_BPM#0 R1013 1 2 0_0402_5% 5 OBSFN_A1 OBSFN_C1 6 CFG9 5
0_0402_5% R1010 1 2@ 0_0402_5% 7 8
5 CFG12 GND2 GND3
AJ22 XDP_BPM#0 XDP_BPM#1 R1014 1 2 0_0402_5% XDP_BPM#0_R 9 10
B BPM#[0] OBSDATA_A0 OBSDATA_C0 CFG0 5 B
14 PM_DRAM_PWRGD 1 R26 2 VDDPW RGOOD_R AK13 SM_DRAMPWROK BPM#[1] AK22 XDP_BPM#1
5 CFG13
R1009 1 2 0_0402_5%
@ XDP_BPM#1_R 11 OBSDATA_A1 OBSDATA_C1 12 CFG1 5
0_0402_5% AK24 XDP_BPM#2 XDP_BPM#2 R1015 1 2 0_0402_5% 13 14
from power BPM#[2] XDP_BPM#3 R1011 GND4 GND5
BPM#[3] AJ24 5 CFG14 1 2 0_0402_5%
@ XDP_BPM#2_R 15 OBSDATA_A2 OBSDATA_C2 16 CFG2 5
32 VTTPWRGOOD AM15 AJ25 XDP_BPM#4 XDP_BPM#3 R1016 1 2 0_0402_5% XDP_BPM#3_R 17 18
VTTPWRGOOD BPM#[4] OBSDATA_A3 OBSDATA_C3 CFG3 5 HP 10/21
AH22 XDP_BPM#5 R1012 1 2 0_0402_5%
@ 19 20
BPM#[5] 5 CFG15 GND6 GND7 +3VS
AK23 XDP_BPM#6 21 22 SI1 NO3
BPM#[6] 5 CFG17 OBSFN_B0 OBSFN_D0 CFG10 5
H_PWRGD_XDP 1 R30 2 H_PW RGD_XDP_R AM26 AH23 XDP_BPM#7 23 24 09/3/9 HP
TAPPWRGOOD BPM#[7] 5 CFG16 OBSFN_B1 OBSFN_D1 CFG11 5
0_0402_5%