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A B C D E
1 1
2
Compal confidential 2
Schematics Document
Mobile Yonah uFCPGA with Intel
Calistoga_GM+ICH7-M core logic
3
2006-02-27 3
REV:0.5
Feb 27, 2007
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/27 Deciphered Date 2007/02/27 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3031P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 28, 2006 Sheet 1 of 49
A B C D E
A B C D E
Compal confidential
File Name : LA-3031
Heavenly 2.0
1 DOCK/DVI 1
Fan Control Mobile Yonah & Merom
page 34 page 4
Thermal Sensor Clock Generator
uFCPGA-478 CPU ADM1032AR ICS9LP306
page 4,5,6
page 4 page 15
FSB
H_A#(3..31) 533/667MHz H_D#(0..63)
DVI controller SDVO
CH7307C-DE Intel Calistoga GMCH DDR2 -400/533/667 DDR-SO-DIMM X2
page 17 BANK 0, 1, 2, 3 page 13,14
945GM
PCBGA 1466 Dual Channel
CRT/TV-OUT page 7,8,9,10,11,12
page 16 FingerPrinter
page 29
2 AES2501 2
USB2.0
LCD CONN USB conn x3
page 17 DMI page 29
PCI-E BUS BT Conn
page 29 MDC1.5
page 31
PCI BUS
Intel ICH7-M AC-LINK/Azalia Audio CKT AMP & Audio Jack
AD1981HD
page 27 page 28
Gigabit LAN mBGA-652
Mini Card CardBus Controller
BCM5753M socket page 18,19,20,21
page 24 page 26 TI PCI6612 SATA Master SATA HDD
3
page 22,23
SPI
Connector
page 19 3
Docking CONN.
SPI ROM
*RJ-45(LED*2)
RTC CKT. SD/SDIO Slot *RJ-11(Pass Through)
page 19
RJ45/11 CONN Slot 0 25LF080A
page 31 *CRT
page 25 page 23 page 22
*COMPOSITE Video Out
LPC BUS *TVOUT
*DVI
Power OK CKT. *LINE IN
page 36 *LINE OUT
*PCI-E x2
SMSC Super I/O SMSC KBC 1021 Security Module Flash ROM
*Serial Port
*Parallel Port
Power On/Off CKT. LPC47N217 30 *PS/2 x2
page 33
page page 32 page 31 SST49LF008A *USB x2
page 31
*DC JACK
COM1 on Touch Pad CONN. Int.KBD
4 DC/DC Interface CKT. Docking side page 33 4
page 30 page 33 page 34
page 35
LPT on FIR Digitizer
page 30
Power Circuit DC/DC Docking side page 17
Security Classification Compal Secret Data Compal Electronics, Inc.
page 30 Issued Date 2006/02/27 Deciphered Date 2007/02/27 Title
36,37,38,39,40,41,42,43 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3031P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 28, 2006 Sheet 2 of 49
A B C D E
A
Voltage Rails Symbol note:
Power Plane Description S0-S1 S3 S5 :means digital ground.
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit N/A N/A N/A :means analog ground.
+CPU_CORE Core voltage for CPU ON OFF OFF
+VCCP 1.05V power rail for Processor I/O and MCH core power ON OFF OFF
@ :means reserved.
+0.9VS 0.9V switched power rail for DDRII Vtt ON OFF OFF
+1.5VS 1.5V switched power rail for PCI-E interface ON OFF OFF
+1.8V 1.8V power rail for DDRII ON ON OFF
+2.5VALW 2.5V always on power rail ON ON ON*
@ : means just reserve , no build
+2.5VS 2.5V switched power rail for MCH video PLL ON OFF OFF
SPI@ : means just build when SPI I/F BIOS function enable.
+3VALW 3.3V always on power rail ON ON ON*
FWH@ : means just build when FWH I/F BIOS function enable.
+3V 3V power rail ON ON OFF
NOXDP@ : means just build when XDP function disable.
+3VS 3.3V switched power rail ON OFF OFF
XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
+5VALW 5V always on power rail ON ON ON*
TPM@ : means just build when TPM1.2 function enable.
+5V 5V power rail ON ON OFF
250@ : means just build when SMsC LPC47N250 chip selected.
+5VS 5V switched power rail ON OFF OFF
1021@ : means just build when SMsC KBC1021 chip selected.
RTCVCC RTC power ON ON ON
45@ : means need be mounted when 45 level assy or rework stage.
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
ACCEL@ : means just build when Accelerometer chip LIS3LV02DQ selected.
DVI_7307@ : means just build when DVI chip CH7307 selected.
DVI_1362@ : means just build when DVI chip SIL1362 selected.
1 Internal PCI Devices 1
DEVICE PCI Device ID IDSEL #
L AN D8 AD24
Azal ia D27 AD11
PCI-E D28 AD12
USB1.1/2.0 D29 AD13
PCI to PCI (DMI to PCI) D30 AD14
AC97 MODEM D30 AD14 (Disabled by BIOS)
AC97 Audio D30 AD14 (Disabled by BIOS)
PATA/SATA D31 AD15 (PATA is Disabled by BIOS)
LPC I/F D31 AD15
SMBUS D31 AD15
External PCI Devices
DEVICE PCI Device ID IDSEL # REQ/GNT # PIRQ
CARD BUS D6 AD22 2 CDEG
I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS
DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/27 Deciphered Date 2007/02/27 Title
CLOCK GENERATOR (EXT.) D2 11010010 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3031P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 28, 2006 Sheet 3 of 49
A
5 4 3 2 1
7 H_A#[3..31]
JP12A
H_D#[0..63] 7 ITP-XDP Connector +3VS
R549
H_A#3 J4 E22 H_D#0 XDP_DBRESET#_R 1 2 @ 1K_0402_5%
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2
JP19
+VCCP
M3 A5# D2# E26 1 GND0 GND1 2
H_A#6 K5 H22 H_D#3 XDP_BPM#5 3 4 This shall place near CPU
H_A#7 A6# D3# H_D#4 XDP_BPM#4 OBSFN_A0 OBSFN_C0 XDP_TDI R550 1 56_0402_5%
M1 A7# D4# F23 5 OBSFN_A1 OBSFN_C1 6 2
H_A#8 N2 G25 H_D#5 7 8
H_A#9 A8# D5# H_D#6 XDP_BPM#3 GND2 GND3 XDP_TMS R551 1 56_0402_1%
J1 A9# D6# E25 9 OBSDATA_A0 OBSDATA_C0 10 2
D H_A#10 H_D#7 XDP_BPM#2 D
N3 A10# D7# E23 11 OBSDATA_A1 OBSDATA_C1 12
H_A#11 P5 K24 H_D#8 13 14 XDP_BPM#5 R553 1 2 56_0402_5%
H_A#12 A11# D8# H_D#9 XDP_BPM#1 GND4 GND5
P2 A12# D9# G24 15 OBSDATA_A2 OBSDATA_C2 16
H_A#13 L1 J24 H_D#10 XDP_BPM#0 17 18 XDP_TRST# R554 1 2 56_0402_5%
H_A#14 A13# D10# H_D#11 OBSDATA_A3 OBSDATA_C3
P4 A14# D11# J23 19 GND6 GND7 20
H_A#15 P1 H26 H_D#12 21 22 XDP_TCK R555 1 2 56_0402_5%
H_A#16 A15# D12# H_D#13 OBSFN_B0 OBSFN_D0
R1 A16# D13# F26 23 OBSFN_B1 OBSFN_D1 24
H_A#17 Y2 K22 H_D#14 25 26
H_A#18 A17# D14# H_D#15 GND8 GND9
U5 A18# D15# H25 27 OBSDATA_B0 OBSDATA_D0 28
H_A#19 R3 N22 H_D#16 29 30 This shall place near JP19 +VCCP
H_A#20 A19# D16# H_D#17 OBSDATA_B1 OBSDATA_D1
W6 A20# D17# K25 31 GND10 GND11 32
H_A#21 U4 P26 H_D#18 33 34 XDP_TDO R552 1 2 56_0402_5%
H_A#22 A21# D18# H_D#19 OBSDATA_B2 OBSDATA_D2
Y5 A22# D19# R23 35 OBSDATA_B3 OBSDATA_D3 36
H_A#23 U2 L25 H_D#20 R556 37 38
H_A#24 A23# D20# H_D#21 H_PW RGOOD 2 GND12 GND13
R4 A24# D21# L22 1H_PWRGOOD_R 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40 CLK_CPU_XDP CLK_CPU_XDP 15
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22 1K_0402_5% 41 42 CLK_CPU_XDP# CLK_CPU_XDP# 15
H_A#26 A25# D22# H_D#23 HOOK1 ITPCLK#/HOOK5
T3 A26# D23# M23 +VCCP 43 VCC_OBS_AB VCC_OBS_CD 44 +VCCP 1K_0402_1%
H_A#27 W3 P25 H_D#24 2 1 45 46 H_RESET#_R 1 R557 2 H_RESET#
H_A#28 A27# D24# H_D#25 C590 0.1U_0402_16V4Z HOOK2 RESET#/HOOK6 XDP_DBRESET#_R 2 R558
W5 A28# D25# P22 47 HOOK3 DBR#/HOOK7 48 1 XDP_DBRESET#
H_A#29 Y4 P23 H_D#26 49 50 200_0402_1%
H_A#30 A29# D26# H_D#27 ICH_SMBDATA GND14 GND15 XDP_TDO
W2 A30# D27# T24 51 SDA TD0 52
H_A#31 Y1 R24 H_D#28 ICH_SMBCLK 53 54 XDP_TRST#
7 H_REQ#[0..4] A31# D28# SCL TRST#
L26 H_D#29 55 56 XDP_TDI
H_REQ#0 D29# H_D#30 XDP_TCK TCK1 TDI XDP_TMS
K3 REQ0# D30# T25 57 TCK0 TMS 58
H_REQ#1 H2 N24 H_D#31 59 60 XDP_PRE 1 R559
2
H_REQ#2 REQ1# D31# H_D#32 GND16 GND17 0_0402_5%
K2 REQ2# D32# AA23
H_REQ#3 J3 AB24 H_D#33 SAMTE_BSH-030-01-L-D-A
H_REQ#4 REQ3# D33# H_D#34
L5 REQ4# D34# V24
V26 H_D#35
H_ADSTB#0 D35# H_D#36
7 H_ADSTB#0 L2 ADSTB0# D36# W25
H_ADSTB#1 V4 U23 H_D#37
7 H_ADSTB#1 ADSTB1# D37#
U25 H_D#38
C D38# H_D#39 C
D39# U22
AB25 H_D#40
D40# H_D#41
W22
CLK_CPU_BCLK A22
D41#
D42# Y23
AA26
H_D#42
H_D#43
Thermal Sensor ADM1032
15 CLK_CPU_BCLK BCLK0 D43#
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44
15 CLK_CPU_BCLK# BCLK1 D44# H_D#45 +3VS
D45# Y22 9/2
AC26 H_D#46
D46# H_D#47
D47# AA24
H_ADS# H1 AC22 H_D#48 2
7 H_ADS# ADS# D48#
H_BNR# E2 AC23 H_D#49 C273
7 H_BNR# BNR# D49#
H_BPRI# G5 AB22 H_D#50
7 H_BPRI# BPRI# D50#
1
H_BR0# F1 AA21 H_D#51 0.1U_0402_16V4Z
7 H_BR0# BR0# D51# 1
H_DEFER# H5 AB21 H_D#52 R227
7 H_DEFER# DEFER# D52#
H_DRD Y# F21 AC25 H_D#53 U16 10K_0402_5%
7 H_DRDY# DRDY# D53#
R560 H_HIT# G6 AD20 H_D#54 1 8 ICH_SMBCLK
7 H_HIT# HIT# D54# VDD SCLK
56_0402_5% H_HITM# E4 CONTROL AE22 H_D#55
7 H_HITM#
2
H_IERR# HITM# D55# H_D#56 H_THERMDA ICH_SMBDATA
+VCCP 1 2 D20 IERR# D56# AF23 2 D+ SDATA 7
H_LOCK# H4 AD24 H_D#57 C264
7 H_LOCK# LOCK# D57#
H_RESET# B1 AE21 H_D#58 1 2 H_THERMDC 3 6 THERM_SCI#
7 H_RESET# RESET# D58# D- ALERT# THERM_SCI# 20
AD21 H_D#59
D59# H_D#60 2200P_0402_50V7K THERM#
7 H_RS#[0..2] D60# AE25 4 THERM# GND 5
H_RS#0 F3 AF25 H_D#61
H_RS#1 RS0# D61# H_D#62
F4 RS1# D62# AF22
H_RS#2 G3 AF26 H_D#63 +3VS 1 R228
2 ADM1032ARMZ-2REEL MSOP8
H_TRDY# RS2# D63# 10K_0402_5%
7 H_TRDY# G2 TRDY#
Address:1001_101
J26 H_DINV#0
DINV0# H_DINV#0 7
M26 H_DINV#1
DINV1# H_DINV#1 7
XDP_BPM#0 AD4 V23 H_DINV#2 13,14,15,20,24,26 ICH_SMBCLK ICH_SMBCLK
BPM0# DINV2# H_DINV#2 7
XDP_BPM#1 AD3 AC20 H_DINV#3 ICH_SMBDATA
BPM1# DINV3# H_DINV#3 7 13,14,15,20,24,26 ICH_SMBDATA
XDP_BPM#2 AD1
B XDP_BPM#3 BPM2# B
AC4 BPM3# H_DSTBN#[0..3] 7
H23 H_DSTBN#0
XDP_DBRESET# C20 DSTBN0# H_DSTBN#1
20 XDP_DBRESET# DBR# DSTBN1# M24
H_DBSY# E1 W24 H_DSTBN#2
7 H_DBSY# DBSY# DSTBN2#
H_DPSLP# B5 AD23 H_DSTBN#3
19 H_DPSLP# DPSLP# DSTBN3# H_DSTBP#[0..3] 7
H_DPRSTP# E5 G22 H_DSTBP#0
19,43 H_DPRSTP# DPRSTP# DSTBP0#
H_DPWR# D24 N25 H_DSTBP#1
7 H_DPWR# DPWR# DSTBP1#
XDP_BPM#4 AC2 MISC Y25 H_DSTBP#2
43 H_PROCHOT#
1 R561 2
XDP_BPM#5 AC1
H_PROCHOT# D21
PRDY#
PREQ#
DSTBP2#
DSTBP3# AE24 H_DSTBP#3 PWM Fan Control circuit
+VCCP 68_0402_5% PROCHOT# +5VS
19 H_PWRGOOD H_PW RGOOD D6
H_CPUSLP# PWRGOOD
7 H_CPUSLP# D7 SLP#
XDP_TCK AC5
XDP_TDI TCK H_A20M# JP8
AA6 TDI A20M# A6 H_A20M# 19 1 1 1
1
XDP_TDO AB3 A5 H_FERR# D11 C932 C125
TDO FERR# H_FERR# 19 1
R562 1 2 @ 1K_0402_5% TEST1 C26 C4 H_IGNNE#