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5 4 3 2 1
Model Name: 8I915P Dual Graphic
Rev:1.02
SHEET TITLE SHEET TITLE
D D
01 COVER SHEET 23 PCI SLOT
02 BLOCK DIAGRAM 24 PCIE X1 /PCIE SLI SLOT
03 BOM & PCB MODIFY HISTORY 25 ITE8712 LPC I/O
04 P4_LGA775_A 26 HWMO/FAN
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05 P4_LGA775_B 27 KB_MS/GAME
06 P4_LGA775_C 28 COM/LPT/FDD
C
07 P4_LGA775_D 29 (FRONT+REAR)USB/RING/IDE SATA LED C
08 VCORE POWER 30 AZALIA CODEC ALC880/CMI9880
09 GMCH-GRANTSDALE_HOST 31 AUDIO JACK
10 GMCH-GARNTSDALE_DDR 32 MARVELL 88E8001
11 GMCH-GRANTSDALE_PCI E, DMI 33 ATX,OTHERS POWER/DUAL BIOS
12 GMCH-GRANTSDALE_INT VGA 34 DISCRETE POWER
13 GMCH-GRANTSDALE_GND 35 TI TSB43AB23 1394
14 GMCH-GRANTSDALE_PWR 36 FRONT PANEL
B B
15 DDR CHANNEL A 37 RAID VIA 6410
16 DDR CHANNEL B 38 RAID IDE CONNECTOR
17 DDR TERMINATION 39 GPIO TABLE
18 PCI EXPRESS*16 SLOT 40 GPIO/RESET TABLE
19 ICH6 PCI, USB, DMI, LAN
20 ICH6 IDE, GPIO, SATA, CTRL
21 ICH6 PWR, GND
A
22 CLK_GEN/CK410M Digitally signed by dd A
DN: cn=dd, o=dd, ou=dd,
COMPONENT SIDE GIGABYTE
[email protected], c=US
(1 oz. Copper)
VCC SIDE
(1 oz. Copper)
Title
Date: 2009.11.15 20:33:53 8I915PDG
GND SIDE
Cover Sheet
(1 oz. Copper) Size Document Number Rev
SOLDER SIDE Custom
+07'00'
(1 oz. Copper)
1.02
Date: Tuesday, January 04, 2005 Sheet 1 of 40
5 4 3 2 1
5 4 3 2 1
BLOCK DIAGRAM
INTEL Pentium4
LGA775
D
CLOCK GENERATOR D
VID0~4
PWM/OTHER POWER
VCORE = 1.75V / SLEEP : 1.3V PAGE 4, 5, 6,7
VCC3 VCORE = 1.75V (650-1100MHZ) / SLEEP : 1.3V
CKVDD = 3.3V PAGE 22 5VSB,-12V,+12V,VCC,VCC3,3VDUAL
VTT_DDR,2_5VSTR PAGE 8,34,35
CHANNEL A
DDRII DIMM X 1
GMCH DDRI DIMM X 1
GAD0~31 2_5VSTR = 2.5V(MEMORY,SUSPEND POWER)
PAGE 15,17
ADSTB0,ADSTB0- GRANTSDALE MAA0~14 VTT_DDR = 1.25V
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ADSTB1,ADSTB1- MAA_CPC1~5
SBA0~7 MAB_CPC1~5
PCI EXPRESS SBSTB,SBSTB- MDD0~63 CHANNEL B
BY 16 PORTS -DQSD0~7 DDRII DIMM X 1
GCBE0~3- DDRI DIMM X 1
VCC3 = 3.3V
DM0~7
+12V = 12V
ST0~2
3VDUAL = 3.3V 2_5VSTR = 2.5V(MEMORY,SUSPEND POWER)
PAGE 18 VCORE = 1.75V / SLEEP : 1.3V VTT_DDR = 1.25V PAGE 16,17
2_5VSTR = 2.5V(MEMORY)
VDDQ = 1.5V (AGP POWER 4X, HUBLINK) PAGE 9,10,11,12,13,14
C C
PCI Express16(4Lane) HL0~10
Slot*1 CONTROL BUS HUB LINK
VCC3 = 3.3V
+12V = 12V
3VDUAL = 3.3V
PAGE 24 IDE Primary
ICH6R
VCC = 5V PAGE 29
USB PORTS 0~7 SERIAL ATA
VCC25 = 2.5V(I/O,MEMORY/I,VLINK/I)
Raid
VCC = 5V 3VDUAL = 3.3V(SUSPEND POWER)
5VSB = 5V VCC3 = 3.3V
5VUSB = 5V PAGE 29 RTCVDD = 3.3V VCC = 5V PAGE 20
PAGE 19,20,21
AZALIA
LINK PCI BUS
B FWH/HWMO B
PCI Slot*3
AC97/Azalia +12 = 12V
VCC = 5V
VCC3 = 3V PAGE 26
ALC880/CMI9880 -12 = -12V
VCC = 5V
VCC3 = 3V
+12V = 12V 3VDUAL = 3V PAGE 23,24
VCC3 = 3.3V
VCC = 5V
AVDD = 5V PAGE 30
LAN MARVELL LPC BUS
88E8001 LPC ITE8712HX
AUDIO PORTS : FRONT AUDIO PAGE 32,33
LIN_ OUT LINE_IN MIC VCC = 5V
5VSB = 5V
VBAT = 3V PAGE 25
TELE CD_IN AUX_IN
PAGE 31 1394 IT TSB43AB23
PAGE 36
A I/O PORTS : A
RAID VIA6410 COMA COMB LPT PS2 IR FDD
PAGE 27,28,29
FRONT PANEL/BZ
VCC = 5V PAGE 38,39 GIGABYTE
5VSB = 5V
+12 = 12V Title
PVCC = 5V PAGE 37 BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom 8I915PDG 1.02
Date: Tuesday, January 04, 2005 Sheet 2 of 40
5 4 3 2 1
5 4 3 2 1
Model Name: 8I915P Dual Graphic Circuit or PCB layout change
for next version
Version: 1.02
PAGE Change Item Reason
D D
Component value change history 2004/12/20
Data Change Item Reason
0.1 BOM
2004/11/19 First BOM release PCB 0.1
1.0A BOM
2004/12/10 PCB 1.01 E-BOM release (Q SW)
1.0B BOM
2004/12/16 PCB 1.01 P-BOM release (Q SW)
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1.0C BOM
2004/12/23 PCB 1.02 P-BOM release (DIP SW) DIP SW MP
1.0D BOM
2005/01/05 R1147 2.2/6==>4.7/6 Dual BIOS issue
C C
B B
A A
GIGABYTE
Title
BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom 8I915PDG 1.02
Date: Tuesday, January 04, 2005 Sheet 3 of 40
5 4 3 2 1
5 4 3 2 1
VCORE
BC1 BC4 BC5
10U/12/X/6.3V 10U/12/X/6.3V 10U/12/X/6.3V
D D
VCORE
BC6 BC7 BC8 BC9 BC10
10U/12/X/6.3V 10U/12/X/6.3V 10U/12/X/6.3V 10U/12/X/6.3V 10U/12/X/6.3V
U1A
HA[3..16]
[9] HA[3..16]
HA3 L5 D2 -HADS Closed to
A03# ADS# -HADS [9]
HA4 P6 C2 -BNR
A04# BNR# -BNR [9] Pin-H1
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HA5 M5 D4 -HIT
A05# HIT# -HIT [9]
HA6 L4 H4 R1
HA7 A06# RSP# -BPRI 49.9/6/1 GTLREF
M4 A07# BPRI# G8 -BPRI [9] VTT_OR
HA8 R4 B2 -DBSY
A08# DBSY# -DBSY [9]
HA9 T5 C1 -DRDY
A09# DRDY# -DRDY [9]
HA10 U6 E4 -HITM BC11 R2 C3
A10# HITM# -HITM [9]
HA11 -IERR 0.01U/6/X/50V 100/6/1 1U/6/Y/10V
HA12
T4
U5
A11# IERR# AB2
P3 -HINIT
*
A12# INIT# -HINIT [20]
HA13 U4 C3 -HLOCK
A13# LOCK# -HLOCK [9]
HA14 V5 E3 -HTRDY C2
A14# TRDY# -HTRDY [9]
HA15 V4 AD3 33P/4/N/50V
C HA16 A15# BINIT# -DEFER C
W5 A16# DEFER# G7 -DEFER [9]
N4 F2 -EDRDY
RSVD EDRDY# -EDRDY [9]
P5 RSVD MCERR# AB3
-HREQ0 K4
[9] -HREQ0 REQ0#
-HREQ1 J5 U2
[9] -HREQ1 REQ1# AP0# TP_CPU1
-HREQ2 M6 U3
[9] -HREQ2 REQ2# AP1# TP_CPU2
-HREQ3 K6
[9] -HREQ3 REQ3#
-HREQ4 J6 F3 -BR0
[9] -HREQ4 REQ4# BR0# -BR0 [9]
-HADSTB0 R6 G3 TESTHI8
[9] -HADSTB0 ADSTB0# TESTHI08 TESTHI8 [5]
-HPCREQ G5 G4 TESTHI9
[9] -HPCREQ PCREQ# TESTHI09 TESTHI9 [5]
HA[17..31] H5 TESTHI10
[9] HA[17..31] TESTHI10 TESTHI10 [5]
HA17 AB6
HA18 A17#
W6 A18# DP0# J16 TP_CPU3
HA19 C1
Y6 A19# DP1# H15 TP_CPU4
HA20 Y4 H16 220P/4/N/25V
A20# DP2# TP_CPU5
HA21 AA4 J17
A21# DP3# TP_CPU6
HA22 AD6 R1539 62/6/X -IERR
A22# VTT_OR
HA23 AA5 H1 GTLREF
HA24 A23# GTLREF
AB5 A24#
HA25 AC5 G23 -CPURST R6 62/6 -IERR
A25# RESET# -CPURST [9] VTT_OL
HA26 AB4
HA27 A26# -RS0
AF5 A27# RS0# B3 -RS0 [9]
HA28 AF4 F5 -RS1 C4 R7 62/6 -BR0
A28# RS1# -RS1 [9] VTT_OL
SP-CAP X 4PCS HA29
HA30
AG6
AG4
A29# RS2# A3 -RS2
-RS2 [9]
22P/4/N/50V
HA31 A30# R8 62/6 -CPURST
AG5 A31# VTT_OL
AH4 A32#
VCORE AH5 A33#
AJ5 A34#
AJ6 A35#
AC4 RSVD
B B
AE4
+
+
SEC1 SEC2 -HADSTB1 RSVD
[9] -HADSTB1 AD5 ADSTB1#
100U/4V/SPCAP/X
CPU-SK/775
100U/4V/SPCAP/X
VCORE
+
+
+
+
EC1 EC2 EC129 EC130
100U/4V/SPCAP/9m/X 100U/4V/SPCAP/9m/X
100U/4V/SPCAP/X 100U/4V/SPCAP/X CR
CPU RETAINTION/X
A A
GIGABYTE
Title
P4_LGA775-A
Size Document Number Rev
Custom 8I915PDG 1.02
Date: Tuesday, January 04, 2005 Sheet 4 of 40
5 4 3 2 1
5 4 3 2 1
VCC3
Note:
Place outside of CPU socket
VCCA & VCOREPLL R1538 R1593
249/6/1 49.9/6/1/X GTLREF1 R10 100/6/1 COMP2
define doesn't same as VTT_OR VTT_OL
R11 100/6/1 COMP3
3
VTT_GMCH 10UH/8/S old P4 design kit R23
L1 Q262 R1594 C1290 C5 R14 60.4/6/1 COMP0
VCCA D 110/6/1 100/6/1/X 1U/6/Y/10V/X 0.1U/6/Y/25V R15 60.4/6/1 COMP1
2N7002/S
G S
D C6 BC213 R17 SOT23 R1595 60.4/6/1/X COMP2 D
[7,9] GTL_DET
1U/6/Y/10V 4.7U/8/Y/10V 0/SHT/X TESTHI0 R1596 60.4/6/1/X COMP3
2
1
VSSA Trace width doesn't
R1224 C439
less than 12 Mil 61.9/6/1 0.1U/6/Y/25V
C7 BC214 RN103
L2 1U/6/Y/10V 4.7U/8/Y/10V 470/8P4R
VCOREPLL 7 8 FSBSEL0
VTT_GMCH
U1C 5 6 FSBSEL2
10UH/8/S As close as possible to 3 4 FSBSEL1
1 2
CPU socket -SMI P2 F26 TESTHI0
[20] -SMI SMI# TESTHI00
-A20M K3 W3 TESTHI1 R22 62/6 TESTHI2_7
[20] -A20M A20M# TESTHI01
-FERR R3 P1 TESTHI11
[20] -FERR FERR#/PBE# TESTHI11
INTR K1 W2 TESTHI12
[20] INTR LINT0 TESTHI12
NMI L1 F25
[20] NMI LINT1 TESTHI02
-IGNNE N2 G25 R24 62/6 -THRMTRIP
[20] -IGNNE IGNNE# TESTHI03
-STPCLK M3 G27 Locate at ICH6 Side
[20] -STPCLK STPCLK# TESTHI04
FSBSEL1 G26 R25 62/6 -FERR
TESTHI05
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VCCA A23 G24
VCC VSSA VCCA TESTHII06 TESTHI2_7
B23 VSSA TESTHI07 F24
3
D23 AK6 -FORCEPR
RSVD RSVD -FORCEPR [36]
Q278 VCOREPLL C23 G6 RSVD_G6
R1598 D VCCIOPLL RSVD R26 62/6/X RSVD_G6
VTT_OL
2N7002/S VID0 AM2 L2 -CPUSLP
8.2K/6 G S VID0 SLP# -CPUSLP [20]
VID[0..5] VID1 AL5 AH2 R27 62/6 TESTHI12
[8] VID[0..5] VID1 RSVD
VID2 AM3 N1 CPUPWROK
VTT_GMCH VID2 PWRGOOD CPUPWROK [20]
VID3 -PROCHOT R29 62/6 TESTHI1
2
1
AL6 VID3 PROCHOT# AL2 -PROCHOT [36]
VID4 AK4 M2 -THRMTRIP
VID4 THERMTRIP# -THRMTRIP [20]
3
VID5 AL4
C R1599 Q279 VID5 COMP0 C
AM5 RSVD COMP0 A13
MMBT2222A/S T1 COMP1 RN1047 8 TESTHI8
COMP1 TESTHI8 [4]
CPUCLK F28 G2 COMP2 5 6 TESTHI9
[22] CPUCLK BCLK0 COMP2 TESTHI9 [4]
1K/6 -CPUCLK G28 R1 COMP3 3 4 TESTHI10
[22] -CPUCLK BCLK1 COMP3 TESTHI10 [4]
TESTHI11
2
1
1 2
FSBSEL0 SKTOC- AE8 N5 62/8P4R
[8] SKTOC- SKTOCC# RSVD
RSVD AE6