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· PIC16CR54C Device Pins

PIC16CR54C
Pin Diagrams
PDIP and SOIC
RA2 RA3 T0CKI MCLRVPP VSS RB0 RB1 RB2 RB3 ·1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4

ROM-Based 8-Bit CMOS Microcontroller Series

Devices Included in this Data Sheet:

High-Performance RISC CPU:
· Only 33 single word instructions to learn · All instructions are single cycle (200 ns) except for program branches which are two-cycle · Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle I/O ROM RAM

PIC16CR54C

PIC16CR54C 18 12 512 25 · 12-bit wide instructions · 8-bit wide data path · Seven or eight special function hardware registers · Two-level deep hardware stack · Direct, indirect and relative addressing modes for data and instructions

SSOP
RA2 RA3 T0CKI MCLRVPP VSS VSS RB0 RB1 RB2 RB3 ·1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4

Peripheral Features:
· 8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler · Power-On Reset (POR) · Device Reset Timer (DRT) · Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation · Programmable code-protection · Power saving SLEEP mode · Selectable oscillator options: - RC: Low-cost RC oscillator - XT: Standard crystal/resonator - HS: High-speed crystal/resonator - LP: Power saving, low-frequency crystal

PIC16CR54C

CMOS Technology:
· Low-power, high-speed CMOS ROM technology · Fully static design · Wide-operating voltage and temperature range: - ROM Commercial/Industrial 3.0V to 5.5V · Low-power consumption - < 2 mA typical @ 5V, 4 MHz - 15 µA typical @ 3V, 32 kHz - < 0.6 µA typical standby current (with WDT disabled) @ 3V, 0°C to 70°C

© 1998 Microchip Technology Inc.

Preliminary

DS40191A-page 1

PIC16CR54C
Device Differences
Device PIC16C52 PIC16C54 PIC16C54A PIC16C54B Voltage Range 3.0-6.25 2.5-6.25 2.0-6.25 3.0-5.5 Oscillator Selection (Program) User Factory User User Oscillator See Note 1 See Note 1 See Note 1 See Note 1 Process Technology (Microns) 0.9 1.2 0.9 0.7 ROM Equivalent -- PIC16CR54A -- PIC16CR54B or PIC16CR54C -- -- -- PIC16CR56A -- PIC16CR57C NA PIC16CR58A PIC16CR58B NA NA NA NA NA NA NA MCLR Filter No No No Yes

PIC16C55 PIC16C55A PIC16C56 PIC16C56A PIC16C57 PIC16C57C PIC16CR57C PIC16C58A PIC16C58B PIC16CR54A PIC16CR54B PIC16CR54C PIC16CR56A PIC16CR57B PIC16CR58A PIC16CR58B

2.5-6.25 3.0-5.5 2.5-6.25 3.0-5.5 2.5-6.25 3.0-5.5 2.5-5.5 2.0-6.25 3.0-5.5 2.5-6.25 2.5-5.5 3.0-5.5 2.5-5.5 2.5-6.25 2.5-6.25 2.5-5.5

Factory User Factory User Factory User Factory User User Factory Factory Factory Factory Factory Factory Factory

See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1

1.7 0.7 1.7 0.7 1.2 0.7 0.7 0.9 0.7 1.2 0.7 0.7 0.7 0.9 0.9 0.7

No Yes No Yes No Yes Yes No(2) Yes Yes Yes Yes Yes Yes Yes Yes

Note 1: If you change from this device to another device, please verify oscillator characteristics in your application. Note 2: In PIC16LV58A, MCLR Filter = Yes

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© 1998 Microchip Technology Inc.

PIC16CR54C
Table of Contents 1.0 General Description............................................................................................................................................. 5 2.0 PIC16C5X Device Varieties................................................................................................................................. 7 3.0 Architectural Overview......................................................................................................................................... 9 4.0 Memory Organization ........................................................................................................................................ 13 5.0 I/O Ports ............................................................................................................................................................ 19 6.0 Timer0 Module and TMR0 Register .................................................................................................................. 21 7.0 Special Features of the CPU ............................................................................................................................. 25 8.0 Instruction Set Summary ................................................................................................................................... 37 9.0 Development Support........................................................................................................................................ 49 10.0 Electrical Characteristics - PIC16CR54C .......................................................................................................... 53 11.0 DC and AC Characteristics - PIC16CR54C....................................................................................................... 63 12.0 Packaging Information....................................................................................................................................... 73 Appendix A: Compatibility ............................................................................................................................................. 77 Index ............................................................................................................................................................................ 79 On-Line Support............................................................................................................................................................ 81 Reader Response ......................................................................................................................................................... 82 PIC16CR54C Product Identification System................................................................................................................. 83

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PIC16CR54C
NOTES:

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Preliminary

© 1998 Microchip Technology Inc.

PIC16CR54C
1.0 GENERAL DESCRIPTION
1.1 Applications
The PIC16C5X from Microchip Technology is a family of low-cost, high performance, 8-bit, fully static, EPROM/ ROM-based CMOS microcontrollers. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle (200 ns) except for program branches which take two cycles. The PIC16C5X delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly. The PIC16C5X products are equipped with special features that reduce system cost and power requirements. The Power-On Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset circuitry. There are four oscillator configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator. Power saving SLEEP mode, Watchdog Timer and code protection features improve system cost, power and reliability. The UV erasable CERDIP packaged versions are ideal for code development, while the cost-effective One Time Programmable (OTP) versions are suitable for production in any volume. The customer can take full advantage of Microchip's price leadership in OTP microcontrollers while benefiting from the OTP's flexibility. The PIC16C5X products are supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a `C' compiler, fuzzy logic support tools, a low-cost development programmer, and a full featured programmer. All the tools are supported on IBM® PC and compatible machines. The PIC16C5X series fits perfectly in applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. The EPROM technology makes customizing application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low-cost, low-power, high performance, ease of use and I/O flexibility make the PIC16C5X series very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of "glue" logic in larger systems, coprocessor applications).

© 1998 Microchip Technology Inc.

Preliminary

DS40191A-page 5

PIC16CR54C
TABLE 1-1: PIC16C5X FAMILY OF DEVICES
PIC16C52 Clock Maximum Frequency of Operation (MHz) EPROM Program Memory (x12 words) Memory ROM Program Memory (x12 words) RAM Data Memory (bytes) Peripherals Timer Module(s) I/O Pins Number of Instructions Features Packages 4 384 -- 25 TMR0 12 33 18-pin DIP, SOIC PIC16C54s 20 512 -- 25 TMR0 12 33 18-pin DIP, SOIC; 20-pin SSOP PIC16CR54s 20 -- 512 25 TMR0 12 33 18-pin DIP, SOIC; 20-pin SSOP PIC16C55s 20 512 -- 24 TMR0 20 33 28-pin DIP, SOIC; 28-pin SSOP PIC16C56s 20 1K -- 25 TMR0 12 33 18-pin DIP, SOIC; 20-pin SSOP

All PICmicroTM Family devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code protect and high I/O current capability.

PIC16CR56s Clock Maximum Frequency of Operation (MHz) EPROM Program Memory (x12 words) Memory ROM Program Memory (x12 words) RAM Data Memory (bytes) Peripherals Timer Module(s) I/O Pins Number of Instructions Features Packages 20 -- 1K 25 TMR0 12 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16C57s 20 2K -- 72 TMR0 20 33 28-pin DIP, SOIC; 28-pin SSOP

PIC16CR57s 20 -- 2K 72 TMR0 20 33 28-pin DIP, SOIC; 28-pin SSOP

PIC16C58s 20 2K -- 73 TMR0 12 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16CR58s 20 -- 2K 73 TMR0 12 33 18-pin DIP, SOIC; 20-pin SSOP

All PICmicroTM Family devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code protect and high I/O current capability.

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© 1998 Microchip Technology Inc.

PIC16CR54C
2.0 PIC16C5X DEVICE VARIETIES
2.3
A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC16CR54C Product Identification System at the back of this data sheet to specify the correct part number. For the PIC16C5X family of devices, there are four device types, as indicated in the device number: 1. C, as in PIC16C54. These devices have EPROM program memory and operate over the standard voltage range. LC, as in PIC16LC54A. These devices have EPROM program memory and operate over an extended voltage range. LV, as in PIC16LV54A. These devices have EPROM program memory and operate over a 2.0V to 3.8V range. CR, as in PIC16CR54A. These devices have ROM program memory and operate over the standard voltage range. LCR, as in PIC16LCR54B. These devices have ROM program memory and operate over an extended voltage range.

Quick-Turnaround-Production (QTP) Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration bit options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your Microchip Technology sales office for more details.

2.

2.4

Serialized Quick-Turnaround-Production (SQTP SM) Devices

3.

4.

5.

Microchip offers the unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. The devices are identical to the OTP devices but with all EPROM locations and configuration bit options already programmed by the factory. Serial programming allows each device to have a unique number which can serve as an entry code, password or ID number.

2.1

UV Erasable Devices (EPROM)

The UV erasable versions, offered in CERDIP packages, are optimal for prototype development and pilot programs UV erasable devices can be programmed for any of the four oscillator configurations. Microchip's PICSTART® and PRO MATE® programmers both support programming of the PIC16CR54C. Third party programmers also are available; refer to the Third Party Guide for a list of sources.

2.5

Read Only Memory (ROM) Devices

Microchip offers masked ROM versions of several of the highest volume parts, giving the customer a low cost option for high volume, mature products.

2.2

One-Time-Programmable (OTP) Devices

The availability of OTP devices is especially useful for customers expecting frequent code changes and updates. The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must be programmed.

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DS40191A-page 7

PIC16CR54C
NOTES:

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© 1998 Microchip Technology Inc.

PIC16CR54C
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CR54C can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CR54C uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12-bits wide making it possible to have all single word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (200ns @ 20MHz) except for program branches. The PIC16CR54C address 512 x 12 of program memory. All program memory is internal. The PIC16CR54C can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. The PIC16CR54C has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16CR54C simple yet efficient. In addition, the learning curve is reduced significantly. The PIC16CR54C device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-1.

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PIC16CR54C
FIGURE 3-1: PIC16CR54C SERIES BLOCK DIAGRAM
9-11 ROM 512 X 12 12 INSTRUCTION REGISTER 9 12 8 INSTRUCTION DECODER DIRECT ADDRESS DIRECT RAM ADDRESS 6 OPTION REG. FROM W 5 8 LITERALS STATUS TMR0 DATA BUS ALU FROM W 4 "TRIS 5" TRISA PORTA 4 RA3:RA0 4 "TRIS 6" 8 FROM W 8 TRISB 8 PORTB FSR 8 W "OPTION" GENERAL PURPOSE REGISTER FILE (SRAM) 25 Bytes WDT TIME OUT WDT/TMR0 PRESCALER CLKOUT 9-11 PC WATCHDOG TIMER "CODE PROTECT" STACK 1 STACK 2 T0CKI PIN OSC1 OSC2 MCLR

CONFIGURATION WORD "DISABLE"

"OSC SELECT" 2 OSCILLATOR/ TIMING & CONTROL

"SLEEP"

8 RB7:RB0

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© 1998 Microchip Technology Inc.

PIC16CR54C
TABLE 3-1:
Name RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 T0CKI MCLR/VPP OSC1/CLKIN OSC2/CLKOUT

PINOUT DESCRIPTION - PIC16CR54C
DIP, SOIC SSOP I/O/P Input No. No. Type Levels 17 18 1 2 6 7 8 9 10 11 12 13 3 4 16 15 19 20 1 2 7 8 9 10 11 12 13 14 3 4 18 17 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I O TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL ST ST ST(1) -- Bi-directional I/O port Description

Bi-directional I/O port

VDD 14 15,16 P -- 5 5,6 P -- VSS Legend: I = input, O = output, I/O = input/output, P = power, -- = Not Used, TTL = TTL input, ST = Schmitt Trigger input Note 1: Schmitt Trigger input only when in RC mode.

Clock input to Timer0. Must be tied to VSS or VDD, if not in use, to reduce current consumption. Master clear (reset) input/verify voltage input. This pin is an active low reset to the device. Oscillator crystal input/external clock source input. Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins.

© 1998 Microchip Technology Inc.

Preliminary

DS40191A-page 11

PIC16CR54C
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memory and latched into instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1. An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

FIGURE 3-2:

CLOCK/INSTRUCTION CYCLE
Q1 OSC1 Q1 Q2 Q3 Q4 PC
PC PC+1 PC+2 Internal phase clock

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

OSC2/CLKOUT (RC mode)

Fetch INST (PC) Execute INST (PC-1)

Fetch INST (PC+1) Execute INST (PC)

Fetch INST (PC+2) Execute INST (PC+1)

EXAMPLE 3-1:
1. MOVLW 55H 2. MOVWF PORTB 3. CALL 4. BSF SUB_1

INSTRUCTION PIPELINE FLOW
Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1

PORTA, BIT3

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.

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© 1998 Microchip Technology Inc.

PIC16CR54C
4.0 MEMORY ORGANIZATION
4.2.1 GENERAL PURPOSE REGISTER FILE PIC16CR54C memory is organized into program memory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one or two STATUS register bits. For devices with a data memory register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Selection Register (FSR). The register file is accessed either directly or indirectly through the file select register FSR (Section 4.7).

FIGURE 4-2:

PIC16CR54C REGISTER FILE MAP

File Address 00h 01h 02h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB

4.1

Program Memory Organization

The PIC16CR54C has a 9-bit Program Counter (PC) capable of addressing a 512 x 12 program memory space (Figure 4-1). Accessing a location above the physically implemented address will cause a wraparound. The reset vector for the PIC16CR54C is at 1FFh. A NOP at the reset vector location will cause a restart at location 000h.

03h 04h 05h 06h 07h

FIGURE 4-1:

PIC16CR54C PROGRAM MEMORY MAP AND STACK
PC<8:0> 9 Stack Level 1 Stack Level 2
000h Note 1:

0Fh 10h

General Purpose Registers

CALL, RETLW

1Fh
Not a physical register. See Section 4.7

User Memory Space

On-chip Program Memory

0FFh 100h

4.2.2

SPECIAL FUNCTION REGISTERS

Reset Vector

1FFh

The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). The special registers can be classified into two sets. The special function registers associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.

4.2

Data Memory Organization

Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: special function registers and general purpose registers. The special function registers include the TMR0 register, the Program Counter (PC), the Status Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special purpose registers are used to control the I/O port configuration and prescaler options. The general purpose registers are used for data and control information under command of the instructions. For the PIC16CR54C, the register file is composed of 7 special function registers and 25 general purpose registers (Figure 4-2).

© 1998 Microchip Technology Inc.

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PIC16CR54C
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY
Value on Power-On Reset 1111 1111 --11 1111 xxxx xxxx xxxx xxxx 1111 1111 TO PD Z DC C 0001 1xxx 1xxx xxxx RA3 RB3 RA2 RB2 RA1 RB1 RA0 RB0 ---- xxxx xxxx xxxx Value on MCLR and WDT Reset 1111 1111 --11 1111 uuuu uuuu uuuu uuuu 1111 1111 000q quuu 1uuu uuuu ---- uuuu uuuu uuuu

Address N/A N/A 00h 01h 02h(1) 03h 04h 05h 06h

Name TRIS OPTION INDF TMR0 PCL STATUS FSR PORTA PORTB

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I/O control registers (TRISA, TRISB) Contains control bits to configure Timer0 and Timer0/WDT prescaler Uses contents of FSR to address data memory (not a physical register) 8-bit real-time clock/counter Low order 8 bits of PC PA2 PA1 PA0

Indirect data memory address pointer -- RB7 -- RB6 -- RB5 -- RB4

Legend: Shaded boxes = unimplemented or unused, = unimplemented, read as '0' (if applicable) x = unknown, u = unchanged, q = see the tables in Section 7.7 for possible values. Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5 for an explanation of how to access these bits.

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PIC16CR54C
4.3 STATUS Register
This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bits for program memories larger than 512 words. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions, which do affect STATUS bits, see Section 8.0, Instruction Set Summary.

FIGURE 4-3:
R/W-0 PA2 bit7 bit 7:

STATUS REGISTER (ADDRESS:03h)
R/W-0 PA0 5 R-1 TO 4 R-1 PD 3 R/W-x Z 2 R/W-x DC 1 R/W-x C bit0

R/W-0 PA1 6

R = Readable bit W = Writable bit - n = Value at POR reset

PA2: This bit unused at this time. Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward compatibility with future products. Not Applicable TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF 1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF SUBWF 1 = A carry occurred 1 = A borrow did not occur 0 = A carry did not occur 0 = A borrow occurred RRF or RLF Load bit with LSb or MSb, respectively

bit 6-5: bit 4:

bit 3:

bit 2:

bit 1:

bit 0:

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PIC16CR54C
4.4 OPTION Register
The OPTION register is a 6-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A RESET sets the OPTION<5:0> bits.

FIGURE 4-4:
U-0 -- bit7 bit 7-6: bit 5:

OPTION REGISTER
U-0 -- 6 W-1 T0CS 5 W-1 T0SE 4 W-1 PSA 3 W-1 PS2 2 W-1 PS1 1 W-1 PS0 bit0 W = Writable bit U = Unimplemented bit - n = Value at POR reset

Unimplemented. T0CS: Timer0 clock source select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: Timer0 source edge select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler assignment bit 1 = Prescaler assigned to the WDT (not implemented on PIC16C52) 0 = Prescaler assigned to Timer0 PS2:PS0: Prescaler rate select bits Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate (not implemented on PIC16C52) 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128

bit 4:

bit 3:

bit 2-0:

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© 1998 Microchip Technology Inc.

PIC16CR54C
4.5 Program Counter FIGURE 4-5:
As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0> (Figure 4-5 and Figure 4-6). For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-10 and Figure 4-11)/ Instructions where the PCL is the destination, or Modify PCL instructions, include MOVWF PC, ADDWF PC, and BSF PC, 5. . Note: Because PC<8> is cleared in the CALL instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). 4.5.1

LOADING OF PC BRANCH INSTRUCTIONS PIC16CR54C

GOTO Instruction
8 PC 7 PCL 0

Instruction Word

CALL or Modify PCL Instruction
8 PC 7 PCL 0

Reset to '0'

Instruction Word

EFFECTS OF RESET

The Program Counter is set upon a RESET, which means that the PC addresses the last location in the last page i.e., the reset vector. The STATUS register page preselect bits are cleared upon a RESET, which means that page 0 is pre-selected. Therefore, upon a RESET, a GOTO instruction at the reset vector location will automatically cause the program to jump to page 0.

4.6

Stack

PIC16CR54C device has a 9-bit, two-level hardware push/pop stack (Figure 4-1). A CALL instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two sequential CALL are executed, only 's the most recent two return addresses are stored. A RETLW instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW's are executed, the stack will be filled with the address previously stored in level 2. Note that the W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory.

© 1998 Microchip Technology Inc.

Preliminary

DS40191A-page 17

PIC16CR54C
4.7 Indirect Data Addressing; INDF and FSR Registers EXAMPLE 4-2: HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x10 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue

The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.

NEXT

EXAMPLE 4-1:
· · · ·

INDIRECT ADDRESSING

movlw movwf clrf incf btfsc goto :

Register file 05 contains the value 10h Register file 06 contains the value 0Ah Load the value 05 into the FSR register A read of the INDF register will return the value of 10h · Increment the value of the FSR register by one (FSR = 06) · A read of the INDR register now will return the value of 0Ah.

CONTINUE

The FSR is a 5-bit ( PIC16CR54C) wide register. It is used in conjunction with the INDF register to indirectly address the data memory area. The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. PIC16CR54C: Do not use banking. FSR<6:5> are unimplemented and read as '1's.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-2.

FIGURE 4-6:

DIRECT/INDIRECT ADDRESSING
Direct Addressing (FSR) 6 5 4 (opcode) 0 6 Indirect Addressing 5 4 (FSR) 0

bank select

location select 00 00h

bank

location select

Data Memory(1)

0Fh 10h

1Fh Bank 0

Note 1: For register map detail see Section 4.2.

DS40191A-page 18

Preliminary

© 1998 Microchip Technology Inc.

PIC16CR54C
5.0 I/O PORTS
As with any other register, the I/O registers can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin's input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance) since the I/O control registers (TRISA, TRISB, TRISC) are all set. outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit (in TRISA, TRISB) must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin can be programmed individually as input or output.

FIGURE 5-1:
Data Bus D WR Port

EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN
Q Data Latch VDD Q P

5.1

PORTA

PORTA is a 4-bit I/O register. Only the low order 4 bits are used (RA3:RA0). Bits 7-4 are unimplemented and read as '0's.

CK

5.2

PORTB
W Reg N D TRIS Latch TRIS `f' CK Q Q VSS I/O pin(1)

PORTB is an 8-bit I/O register (PORTB<7:0>).

5.3

TRIS Registers

The output driver control registers are loaded with the contents of the W register by executing the TRIS f instruction. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low.

Reset

RD Port Note 1: I/O pins have protection diodes to VDD and VSS.

The TRIS registers are "write-only" and are set (output drivers disabled) upon RESET.

5.4

I/O Interfacing

The equivalent circuit for an I/O port pin is shown in Figure 5-1. All ports may be used for both input and output operation. For input operations these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB, W). The

TABLE 5-1:

SUMMARY OF PORT REGISTERS
Value on Power-On Reset 1111 1111 RA3 RB3 RA2 RB2 RA1 RB1 RA0 RB0 ---- xxxx xxxx xxxx Value on MCLR and WDT Reset 1111 1111 ---- uuuu uuuu uuuu

Address N/A 05h 06h

Name TRIS PORTA PORTB

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I/O control registers (TRISA, TRISB) -- RB7 -- RB6 -- RB5 -- RB4

Legend: Shaded boxes = unimplemented, read as `0', = unimplemented, read as '0', x = unknown, u = unchanged

© 1998 Microchip Technology Inc.

Preliminary

DS40191A-page 19

PIC16CR54C
5.5
5.5.1

I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS

EXAMPLE 5-1:

READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT

Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU, bit5 to be set and the PORTB value to be written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. Example 5-1 shows the effect of two sequential read-modify-write instructions (e.g., BCF, BSF, etc.) on an I/O port. A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip.

;Initial PORT Settings ; PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- ---------BCF PORTB, 7 ;01pp pppp 11pp pppp BCF PORTB, 6 ;10pp pppp 11pp pppp MOVLW 03Fh ; TRIS PORTB ;10pp pppp 10pp pppp ; ;Note that the user may have expected the pin ;values to be 00pp pppp. The 2nd BCF caused ;RB7 to be latched as the pin value (High).

5.5.2

SUCCESSIVE OPERATIONS ON I/O PORTS

The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.

FIGURE 5-2:

SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 MOVF PORTB,W PC + 2 NOP PC + 3 NOP

Instruction fetched RB7:RB0

MOVWF PORTB

This example shows a write to PORTB followed by a read from PORTB.
Port pin written here Port pin sampled here MOVF PORTB,W (Read PORTB) NOP

Instruction executed

MOVWF PORTB (Write to PORTB)

DS40191A-page 20

Preliminary

© 1998 Microchip Technology Inc.

PIC16CR54C
6.0 TIMER0 MODULE AND TMR0 REGISTER
Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The incrementing edge is determined by the source edge select bit T0SE (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1. The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 6.2 details the operation of the prescaler. A summary of registers associated with the Timer0 module is found in Table 6-1.

The Timer0 module has the following features: · 8-bit timer/counter register, TMR0 - Readable and writable · 8-bit software programmable prescaler · Internal or external clock select - Edge select for external clock Figure 6-1 is a simplified block diagram of the Timer0 module, while Figure 6-2 shows the electrical structure of the Timer0 input. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles (Figure 6-3 and Figure 6-4). The user can work around this by writing an adjusted value to the TMR0 register.

FIGURE 6-1:

TIMER0 BLOCK DIAGRAM
Data bus FOSC/4 0 1 1 PSout Sync with Internal Clocks 8 TMR0 reg

T0CKI pin

T0SE(1)

Programmable Prescaler(2) 3 T0CS(1) PS2, PS1, PS0(1)

0

PSout (2 cycle delay) Sync

PSA(1)

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure 6-6).

FIGURE 6-2:

ELECTRICAL STRUCTURE OF T0CKI PIN
RIN T0CKI pin

(1)

N

(1)

Schmitt Trigger Input Buffer

VSS

VSS

Note 1: ESD protection circuits

© 1998 Microchip Technology Inc.

Preliminary

DS40191A-page 21

PIC16CR54C
FIGURE 6-3:
PC (Program Counter) Instruction Fetch

TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6

Timer0 Instruction Executed

T0

T0+1

T0+2

NT0

NT0

NT0

NT0+1

NT0+2

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

Read TMR0 reads NT0 + 2

FIGURE 6-4:
PC (Program Counter) Instruction Fetch Timer0 T0

TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6

T0+1

NT0

NT0+1

T0

Instruction Execute

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0

Read TMR0 reads NT0

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

TABLE 6-1:

REGISTERS ASSOCIATED WITH TIMER0
Value on Power-On Reset Value on MCLR and WDT Reset

Address 01h N/A

Name TMR0 OPTION

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Timer0 - 8-bit real-time clock/counter -- -- T0CS T0SE PSA PS2 PS1 PS0

xxxx xxxx uuuu uuuu --11 1111 --11 1111

Legend: Shaded cells: Unimplemented bits, - = unimplemented, x = unknown, u = unchanged,

DS40191A-page 22

Preliminary

© 1998 Microchip Technology Inc.

PIC16CR54C
6.1 Using Timer0 with an External Clock
When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 6.1.1 EXTERNAL CLOCK SYNCHRONIZATION When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 6.1.2 TIMER0 INCREMENT DELAY

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.

Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing.

FIGURE 6-5:

TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling

External Clock Input or Prescaler Output (2) (1) External Clock/Prescaler Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 (3)

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.

© 1998 Microchip Technology Inc.

Preliminary

DS40191A-page 23

PIC16CR54C
6.2 Prescaler
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT) (WDT postscaler not implemented on PIC16C52), respectively (Section 6.1.2). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa. The PSA and PS2:PS0 bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler contains all '0's. 6.2.1 SWITCHING PRESCALER ASSIGNMENT following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT.

EXAMPLE 6-1:

CHANGING PRESCALER (TIMER0WDT)

1.CLRWDT ;Clear WDT 2.CLRF TMR0 ;Clear TMR0 & Prescaler 3.MOVLW '00xx1111'b ;These 3 lines (5, 6, 7) 4.OPTION ; are required only if ; desired 5.CLRWDT ;PS<2:0> are 000 or 001 6.MOVLW '00xx1xxx'b ;Set Postscaler to 7.OPTION ; desired WDT rate

To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler.

EXAMPLE 6-2:
CLRWDT MOVLW

CHANGING PRESCALER (WDTTIMER0)
;Clear WDT and ;prescaler ;Select TMR0, new ;prescale value and ;clock source

The prescaler assignment is fully under software control (i.e., it can be changed "on the fly" during program execution). To avoid an unintended device RESET, the

'xxxx0xxx'

OPTION

FIGURE 6-6:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 0 M U X 8 1 0 T0SE T0CS PSA M U X Sync 2 Cycles TMR0 reg

TCY ( = Fosc/4)

T0CKI pin

1

0 M U X

8-bit Prescaler 8 8 - to - 1MUX PS2:PS0

Watchdog Timer

1

PSA WDT Enable bit 0 MUX 1 PSA

WDT Time-Out Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.

DS40191A-page 24

Preliminary

© 1998 Microchip Technology Inc.

PIC16CR54C
7.0 SPECIAL FEATURES OF THE CPU
The SLEEP mode is designed to offer a very low current power-down mode. The user can wake up from SLEEP through external reset or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.

What sets a microcontroller apart from other processors are special circuits that deal with the needs of real-time applications. The PIC16C5X family of microcontrollers has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are: · · · · · · · Oscillator selection Reset Power-On Reset (POR) Device Reset Timer (DRT) Watchdog Timer (WDT) SLEEP Code protection

7.1

Configuration Bits

Configuration bits can be programmed to select various device configurations. Two bits are for the selection of the oscillator type and one bit is the Watchdog Timer enable bit. Nine bits are code protection bits (Figure 7-1 and Figure 7-2) for the PIC16CR54C devices. ROM devices have the oscillator configuration programmed at the factory and these parts are tested accordingly (see "Product Identification System" diagrams in the back of this data sheet).

The PIC16CR54C Family has a Watchdog Timer which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability. There is an 18 ms delay provided by the Device Reset Timer (DRT), intended to keep the chip in reset until the crystal oscillator is stable. With this timer on-chip, most applications need no external reset circuitry.

FIGURE 7-1:
CP bit11 CP 10

CONFIGURATION WORD FOR PIC16CR54C
CP 9 CP 8 CP 7 CP 6 CP 5 CP 4 CP 3 WDTE FOSC1 FOSC0 2 1 bit0 Register: Address(1): CONFIG 0FFFh

bit 11-3: CP: Code protection bits 1 = Code protection off 0 = Code protection on bit 2: WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator

bit 1-0:

Note 1: Refer to the PIC16C5X Programming Specification (Literature number DS30190) to determine how to access the configuration word.

© 1998 Microchip Technology Inc.

Preliminary

DS40191A-page 25

PIC16CR54C
7.2
7.2.1

Oscillator Configurations
OSCILLATOR TYPES

FIGURE 7-3:

EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1 PIC16CR54C

PIC16CR54Cs can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1:FOSC0) to select one of these four modes: · · · · LP: XT: HS: RC: Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR / CERAMIC RESONATORS

Clock from ext. system Open

OSC2

TABLE 7-1:

7.2.2

CAPACITOR SELECTION FOR CERAMIC RESONATORS - PIC16CR54C
Cap. Range C1 Cap. Range C2

In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 7-2). The PIC16CR54C oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source drive the OSC1/CLKIN pin (Figure 7-3).

Osc Type XT

Resonator Freq

455 kHz 68-100 pF 68-100 pF 2.0 MHz 15-33 pF 15-33 pF 4.0 MHz 10-22 pF 10-22 pF HS 8.0 MHz 10-22 pF 10-22 pF 16.0 MHz 10 pF 10 pF These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.

FIGURE 7-2:

CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)
OSC1

TABLE 7-2:

CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR - PIC16CR54C
Cap.Range C1 Cap. Range C2

C1(1)

PIC16CR54C
SLEEP

Osc Type LP XT

Resonator Freq

XTAL RS(2) C2(1) OSC2

RF(3)

To internal logic

Note 1: See Capacitor Selection tables for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen (approx. value = 10 M).

32 kHz(1) 15 pF 15 pF 200-300 pF 15-30 pF 100 kHz 100-200 pF 15-30 pF 200 kHz 15-100 pF 15-30 pF 455 kHz 15-30 pF 15-30 pF 1 MHz 15 pF 15 pF 2 MHz 15 pF 15 pF 4 MHz HS 4 MHz 15 pF 15 pF 8 MHz 15 pF 15 pF 20 MHz 15 pF 15 pF Note 1: For VDD > 4.5V, C1 = C2 30 pF is recommended. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.

Note:

If you change from this device to another device, please verify oscillator characteristics in your application.

DS40191A-page 26

Preliminary

© 1998 Microchip Technology Inc.

PIC16CR54C
7.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT

FIGURE 7-5:

Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. Figure 7-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs.

EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT (USING XT, HS OR LP OSCILLATOR MODE)
330 74AS04 74AS04 To Other Devices PIC16CR54C CLKIN

330 74AS04 0.1 µF XTAL

OSC2 100k

Note:

If you change from this device to another device, please verify oscillator characteristics in your application. RC OSCILLATOR

FIGURE 7-4:

EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT (USING XT, HS OR LP OSCILLATOR MODE)
To Other Devices

7.2.4

+5V 10k 4.7k 74AS04 74AS04 PIC16CR54C CLKIN

OSC2 10k XTAL 10k 20 pF 20 pF 100k

For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 7-6 shows how the R/C combination is connected to the PIC16CR54C. For Rext values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 M) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping Rext between 3 k and 100 k. Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance.

Note:

If you change from this device to another device, please verify oscillator characteristics in your application.

Figure 7-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180-degree phase shift in a series resonant oscillator circuit. The 330 resistors provide the negative feedback to bias the inverters in their linear region.

© 1998 Microchip Technology Inc.

Preliminary

DS40191A-page 27

PIC16CR54C
The Electrical Specifications sections show RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). Also, see the Electrical Specifications sections for variation of oscillator frequency due to VDD for given Rext/Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic.

7.3

Reset

PIC16CR54C devices may be reset in one of the following ways: · · · · · Power-On Reset (POR) MCLR reset (normal operation) MCLR wake-up reset (from SLEEP) WDT reset (normal operation) WDT wake-up reset (from SLEEP)

Table 7-3 shows these reset conditions for the PCL and STATUS registers. Some registers are not affected in any reset condition. Their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a "reset state" on Power-On Reset (POR), MCLR or WDT reset. A MCLR or WDT wake-up from SLEEP also results in a device reset, and not a continuation of operation before SLEEP. The TO and PD bits (STATUS <4:3>) are set or cleared depending on the different reset conditions (Section 7.7). These bits may be used to determine the nature of the reset. Table 7-4 lists a full description of reset states of all registers. Figure 7-7 shows a simplified block diagram of the on-chip reset circuit.

FIGURE 7-6:
VDD Rext

RC OSCILLATOR MODE

OSC1 N

Internal clock

Cext VSS Fosc/4

PIC16CR54C

OSC2/CLKOUT

Note:

If you change from this device to another device, please verify oscillator characteristics in your application.

DS40191A-page 28

Preliminary

© 1998 Microchip Technology Inc.

PIC16CR54C
TABLE 7-3: RESET CONDITIONS FOR SPECIAL REGISTERS
Condition Power-On Reset MCLR reset (normal operation) MCLR wake-up (from SLEEP) WDT reset (normal operation) PCL Addr: 02h 1111 1111 1111 1111 1111 1111 1111 1111 STATUS Addr: 03h 0001 1xxx 000u uuuu(1) 0001 0uuu 0000 1uuu(2) 0000 0uuu

WDT wake-up (from SLEEP) 1111 1111 Legend: u = unchanged, x = unknown, - = unimplemented read as '0'. Note 1: TO and PD bits retain their last value until one of the other reset conditions occur. 2: The CLRWDT instruction will set the TO and PD bits.

TABLE 7-4:
Register W TRIS OPTION INDF TMR0 PCL(1) STATUS(1) FSR PORTA PORTB

RESET CONDITIONS FOR ALL REGISTERS
Address N/A N/A N/A 00h 01h 02h 03h 04h 05h 06h Power-On Reset
xxxx xxxx 1111 1111 --11 1111 xxxx xxxx xxxx xxxx 1111 1111 0001 1xxx 111x xxxx ---- xxxx xxxx xxxx

MCLR or WDT Reset
uuuu uuuu 1111 1111 --11 1111 uuuu uuuu uuuu uuuu 1111 1111 000q quuu 111u uuuu ---- uuuu uuuu uuuu uuuu uuuu

General Purpose Register Files 07-1Fh xxxx xxxx Legend: u = unchanged, x = unknown, - = unimplemented, read as '0', q = see tables in Section 7.7 for possible values. Note 1: See Table 7-3 for reset value for specific conditions.

FIGURE 7-7:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Power-Up Detect VDD POR (Power-On Reset)

MCLR/VPP pin

WDT Time-out RESET WDT On-Chip RC OSC 8-bit Asynch Ripple Counter (Start-Up Timer) S Q

R

Q CHIP RESET

DS40191A-page 29

Preliminary

© 1998 Microchip Technology Inc.

PIC16CR54C
7.4 Power-On Reset (POR) FIGURE 7-8:
The PIC16CR54C incorporates on-chip Power-On Reset (POR) circuitry which provides an internal chip reset for most power-up situations. To use this feature, the user merely ties the MCLR/VPP pin to VDD. A simplified block diagram of the on-chip Power-On Reset circuit is shown in Figure 7-7. The Power-On Reset circuit and the Device Reset Timer (Section 7.5) circuit are closely related. On power-up, the reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the on-chip reset signal. A power-up example where MCLR is not tied to VDD is shown in Figure 7-9. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of reset TDRT msec after MCLR goes high. In Figure 7-10, the on-chip Power-On Reset feature is being used (MCLR and VDD are tied together). The VDD is stable before the start-up timer times out and there is no problem in getting a proper reset. However, Figure 7-11 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses a high on the MCLR/VPP pin, and when the MCLR/VPP pin (and VDD) actually reach their full value, is too long. In this situation, when the start-up timer times out, VDD has not reached the VDD (min) value and the chip is, therefore, not guaranteed to function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure 7-8). When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be meet to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. For more information on PIC16CR54C POR, see Power-Up Considerations - AN522 in the Embedded Control Handbook. The POR circuit does not produce an internal reset when VDD declines. Note:

EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD

VDD

D

R R1 MCLR C PIC16CR54C

· External Power-On Reset circuit is required only if VDD power-up is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. · R < 40 k is recommended to make sure that voltage drop across R does not violate the device electrical specification. · R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).

DS40191A-page 30

Preliminary

© 1998 Microchip Technology Inc.

PIC16CR54C
FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)

VDD MCLR INTERNAL POR TDRT

DRT TIME-OUT INTERNAL RESET

FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME

VDD MCLR INTERNAL POR TDRT

DRT TIME-OUT

INTERNAL RESET

FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1 VDD MCLR INTERNAL POR TDRT DRT TIME-OUT

INTERNAL RESET When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min

DS40191A-page 31

Preliminary

© 1998 Microchip Technology Inc.

PIC16CR54C
7.5 Device Reset Timer (DRT) 7.6 Watchdog Timer (WDT)
The Device Reset Timer (DRT) provides a fixed 18 ms nominal time-out on reset. The DRT operates on an internal RC oscillator. The processor is kept in RESET as long as the DRT is active. The DRT delay allows VDD to rise above VDD min., and for the oscillator to stabilize. Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the device in a RESET condition for approximately 18 ms after the voltage on the MCLR/VPP pin has reached a logic high (VIH) level. Thus, external RC networks connected to the MCLR input are not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications. The Device Reset time delay will vary from chip to chip due to VDD, temperature, and process variation. See AC parameters for details. The DRT will also be triggered upon a Watchdog Timer time-out. This is particularly important for applications using the WDT to wake the PIC16CR54C from SLEEP mode automatically. The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins have been stopped, for example, by execution of a SLEEP instruction. During normal operation or SLEEP, a WDT reset or wake-up reset generates a device RESET. The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer reset. The WDT can be permanently disabled by programming the configuration bit WDTE as a '0' (Section 7.1). Refer to the PIC16C5X Programming Specifications (Literature Number DS30190) to determine how to access the configuration word. 7.6.1 WDT PERIOD

The WDT has a nominal time-out period of 18 ms, (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, time-out a period of a nominal 2.3 seconds can be realized. These periods vary with temperature, VDD and part-to-part process variations (see DC specs). Under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs. 7.6.2 WDT PROGRAMMING CONSIDERATIONS

The CLRWDT instruction clears the WDT and the postscaler, if assigned to the WDT, and prevents it from timing out and generating a device RESET. The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum SLEEP time before a WDT wake-up reset.

DS40191A-page 32

Preliminary

© 1998 Microchip Technology Inc.

PIC16CR54C
FIGURE 7-12: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source 0 Watchdog Timer 1 M U X Postscaler Postscaler

8 - to - 1 MUX WDT Enable EPROM Bit PSA

PS2:PS0

To TMR0 0 MUX Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register. WDT Time-out 1 PSA

TABLE 7-5:

SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on Power-On Reset --11 1111 Value on MCLR and WDT Reset --11 1111

Address N/A

Name OPTION

Bit 7 --

Bit 6 --

Bit 5 T0CS

Bit 4 T0SE

Bit 3 PSA

Bit 2 PS2

Bit 1 PS1

Bit 0 PS0

Legend: Shaded boxes = Not used by Watchdog Timer, = unimplemented, read as '0', u = unchanged

DS40191A-page 33

Preliminary

© 1998 Microchip Technology Inc.

PIC16CR54C
7.7 Time-Out Sequence and Power Down Status Bits (TO/PD) 7.8 Reset on Brown-Out
A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a brown-out. To reset PIC16CR54C devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in Figure 7-13 and Figure 7-14.

The TO and PD bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) reset, or a MCLR or WDT wake-up reset.

TABLE 7-6:
TO
1 u 1 0 0

TO/PD STATUS AFTER RESET
RESET was caused by Power-up (POR) MCLR reset (normal operation)(1) MCLR wake-up reset (from SLEEP) WDT reset (normal operation) WDT wake-up reset (from SLEEP)

PD
1 u 0 1 0

FIGURE 7-13: BROWN-OUT PROTECTION CIRCUIT 1
VDD VDD 33k 10k Q1 MCLR 40k PIC16CR54C

Legend: u = unchanged Note 1: The TO and PD bits maintain their status (u) until a reset occurs. A low-pulse on the MCLR input does not change the TO and PD status bi