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KL3E Intel Huron River Platform with Discrete GFX
01
14.318MHz
CLOCK GEN FAN / THERMAL
ICS9LRS3197AKLFT
EMC2103-2 POWER
PG 35
PG 3
A
Discharge A
PG 38
AMD (40nm)
DDR SYSTEM MEMORY
27MHz
RUN POWER SW
PCI-E 3VSUS, 5VSUS, 3V_S5, 5V_S5
DDRIII-SODIMM1
PCI-Express
Park XT 64 Bit 969p +3V, +5V PG 38
PG 14
Dual Channel DDR3 SandyBridge 0.61 Madison Pro AC/BATT CONNECTOR
16X
Graphics Interfaces
800/1067 1.5V
DDRIII-SODIMM2
rPGA 988 PG 16,17,18,19,20,21,22 PG 42
PG 15
BATT CHARGER
EXT_HDMI
EXT_LVDS
EXT_CRT
FDI DMI
PG 39
PG 4,5,6,7
REGULATOR (DDR3)
1.5VSUS, 0.75VSMDDR_VTERM,1.5V
1.5V_GPU,1.5V_CPU PG 40
FDIx8 DMIX4
HDMI CON
B 32.768KHz PG 23
REGULATOR B
+1.05V_VTT,+1.8V PG 41
FDI DMI
SATA - HDD SATA0 150MB LVDS_CRT_HDMI
CRT DC/DC
PG 28
INT_HDMI Switch Graphic PG 25 3VPCU, 5VPCU, +15V
SATA1 150MB INT_CRT PG 42
SATA - CD-ROM
INT_LVDS LCD CONN
PG 28 PG 23 PG 24
CPU Core
SATA5 150MB PG 43
USB+eSATA
USB2.0 USB2.0
PG 28 VGA Core Discrete
CougarPoint 0.7 0,1,8 4 6,10,11 1.8V_GPU, 1V_GFX_PCIE
PG 44
SPI BIOS SPI USB2.0 Ports X3 BlueTooth Mini PCI-E Card X 2
PG 9 PCH PG 29 PG 29 Express Card
PG 30
VGA Core UMA PG 45
Speaker
IHDA
PG 27 AUDIO CODEC PCI-E
C C
Audio Jack ALC272 X2 X1 X1 X1
PG 27 USB2.0 2
(External MIC)
Mini PCI-E Card LAN Express Card Card Reader
PG 27 PG 8,9,10,11,12,13
(NEW CARD)
Camera + D-MIC (WLAN/ WWAN) Broadcom JMB385/387
Head-Phone Jack PG 24 (10/100/1G LAN)
+ SPDIF LPC
32.768KHz BCM57790/57780 PAGE 30
PG 27 PAGE 30 PAGE 26 PAGE 32
Touch Pad PS/2
PG 34 25MHz
EC
SPI SPI BIOS RJ45 CONN 7-IN-1 Card
Keyboard IT8512E Reader CONN
PG 34 PG 36 PG 26
PG 30
PAGE 36
D D
Ambient
LIGHT SENSOR
PG 35
PROJECT : KL2D
Quanta Computer Inc.
Size Document Number Rev
Custom BLOCK DIAGRAM 1A
Date: Thursday, September 30, 2010 Sheet 1 of 48
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)
+3V +VIN +VIN +1.05V_VTT +1.5V_SUS +1.8V
02
PCH DGPU_PWR_EN# VDDR3 +3V_GPU VDDC PG_GPUIO_EN VDDCI PG_1V_EN PCIE_VDDC PG_1.5V_EN VDDR1 +1.5V_GPU VDDR4 +1.8V_GPU
BJT dGPU_PWROK
Cougar Point MOS (SI2303) RT8204 UP6111A RT8204 MOS (AO4496) MOS (AO6402A)
P51
P10 P19 P45 P46 P45 P50 P51
A A
+3V_GPU (0.6A) +VGPU_CORE (29A) +VGPU_IO (4.5A) +1V_GPU (2A) +1.5V_GPU (5.25A) +1.8V_GPU (1.9A)
AC/DC +VIN PCU +5VPCU
+3V_PCU S5_ON
+3V_S5 RUN_ON
Charger 3V/5V ALW S5 PWR RUN PWR
ISL88731A RT8206B AO4496 MOS (AO4496) +5V
P53 P52 P52 +5V_S5
P54
NBSWON# EC_PWRBTN# 1 SLP_LAN#
+3VPCU
+VIN +3V_PCU
Main Power Rails +5V_PCU 2 SLP_A#
EC
IT8502N PCH
CONTROL 3 Cougar Point RUN PWR
POWER PLANE VOLTAGE DESCRIPTION ACTIVE IN SUS_ON SLP_S4# +3V
SIGNAL SYS_PWRGD MOS (AO4496)
VDDR_PWRGD RUN_ON SLP_S3# 4 P54
B +0.75V_DDR_VTT +0.75V DDR3 reference voltage RUN_ON B
1.8V_PWRGD P08
+0.85V +0.9V Intel new power rail 1.05V_VTT_PWRGD 1.05V_PCH_PWRGD
+1.5V_SUS
HWPG VRON
1.05V_VTT_PWRGD
+1.05V_LAN_M +1.05V LAN M power for iAMT SLP_LAN#
0.85V_PWRGD P39
+1.05V_M +1.05V ME power for iAMT SLP_A# APWROK
RUN PWR
MOS (AO6402A) +1.5V
GFX_PWRGD
+1.05V_PCH +1.05V PCH core power RUN_ON P50
+1.05V_SUS +1.05V USB3.0 chip power SUSD +VIN
+1.05V_VTT +1.05V CPU core logic power RUN_ON +VIN +VIN
+1.5V +1.5V I/O module power RUN_ON RUN PWR
UP6111A +1.8V
+1.5V_CPU +1.5V CPU DDR3 controller power RUN_ON_D SUS_ON DDR PWR SLP_LAN# VDD_LAN
+1.5V_SUS +1.05V_LAN_M P51
RT8207A UP6111AQDD
+1.5V_GPU +1.5V GPU DDR3 controller power PG_1.5V_EN
P50 P49 +1.5V_SUS
+1.5V_SUS +1.5V DDR3 SODIMM power SUS_ON
+5VPCU +3VPCU
+1.8V +1.8V CPU/PCH/LVDS power RUN_ON
RUN PWR
+1.8_GPU +1.8V GPU power +1.5V_GPU RT8207A +SMDDR_VREF
C SUS PWR VCC_LAN P50
C
+1V_GPU +1V GPU PCIE VDDC power PG_1V_EN MOS (AO6402A) +5V_SUS MOS (ME3424) +3V_LAN
P54 P36 +1.05V_LAN_M
+3V +3.3V I/O power RUN_ON
+3V_GPU +3.3V GPU power DGPU_PWR_EN#
+3VPCU +3VPCU
+3V_M +3.3V PCH/SPI power for iAMT SLP_A#
VCC_PCH
MOS (AOL1718) +1.05V_PCH
+3V_S5 +3.3V 3V power sequence S5_ON
SUS PWR VCCSPI P49
MOS (AO6402A) +3V_SUS MOS (AO4496) +1.05V_M
+3V_SUS +3.3V USB3.0 chip power SUSD P54 P49 +VIN +VIN
+3VPCU +3.3V Always power SYS_SHDN# +1.05V_LAN_M
+1.05V_LAN_M
+5V +5V I/O power RUN_ON VCCIO_CPU 1.05V_VTT_PWRGD VCCSA
UP6111A UP6112
+5V_S5 +5V 5V power sequence S5_ON SUS PWR
+1.05V_SUS SLP_A# VCCASW P47 P49
MOS (AO6402A) +3V_M
+5V_SUS +5V USB2.0 power SUSD MOS (AO6402A)
P54
P54 +1.05V_VTT +0.85V
+5VPCU +5V Always power SYS_SHDN#
+15V_ALW +15V Power sequence +VIN
D +SMDDR_VREF +0.75V DDR3 reference power RUN_ON D
+VCC_CORE +1.1V CPU Core power VRON VRON
+VCC_CORE
CPU Core
ISL9583CRZ
+VCC_GFX +1.52V Internal GPU Core power VRON +VCC_GFX
P43
+VGPU_CORE +1V GPU Core power DGPU_VRON
PROJECT : KL2D
+VGPU_IO +1V GPU I/O controller power PG_GPUIO_EN Quanta Computer Inc.
+VIN +19V AC power input Size Document Number Rev
1A
PWR Status & GPU PWR CRL
Date: Thursday, September 30, 2010 Sheet 2 of 48
1 2 3 4 5 6 7 8
5 4 3 2 1
EC
NO.
PG. DATE
PART
REFERENCE
DESCRIPTION 03
EC-C-01 41 08/26 PR319 Add PR319. Change +0.75V contral signal
EC-C-02 36 08/26 Change LED power to +3V_S5
D D
EC-C-03 24 08/26 Change HDMI pull high to +3V
EC-C-04 23 08/30 Remove MUX for LVDS and CRT. Change for Resistor option.
EC-C-05 18 09/01 C91 Change C91 to 0603 part. The same as C594
EC-C-06 10 09/01 Q47, R725, R726 Del reserve schematic
EC-C-07 9 09/01 R538 Change value to 1K
EC-C-08 9 C814 Reserve for RF
09/02
C483, C355, C356 Mount CYAVLC18B02 for ESD
EC-A-09 35,37 09/07
C C
B B
A A
PROJECT : KL2D
Quanta Computer Inc.
Size Document Number Rev
1A
Clock Generator
Date: Thursday, September 30, 2010 Sheet 3 of 48
5 4 3 2 1
5 4 3 2 1
Sandy Bridge Processor (DMI,PEG,FDI)
U47A
PEG_COMP
PEG_COMP connect to PIN H22&J22 W:4mils/S:15mils/L: 500mils.
Sandy Bridge Processor (CLK,MISC,JTAG)
U47B
04
J22 PEG_COMP connect to PIN J21 W:12mils/S:15mils/L: 500mils.
PEG_ICOMPI
J21
PEG_ICOMPO
DMI_TXN0 B27
DMI_RX#[0] PEG_RCOMPO
H22 SNB_IVB# N.A at SNB EDS #27637 0.7v1 BCLK
A28 CLK_CPU_BCLKP
MISC
CLOCKS
DMI_TXN1 B25 DMI_RX#[1] PEG_RXN[0..15] H_SNB_IVB# C26 PROC_SELECT# BCLK# A27 CLK_CPU_BCLKN
DMI_TXN2 A25
DMI_RX#[2] PEG_RXN0
DMI_TXN3 B24 K33
DMI_RX#[3] PEG_RX#[0] PEG_RXN1 SKTOCC#
M35 TP7 AN34
D PEG_RX#[1] PEG_RXN2 SKTOCC# CLK_DPLL_SSCLKP_R
D
DMI_TXP0 B28 L34 A16 3 4 CLK_DPLL_SSCLKP
DMI_RX[0] PEG_RX#[2] PEG_RXN3 DPLL_REF_CLK CLK_DPLL_SSCLKN_R
DMI_TXP1 B26 DMI_RX[1] PEG_RX#[3] J35 DPLL_REF_CLK# A15 1 2 CLK_DPLL_SSCLKN
DMI
PEG_RXN4 R514
DMI_TXP2 A24
B23
DMI_RX[2] PEG_RX#[4]
J32
H34 PEG_RXN5 Ra SW@0X2
DMI_TXP3 DMI_RX[3] PEG_RX#[5]
H31 PEG_RXN6 TP_CATERR# AL33 R515 Rb *DIS@0/J_4 DIS SW/UMA
PEG_RX#[6] TP6 CATERR#
G21 G33 PEG_RXN7 R510 *DIS@0/J_4
DMI_RXN0
E22
DMI_TX#[0] PEG_RX#[7]
G30 PEG_RXN8 Ra NA 0 ohm
DMI_RXN1 DMI_TX#[1] PEG_RX#[8] Rc
THERMAL
F21 F35 PEG_RXN9
DMI_RXN2
D21
DMI_TX#[2] PEG_RX#[9]
E34 PEG_RXN10
EC_PECI AN33 R8 CPU_DRAMRST#
Rb 0 ohm NA
DMI_RXN3 DMI_TX#[3] PEG_RX#[10] PECI SM_DRAMRST#
E32 PEG_RXN11
Rc 0 ohm NA
DDR3
MISC
PEG_RX#[11] PEG_RXN12
DMI_RXP0 G22 DMI_TX[0] PEG_RX#[12] D33
D22 D31 PEG_RXN13
DMI_RXP1 DMI_TX[1] PEG_RX#[13]
PCI EXPRESS* - GRAPHICS
F20 B33 PEG_RXN14