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R AM_PWR
C188 C189 N 13
O CMADDR18 1 21 OCMDATA7
O CMADDR17 A18 DQ7 OCMDATA6
4 7 u F / 16V 0.1uF 30 20
O CMADDR16 A17 DQ6 OCMDATA5
2 19
O CMADDR15 A16 DQ5 OCMDATA4
3 18
O CMADDR14 A15 DQ4 OCMDATA3
29 17
O CMADDR13 A14 DQ3 OCMDATA2
GND 28 15
O C M D A T A [ 0 . .7] O CMADDR12 A13 DQ2 OCMDATA1
4 14
O C M D A T A [ 0 . .7] A12 DQ1
O CMADDR11 25 13 OCMDATA0
O CMADDR10 A11 DQ0
23
O CMADDR9 A10
26
O CMADDR8 A9 /ROM_CS
27 22
O CMADDR7 A8 CE# /OCM_RE
5 24 +5V
O CMADDR6 A7 OE# / OCM_WE
6 31
O CMADDR5 A6 WE#
7 J1
O CMADDR4 A5
8
O CMADDR3 A4 R AM_PWR 1
9 32
O CMADDR2 A3 VCC 2
10
A2 3
O CMADDR1 11 16
O CMADDR0 A1 VSS
12 C O N3
O C M A D D R [ 0 . . 1 9] A0
O C M A D D R [ 0 . . 1 9]
P L C C 3 2 / S O C KET G ND + 3 . 3 V _ D IG
2 9 L V 040B
/ OCM_WE
/ OCM_WE /OCM_RE
/OCM_RE /ROM_CS
/ROM_CS
+ 3 . 3 V _ DIG
10: L O W ( U s e T C LK)
11: L O W ( s e t a l l d i s p l a y o u t p u t t o '0')
12: L OW
8 13: L O W ( d i s a b l e s e r i a l i n t e r f a c e d e b u g)
7
6
5
8
7
6
5
14: L OW
RP21 15: L OW
RP20 16: H I G H ( u s e c rystal)
10KX4
10KX4 17: LOW (8bit bus with OCM access external ROM)
18: HIGH
19: L OW
1
2
3
4
1
2
3
4
C ustom1 R 78 0R
C ustom2 R 44 0R
R P 2 2 10KX4 S e r i a l _ I n t e r f a ce_Debug1 R 79 0R
O CMADDR8 1 8
O CMADDR9 2 7 S e r i a l _ I n t e r f a ce_Debug2 R 80 0R
O CMADDR10 3 6 TCLK
O CMADDR12 4 5 OUTPUTS_ZERO S e r i a l _ I n t e r f a ce_Debug3 R 81 0R
O CMADDR11 1 8 OUTPUTS_ZERO
O CMADDR13 2 7
O CMADDR14 3 6 BOOTSTRAP HEADER
O CMADDR15 4 5 OP EN=1 GND
O CMADDR16 R P 2 3 10KX4 INT_OSC S H U NTED=0
O CMADDR18 8 - B I T _ F L ASH2
O CMADDR17 R 82 10K 8 - B I T _ F L ASH1 GND
O CMADDR19 R 83 10K 8 - B I T _ F L ASH3
GND