Text preview for : ACER 4750 CORE I5 - JV50 CP.pdf part of acer ACER 4750 CORE I5 - JV50 CP acer ACER 4750 CORE I5 - JV50 CP.pdf
Back to : ACER 4750 CORE I5 - JV50 | Home
5 4 3 2 1
Project code: 91.4GD01.001 CPU DC/DC
ISL62882
JV50-CP Block Diagram PCB P/N
REVISION
: 48.4GD01.0SB
: SB 09285
INPUTS OUTPUTS
DCBATOUT VCC_CORE
47,48
Intel CPU SYSTEM DC/DC
Clock Generator DDRIII Slot 0 ATI TPS51123
D
ICS9LRS3197AKLFT 3 800/1066/1333 20
DDRIII Channel A Arrandale PCI EXPRESS GRAPHIC Madison
VRAM
INPUTS OUTPUTS
D
sDDR3 1Gb*8
Clarksfield X16 or Park
62~66
67~70 DCBATOUT
5V_S5
3D3V_S5 49
DDRIII Slot 1 DDRIII Channel B 4~10
800/1066/1333 21
SYSTEM DC/DC
Digital Display
TPS51117
LVDS 1CH
RGB CRT
DMIx4 FDIx8 INPUTS OUTPUTS
DCBATOUT 1D5V_S3
50
PCH RGB CRT Switch CRT 24
Mini-Card 1 PCIE+USB 2.0 22 SYSTEM DC/DC
WLAN 37 INTEL TPS51117
LCD
PCH LVDS 1CH Switch 23 INPUTS OUTPUTS
WXGA+
PCH 22
DCBATOUT 1D05V_S0
50
Mini-Card 2 14 USB 2.0/1.1 ports PCH Digital Display Switch HDMI 25
WLAN or 3G 37 ETHERNET (10/100/1000Mb) 25 SYSTEM DC/DC
C C
High Definition Audio
TPS51117
WEBCAM 23
INPUTS OUTPUTS
6 SATA ports
Giga LAN 8 PCIE ports DCBATOUT 1D05V_VTT
RJ45 PCIE 51
BLUETOOTH28
CONN 31 BCM57780 ACPI 1.1
30 LPC I/F
RT9025
USB x 4 29
INPUTS OUTPUTS
PCI/PCI BRIDGE
INT MIC USB 2.0
SD/MMC 3D3V_S0 1D8V_S0
Card Reader
AU6433 36 50
HD AUDIO 36 MS/MS Pro/xD
MIC IN CODEC AZALIA G2997
ALC272 32 Touch Panel 23
INPUTS OUTPUTS
LINE IN 1D5V_S3 0D75_S0
52
Finger Print 43
LINE OUT&SPDIF
SYSTEM DC/DC
ISL62881
SATA HDD 26
B INPUTS OUTPUTS B
SATA DCBATOUT VCC_GFXCORE
54
SATA ODD 27
2CH SPEAKER
OP AMP SYSTEM DC/DC
APA2031 11~19 TPS51117
33 SPI
Flash ROM
41
INPUTS OUTPUTS
4MB
DCBATOUT +VGA_CORE
LPC Bus LPC debug 55
MODEM 40
RJ11
MDC CARD
35
CHARGER
KBC ISL88731A
PCB STACKUP INPUTS OUTPUTS
SPI
NPCE781B
40 TOP DCBATOUT BT+
53
GND
A ENG DIS MADSION SAMSUNG A
S
Thermal Wistron Corporation
S 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Flash ROM Touch Int. Taipei Hsien 221, Taiwan, R.O.C.
Sensor
128KB 41 PAD KB40 GND
Title
G787 39 43
BOTTOM Block Diagram
FAN Size Document Number Rev
A3
JV50-CP SA
Date: Thursday, August 27, 2009 Sheet 1 of 57
5 4 3 2 1
A B C D E
PCH Strapping Processor Strapping
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
CFG[4] Embedded 1: Disabled - No Physical Display Port attached to 1
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k Embedded DisplayPort.
- 10-k weak pull-up resistor. DisplayPort
Presence 0: Enabled - An external Display Port device is
INIT3_3V# Weak internal pull-down. Do not pull high. connected to the Embedded Display Port.
4 GNT3#/ Default Mode: Internal pull-up. CFG[3] PCI-Express Static 1: Normal Operation. 1
4
GPIO55 Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k weak Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
pull-down resistor).
CFG[0] PCI-Express 1: Single PCI-Express Graphics 1
INTVRMEN High (1) = Integrated VRM is enabled Configuration 0: Bifurcation enabled
Low (0) = Integrated VRM is disabled Select
GNT0#, Default (SPI): Left both GNT0# and GNT1# floating. No pull up
GNT1# required. CFG[7] Reserved - Clarksfield (only for early samples pre-ES1) - 0
Temporarily used Connect to GND with 3.01K Ohm/5% resistor
Boot from PCI: Connect GNT1# to ground with 1-k pull-down
resistor. Leave GNT0# Floating. for early Note: Only temporary for early CFD samples
Clarksfield (rPGA/BGA) [For details please refer to the WW33
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-k samples. MoW and sighting report].
pull-down resistor. For a common motherboard design (for AUB and CFD),
GNT2#/ Default - Internal pull-up. the pull-down resistor should be used. Does not
GPIO53 Low (0)= Configures DMI for ESI compatible operation (for servers impact AUB functionality.
only. Not for mobile/desktops).
GPIO33 Default: Do not pull low.
Disable ME in Manufacturing Mode: Connect to ground with 1-k
pull-down resistor.
SPI_MOSI Enable iTPM: Connect to Vcc3_3 with 8.2-k weak pull-up resistor.
3 Disable iTPM: Left floating, no pull-down required. 3
NV_ALE Enable Danbury: Connect to Vcc3_3 with 8.2-k weak pull-up
resistor.
Disable Danbury: Connect to ground with 4.7-k weak pull-down
resistor.
NC_CLE Weak internal pull-up. Do not pull low.
HAD_DOCK_EN# Low (0): Flash Descriptor Security will be overridden.
/GPIO[33] High (1) : Flash Descriptor Security will be in effect.
HDA_SDO Weak internal pull-down. Do not pull high.
HDA_SYNC Weak internal pull-down. Do not pull high.
GPIO15 Weak internal pull-down. Do not pull high.
GPIO8 Weak internal pull-up. Do not pull low.
GPIO27 Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
2 2
USB Table
PCIE Routing
Pair Device
LANE1 LAN 0 USB3
LANE2 MiniCard1 1 USB2
2 USB4
LANE3 MiniCard2 3 MINICARD1
4 WECAM
5 Touch Panel
6 NC
7 NC
8 NC
9 USB1(HS)
10 Finger Print ENG DIS MADSION SAMSUNG
1 11 Blue Tooth 1
12 MINIC2 Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
13 Cardreader Taipei Hsien 221, Taiwan, R.O.C.
Title
Table of Content
Size Document Number Rev
A3
JV50-CP SA
Date: Tuesday, August 18, 2009 Sheet 2 of 57
A B C D E
1D5V_S0_CLKGEN
1D5V_S0_CLKGEN
1
1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C382 C372
1D5V_S0 R268 1 2
Do Not Stuff 1D05V_S0
2
2
DY
R2801 2
0R3J-0-U-GP
1 2 1D5V_S0_CLKGEN
3D3V_S0 3D3V_S0
R267
4 0R3J-0-U-GP 4
1 2 3D3V_CK505 3D3V_CK505_IO R281 1 2
C387 C390 Do Not Stuff
1
1
1
1
1
1
1
1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
R276 C375 C380 C379 C383
DY
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
0R3J-0-U-GP C371 C378
SC1U10V2ZY-GP
SC1U10V2ZY-GP
2
2
2
2
2
2
2
2
SA 0622 EMI
VGA_XIN1_L 1 2
OSC_SPREAD_L DY EC41 2 Do Not Stuff
24
17
29
15
18
1
1
5
U19 DY EC40 Do Not Stuff
VDDCPU_3_3
VDDSRC_3_3
VDDREF_3_3
VDDDOT96MHZ_3_3
VDDSRC_IO
VDDCPU_IO
VDD_27MHZ
DY
12 DREFCLK# 4 1 DREFCLK#_R 4 6 VGA_XIN1_L 4 1 RNT1 VGA_XIN1 63
RN34 DREFCLK_R DOT96C_LPR 27MHZ_NONSS OSC_SPREAD_L
12 DREFCLK 3 2 3 DOT96T_LPR 27MHZ_SS 7 3 2 Do Not Stuff OSC_SPREAD 63
SRN0J-10-GP-U
4 1 CLKIN_DMI#_R 14 3D3V_S0
12 CLKIN_DMI# RN38 SRCC1_LPR
12 CLKIN_DMI 3 2 CLKIN_DMI_R 13 16 CPU_STOP# R269 1 2 10KR2J-3-GP
SRN0J-10-GP-U SRCT1_LPR CPU_STOP# CLK_EN
CLKPWRGD/PD#_3_3 25
12 CLK_PCIE_SATA# RN37 4 1 CLK_PCIE_SATA#_R 11 30 FSC R260
1 2 33R2J-2-GP CLK_ICH14 12
SRN0J-10-GP-U 3 CLK_PCIE_SATA_R 10 SATAC_LPR REF_3L/FSLC_3_3
12 CLK_PCIE_SATA 2 SATAT_LPR
3