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1 1
Compal Confidential
2 2
PAWGC/D Schematics Document
AMD APU Ontario-FT1 + FCH Hudson-M1 + GPU Roberson XT
3
2010-11-10 3
REV:1.0
4 4
CIT RD Only
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 1 of 48
A B C D E
A B C D E
Compal confidential For PAWGC
File Name : PAWGC/D 1. POWER BOARD
2. Card Reader BOARD
For PAWGD
1 1
LVDS Conn. 1. POWER BOARD
page 10 Memory BUS(DDRIII) 200pin DDRII-SO-DIMM X2 2. Card reader BOARD
AMD Brazos APU Single Channel BANK 0, 1, 2, 3 page 8,9
CRT Conn. 3. 4*LED+SW(3pin)
1.5V DDRIII 1333
page 12 FT1
+SW(4pin) BOARD
BGA 413-Ball
HDMI Conn. 19mm x 19mm 4. ODD BOARD
AMD Robson page 11
page 5,6,7
VRAM 64*16 x4 PCI-E GPP GEN2
DDR3*4 x4 UMI Gen. 1
page 18 ~ 24 2.5GT/s per lane
2Channel Speaker
page 27
2
Audio Codec Internal MIC 2
page 27
Hudson M1 AZALIA CX20671
page 27
BGA 605-Ball Audio Jacks
23mm x 23mm Stereo
HeadPhone Output
4 * x1 PCI-E 2.0 14*USB2.0
Microphone Input
CMOS Camera page 10
WLAN &WiMax page 13,14,15,16,17 6*SATA serial BlueTooth CONN page 34
page 30
USB PORT 2.0 x3(Left) page 34
GIGA LAN LPC BUS
AR8151/8152 USB PORT 2.0 x1(Right) page 35
page 25,26
SPI ROM WLAN/WiMAX
3
page 15
EC 3
ENE KB930
page 31 Card Reader
PCI Express USB(WiMAX) Realtek RTS5139
SD/MMC/MS/MS Pro/XD
Mini card Slot 1 PCI-E(WLAN)
WLAN/WiMAX page 30
Int.KBD
page 32
ESATA HDD AND USB CONN
Touch Pad SPI ROM (Left) page 34
page 32 page 33
SATA3.0 HDD CONN
page 29
Thermal Sensor
4
EMC1403 page 28 SATA ODD CONN
page 29 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 2 of 48
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A B C D E
Voltage Rails FCH Hudson-M1 Brazos FCH Hudson-M1
Power Plane Description S1 S3 S5 USB Port List PCIE Port List SATA Port List
VIN Adapter power supply (19V) N/A N/A N/A USB1.1 PCIE0 SATA0 HDD
B+ AC or battery power rail for power circuit. N/A N/A N/A
Port0 NC PCIE1 SATA1 ODD
APU
+APU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF GPU
+APU_CORE_NB 1.0V switched power rail ON OFF OFF Port1 NC PCIE2 PCIE x4 SATA2 eSATA
1 1
+1.5V 1.5V power rail for CPU VDDIO and DDRIII ON ON OFF
USB2.0 PCIE3 SATA3 NC
+0.75VS 0.75VS switched power rail for DDR terminator ON OFF OFF
+1.0VS 1.0V switched power rail for NB VDDC & VGA ON OFF OFF Port0 Left USB1 PCIE0 LAN SATA4 NC
+1.1VS 1.1VS switched power rail ON OFF OFF
Port1 USB Camera PCIE1 WLAN SATA5 NC
FCH
+1.8VS 1.8V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON* Port2 Left(Combo) PCIE2 NC
+3V_LAN 3.3V power rail for LAN ON ON(WOL) OFF
Port3 Left USB2 PCIE3 NC
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON* Port4 Right USB
+5VS 5V switched power rail ON OFF OFF
Port5 BT
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON Port6 CardReader
+1.1VALW 1.1V always on power rail ON ON ON*
Port7 Mini-PCIE
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Port8 NC
2 Port9 NC BOM Structure 2
EC SM Bus1 address EC SM Bus2 address
Port10 NC
UMA@ : UMA only
Device Address HEX Device Address HEX
Port11 NC PX@ : DIS muxluss
Smart Battery 0001-011xb 15H EMC1412-2 (dGPU) 1111-100xb F8H
- PX3@ : PX3.0 only
EMC1403-2(DDR,WLAN) 1001-101xb 9AH Port12 NC - BACO@ : Baco only
SB-TSI 1001-100xb 98H
Port13 NC GIGA@ : AR8151
8152@ : AR8152
SM Bus Controller 0 (FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)
CMOS@ : USB camera
HDMI@ : HDMI function
Device Address HEX nonHDMI@ : w/o HDMI function
APU SIC/SID (FCH_SMB3)
ESATA@: eSATA function
H_THERMTRIP# (FCH_ALERT#)
BT@ : BT function
ME@ : ME components
X76@, H1G@, H512@, S1G@, S512@ : VRAM
45@ : 45 Level
3
SM Bus Controller 1 (FCH_SMB0)
HWM@ : hardware monitor function 3
nonHWM@: w/o hardware monitor function
Device Address HEX
DDR DIMM1 (FCH_SMB0) 1001-000xb 90
DDR DIMM2 (FCH_SMB0) 1001-001xb 92
WLAN (FCH_SMB0)
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 3 of 48
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5 4 3 2 1
Without BACO option :
Power-Up/Down Sequence PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation
1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
sequence, though a shorter ramp-up duration is preferred.
BACO option :
2. VDDR3 should ramp-up before or simultaneously with VDDC. PE_GPIO0 : High ->Normal operation (dGPU is not reset on BACO mode)
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
D DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
D
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA
VDD_CT have ramped up. DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
DPLL_PVDD, MPV18, and SPV18
ramp-up (or vice versa).)
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 575mA
SPV10
PCIE_VDDC 1.0V OFF ON 2A
VDDR3(3.3VGS) Note: Do not drive any IOs before VDDR3 is ramped up.
VDDR3 , and A2VDD 3.3V OFF ON 190mA
BIF_VDDC (current consumption = [email protected], in Same as OFF ON 70mA
PCIE_VDDC(1.0V) BACO mode) VDDC Same as
PCIE_VDDC
VDDR1 1.5V OFF OFF 2.8A
C
VDDR1(1.5VGS) VDDC/VDDCI 1.12V OFF OFF 12.9A C
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
PE_GPIO0 PE_EN BACO Switch
iGPU dGPU
PERSTb BIF_VDDC
PE_GPIO1
REFCLK PX_mode
B +3.3VALW MOS
+3.3VGS B
Straps Reset 1
+1.5V SI4800
+1.5VGS
Straps Valid +1.0V +1.0VGS
Regulator
2 3
Global ASIC Reset
+B Regulator
+VGA_CORE
+1.8V +1.8VGS
T4+16clock
SI4800
5 4
PWRGOOD
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/07/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
dGPU Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 4 of 48
5 4 3 2 1
5 4 3 2 1
U22B
+1.8VS C508 1 0.1U_0402_16V7K HDMI_TX2P_C R398 1 2 150_0402_1%
DISPLAYPORT 1
(11) HDMI_TX2P 2 A8 TDP1_TXP0 DP_ZVSS H3
C509 1 0.1U_0402_16V7K HDMI_TX2N_C
DP MISC
(11) HDMI_TX2N 2 B8
TDP1_TXN0
DP_BLON G2 APU_ENBKL (10)
C510 1 2 0.1U_0402_16V7K HDMI_TX1P_C B9 H2
(11) HDMI_TX1P TDP1_TXP1 DP_DIGON APU_ENVDD (10)
R404 2 1 300_0402_5% APU_DBREQ# C511 1 2 0.1U_0402_16V7K HDMI_TX1N_C A9 H1
D APU_SVC (11) HDMI_TX1N TDP1_TXN1 DP_VARY_BL APU_BLPWM (10) D
R399 1 2 1K_0402_5%
R400 1 2 1K_0402_5% APU_SVD C512 1 2 0.1U_0402_16V7K HDMI_TX0P_C D10
LDT_RST# (11) HDMI_TX0P HDMI_TX0N_C TDP1_TXP2 HDMI_CLK
R405 2 1 300_0402_5% C513 1 2 0.1U_0402_16V7K C10 B2
(11) HDMI_TX0N TDP1_TXN2 TDP1_AUXP HDMI_CLK (11)
R401 2 1 300_0402_5% APU_PWRGD C2 HDMI_DATA
TEST_25_L HDMI_CLKP_C TDP1_AUXN HDMI_DATA (11)
R402 1 2 510_0402_1% C514 1 2 0.1U_0402_16V7K A10
(11) HDMI_CLKP TDP1_TXP3
R403 1 2 1K_0402_5% TEST36 C515 1 2 0.1U_0402_16V7K HDMI_CLKN_C B10 C1
(11) HDMI_CLKN TDP1_TXN3 TDP1_HPD HDMI_DET (11)
B5 A3 EDID_CLK
(10) LVDS_A2 LTDP0_TXP0 LTDP0_AUXP EDID_CLK (10)
EDID_DATA
DISPLAYPORT 0
(10) LVDS_A2# A5 LTDP0_TXN0 LTDP0_AUXN B3 EDID_DATA (10)
D6 D3 R406 1 2 100K_0402_5%
(10) LVDS_A1 LTDP0_TXP1 LTDP0_HPD
(10) LVDS_A1# C6
LTDP0_TXN1
DAC_RED C12 DAC_RED (12)
A6 D13 R407 1 2 150_0402_1%
+3VS (10) LVDS_A0 LTDP0_TXP2 DAC_REDB
(10) LVDS_A0# B6 A12 DAC_GRN (12)
LTDP0_TXN2 DAC_GREEN R408 1
B12 2 150_0402_1%
DAC_GREENB
D8 A13
VGA DAC
HDMI_DATA (10) LVDS_ACLK LTDP0_TXP3 DAC_BLUE DAC_BLU (12)
R811 1 2 10K_0402_5% C8 B13 R409 1 2 150_0402_1%
(10) LVDS_ACLK# LTDP0_TXN3 DAC_BLUEB
R812 1 2 10K_0402_5% HDMI_CLK V2 E1
(13) APU_CLK CLKIN_H DAC_HSYNC CRT_HSYNC (12)
(13) APU_CLK# V1 E2 CRT_VSYNC (12)
R410 1 APU_PROCHOT# CLKIN_L DAC_VSYNC
2 1K_0402_5%
CLK
(13) DISP_CLK D2 DISP_CLKIN_H DAC_SCL F2 CRT_DDC_CLK (12)
R411 1 2 1K_0402_5% APU_ALERT#_R D1 D4
(13) DISP_CLK# DISP_CLKIN_L DAC_SDA CRT_DDC_DATA (12)
R412 1 2 1K_0402_5% APU_SIC J1 D12 R413 1 2 499_0402_1%
(44) APU_SVC SVC DAC_ZVSS
(44) APU_SVD J2
SVD
SER
R414 1 2 1K_0402_5% APU_SID R1 PAD T66
APU_SIC TEST4 AMD check list update
P3 SIC TEST5 R2 PAD T67
APU_SID P4 R6 20101110
SID TEST6
T5 PAD T68
TEST14 TEST15 R415 1 @
(13) LDT_RST# T3 E4 2 1K_0402_5%
C RESET_L TEST15 C
(13) APU_PWRGD T4 K4 PAD T69
CTRL
PWROK TEST16
L1 PAD T95