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PowerPC! 604 SMP Reference
Design Technical Specification
Release 3.0
This document provides a detailed
technical description of the PowerPC 604
SMP Reference Design. It is intended as
a first source of information for both
hardware and software designers. Where
appropriate, other documents are
referenced.
Document Number:
MPRZAPTSU-03
December 1995
R
" International Business Machines Corporation, 1995. Printed in the United States of America 12/95. All
Rights reserved.
IBM Microelectronics, PowerPC, PowerPC 603e, PowerPC 604, RISCWatch, and AIX are trademarks of the
IBM corporation. IBM and the IBM logo are registered trademarks of the IBM corporation. Other company
names and product identifiers are trademarks of the respective companies.
This document contains information which is subject to change by IBM without notice. IBM assumes no re-
sponsibility or liability for any use of the information contained herein. Nothing in this document shall operate
as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The
products described in this document are not intended for use in implantation or other direct life-support ap-
plications where malfunction may result in physical harm or injury to persons. NO WARRANTIES OF ANY
KIND, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR
FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
Contacts
IBM Microelectronics Division
1580 Route 52, Bldg. 504
Hopewell Junction, NY 12533-6531
Tel: (800) PowerPC
Fax: (800) PowerFax
http://www.chips.ibm.com
http://www.ibm.com
ftp://ftp.austin.ibm.com/pub/PPC_support
ESD Warning
The motherboard, CPU, and memory cards contain CMOS devices which are very suscep-
tible to ElectroStatic Discharge (ESD). DO NOT remove them from the antistatic bags until
you have connected yourself to an acceptable ESD grounding strap. Work in a static free
environment and be sure any person or equipment coming into contact with the cards does
not have a static charge. The cards are particularly susceptible until they are placed in a
properly designed enclosure. Bench work should be done by persons connected to ESD
grounding straps.
2 MPRZAPTSU-03
IBM POWERPC 604TM SMP REFERENCE DESIGN AGREEMENT
BEFORE READING THE REST OF THE DOCUMENT, YOU SHOULD CAREFULLY READ THE FOLLOWING TERMS
AND CONDITIONS. OPENING THE PACKAGE INDICATES YOUR ACCEPTANCE OF THESE TERMS AND CONDI-
TIONS. IF YOU DO NOT AGREE WITH THEM, YOU SHOULD PROMPTLY RETURN THE PACKAGE UNOPENED TO
YOUR IBM SALES OFFICE.
International Business Machines Corporation ("IBM") agrees to provide you a PowerPC 604 SMP Reference Design (Reference Design)
in return for your promise to use reasonable efforts to develop a system based on the technology in the Reference Design. The Reference
Design contains documentation and software listed below:
Documentation
PowerPC 604 SMP Reference Design Technical Specification
PowerPC 604 RISC Microprocessor Hardware Specification
IBM PowerPC 604 SMP Reference Board Design Files (on 8mm tape)
IBM PowerPC 604 SMP Reference Board Mfg. Data Files (in Gerber format)
IBM14N1372 Data Sheet
IBM11D4360B Data Sheet
Selected data sheets from other manufacturers (included with their permission).
LICENSE TO SOFTWARE
The software is licensed not sold. IBM, or the applicable IBM country organization, grants you a license for the software only in the country
where you received the software. Title to the physical software and documentation (not the information contained in such documentation)
transfers to you upon your acceptance of these terms and conditions. The term "software" means the original and all whole or partial copies
of it, including modified copies or portions merged into other programs. IBM retains title to the software. IBM owns, or has licensed from
the owner, copyrights to the software provided under this agreement. The terms of this Agreement apply to all of the hardware, software
and documentation provided to you as part of the Reference Design.
With regard to the software provided hereunder, it is understood and agreed that you intend to use the software solely for the purpose of
designing PowerPCTM compatible products, testing your designs, and making your own independent determination of whether you wish
to eventually manufacture PowerPC compatible products commercially. In accordance with this understanding, IBM hereby grants you
the rights to: a) use, run, and copy the software, but only make such number of copies and run on such number of machines as are reason-
ably necessary for the purpose of designing PowerPC compatible products and testing such designs; and b) copy the software for the pur-
pose of making one archival or backup copy.
With regard to any copy made in accordance with the foregoing license, you must reproduce any copyright notice appearing thereon. With
regard to the software provided hereunder, you may not: a) use, copy, modify or merge the software, except as provided in this license;
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wish to use the software, you will return it to IBM.
LICENSE TO DESIGN DOCUMENTATION
With regard to the design documentation provided hereunder, it is understood that you intend to use such documentation solely for the pur-
pose of designing your own PowerPC compatible products, testing your designs, and making your own independent determination of wheth-
er you wish to eventually manufacture PowerPC compatible products commercially. In accordance with this understanding, IBM hereby
grants you the right to: a) use the design documentation for the purpose of designing PowerPC compatible products and testing such de-
signs; b) make derivative works of the design documentation for the purpose of designing PowerPC compatible products, and testing such
designs; and c) make copies of the design documentation and any such derivative works, but only such numbers as are reasonably neces-
sary for designing PowerPC compatible products and testing such designs.
With regard to any copy made in accordance with the forgoing license, you must reproduce any copyright notice appearing thereon. With
regard to the design documentation provided hereunder, you may not: a) copy, modify, or merge the design documentation as provided
in this license; or b) sell, sublicense, rent, lease, assign, or otherwise transfer it.
In the event you no longer wish to use the design documentation or any derivative versions thereof, you must return them to IBM.
DISCLAIMER OF WARRANTY
IBM does not represent or warrant that the Reference Design (which may contain prototype items): a) meets any particular requirements;
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IBM makes no representation or warranty regarding the performance or compatibility that may be obtained from the use of the Reference
Design or that the Reference Design is adequate for any use. The Reference Design may contain errors and may not provide the level of
completeness, functionality, support, performance, reliability, or ease of use available with other products, whether or not similar to the Ref-
erence Design. IBM does not represent or warrant that errors or other defects will be identified or corrected.
THE REFERENCE DESIGN IS PROVIDED "AS IS" WITH ALL FAULTS, WITHOUT WARRANTY OF ANY KIND, EX-
PRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE
REFERENCE DESIGN IS WITH YOU.
Some jurisdictions do not allow exclusion of implied warranties, so the above exclusions may not apply to you.
MPRZAPTSU-03 3
LIMITATION OF REMEDIES
IBM's entire cumulative liability and your exclusive remedy for damages for all causes, claims or actions wherever and whenever asserted
relating in any way to the subject matter of this agreement including the contents of the Reference Design and any components thereof,
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ages, even if IBM has been advised of the possibility of such damages, or for any damages caused by your failure to perform your responsibi-
lities. In addition, IBM will not be liable for any damages claimed by you based on any third party claim. Some jurisdictions do not allow these
limitations or exclusions, so they may not apply to you.
RISK OF LOSS
You are responsible for all risk of loss or damage to the Reference Design upon its delivery to you.
IBM TRADEMARKS AND TRADE NAMES
This Agreement does not give you any rights to use any of IBM's trade names or trademarks. You agree that should IBM determine that
any of your advertising, promotional, or other materials are inaccurate or misleading with respect to IBM trademarks or trade names, that
you will, upon written notice from IBM, change or correct such materials at your expense.
NO IMPLIED LICENSE TO IBM INTELLECTUAL PROPERTY
Notwithstanding the fact that IBM is hereby providing design information for your convenience, you expressly understand and agree that,
except for the rights granted under the sections above, no right or license of any type is granted, expressly or impliedly, under any patents,
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of IBM intellectual property, when you seek the license.
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portion(s), where use of all or any part of the Reference Design is involved. You are solely responsible for any claims, warranties, represen-
tations, indemnities and liabilities you undertake with your customers, distributors, resellers or others, concerning any product(s) or por-
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cost, reliability, maintainability, quality, manufacturability or the like, requirements, or goals, self-imposed by you or accepted by you from
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the like, resulting from such non-attainment, where use of all or any part of the Reference Design is involved.
GENERAL
In the event there is a conflict between the terms of this Agreement and the terms printed or stamped on any item or any ambiguities with
respect thereto, including documentation, contained in the Reference Design, the terms of this Agreement control to the extent IBM is af-
forded greater protection thereby. IBM may terminate this Agreement if you fail to comply with the terms and conditions of this Agreement.
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ence Design in Canada, this Agreement is governed by the laws of the Province of Ontario; otherwise, this Agreement is governed by the
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in any respect for any reason, the validity, legality, and enforceability of any such section or paragraph in every other respect, and the remain-
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ness planning information to you. You agree to comply with all applicable government laws and regulations. Any changes to this Agreement
must be in writing and signed by the parties.
4 MPRZAPTSU-03
Table of Contents
Section 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1 IBM Reference Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1.1 Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1.2 Reference Boards and Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1.3 Reference Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.3 Differences Between Release 1.0 and Release 3.0 . . . . . . . . . . . . . . . . . 24
1.4 Reference Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4.1 Processor Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4.2 Other CEC Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4.3 IBM27-82660 Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4.4 L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4.5 System Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4.6 PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4.7 SCSI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4.8 Network Support AMD AM79C970A (Ethernet) . . . . . . . . . . . . . . . . . 28
1.4.9 Multi-Processor Interrupt Controller (MPIC) . . . . . . . . . . . . . . . . . . . . . 28
1.4.10 Flash ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4.11 PCI/ISA Bridge Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.4.12 Business Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.4.13 Native I/O Controller National PC87332 Super I/O . . . . . . . . . . . . . . . 30
1.4.14 X Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.4.15 Time of Day Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.4.16 PS/2 Compatible Keyboard/Mouse Controller . . . . . . . . . . . . . . . . . . . 30
1.4.17 System I/O EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.4.18 System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5 Quickstart Peripheral List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Section 2 CPU Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.1 CPU Busmasters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.1.1 CPU Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.1.2 Fast L2/Data Streaming Mode (No-DRTRY#) . . . . . . . . . . . . . . . . . . . 34
2.1.3 CPU Bus Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.1.4 Bi-Endian Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2 System Response by CPU Bus Transfer Type . . . . . . . . . . . . . . . . . . . . . 35
2.3 System Response by CPU Bus Address Range . . . . . . . . . . . . . . . . . . . . 36
2.3.1 Address Mapping for Contiguous I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.2 Address Mapping for Non-Contiguous I/O . . . . . . . . . . . . . . . . . . . . . . 38
2.3.3 PCI Final Address Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.4 CPU to Memory Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.4.1 LE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
MPRZAPTSU-03 5
2.5 CPU to PCI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.5.1 CPU to PCI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.5.2 CPU to PCI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.5.2.1 Eight-Byte Writes to the PCI (Memory and I/O) . . . . . . . . . . . . . . . . . 40
2.5.3 CPU to PCI Memory Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.5.4 CPU to PCI I/O Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.5.5 CPU to PCI Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . 40
2.5.6 CPU to PCI Interrupt Acknowledge Transaction . . . . . . . . . . . . . . . . . 41
2.5.7 PCI Locks and CPU Reservations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.6 CPU to ROM Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.6.1 CPU to ROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.6.2 CPU to ROM Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.6.2.1 ROM Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.6.3 CPU to BCR Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.7 CPU Card Interface (CPU Slot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.7.1 CPU Slot Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.7.2 CPU Slot DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.7.3 CPU Slot AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.7.4 CPU Slot Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.7.5 CPU Slot Thermal Envelope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.7.6 CPU Slot Card Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.7.7 Auxiliary CPU Slot Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.8 L2 Tag/SRAM Interface (L2 Slot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.8.1 L2 Slot ID ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.8.1.1 L2 Cache ID ROM Signaling Interface . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.8.2 L2 Slot Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.8.3 L2 Slot DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.8.4 L2 Slot AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.8.5 L2 Slot Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.8.6 L2 Slot Thermal Envelope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.8.7 L2 Slot Dual Voltage Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.8.8 L2 Slot Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.8.9 L2 Slot Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.9 JTAG/RISCWatch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.10 Electrical Model of Major Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.10.1 Motherboard Electrical Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.10.2 CPU Card and L2 Card Interface Models . . . . . . . . . . . . . . . . . . . . . . . 80
2.10.3 CPU Card Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.10.4 L2 Card Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.10.5 660 Bridge Electrical Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.10.6 Model Building . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Section 3 Endian Mode Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.1 What the 604 CPU Does . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.1.1 The 604 Address Munge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6 MPRZAPTSU-03
3.1.2 The 604 Data Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.2 What the 660 Bridge Does . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.2.1 The 660 Bridge Address Unmunge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.2.2 The 660 Bridge Data Swapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.3 Bit Ordering Within Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.4 Byte Swap Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.5 604 CPU Alignment Exceptions In LE Mode . . . . . . . . . . . . . . . . . . . . . . . 87
3.6 Single-Byte Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.7 Two-Byte Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.8 Four-Byte Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.9 Three byte Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.10 Instruction Fetches and Endian Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.11 Changing BE/LE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.12 Summary of Bi-Endian Operation and Notes . . . . . . . . . . . . . . . . . . . . . . . 100
Section 4 CPU Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.1 Major Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.1.1 PowerPC 604 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.1.2 JTAG/RISCWatch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.1.3 J2 Auxiliary Test Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.1.4 Fansink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2 Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.2.1 Bus Clock Skew Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.2.2 2.5v Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.2.3 Presence Detect Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.2.4 DRVMOD Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.2.5 Additional Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.3 Electrical and Thermal Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.3.2 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.3.3 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.3.4 AC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.4 Electrical Model of Major Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.5 CPU Card Slot Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.5.1 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Section 5 DRAM and ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.1 DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.1.1 Memory Controller (DRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.1.2 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.1.3 Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.1.4 DRAM Presence Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.1.5 DRAM Bank Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.2 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.2.1 PCI Bus ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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5.2.2 Remote ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.2.3 ROM Read, Write, and Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Section 6 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.1.1 PCI interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.1.2 ISA interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.1.3 CPU to CPU Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.1.4 PCI Interrupt Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.1.5 ISA Interrupt Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.1.5.1 Scatter/Gather (SG) Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.1.6 SCSI Bus Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.1.7 MCP# Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.1.8 SMI# Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.2.1 HRESET# Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.2.1.1 JTAG Interface Hard Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.2.1.2 HRESET PAL Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.2.2 SRESET Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.2.3 SRESET PAL equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.3 SMP Reset Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.1 Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.1.1 Hard Reset Phase 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.1.2 Hard Reset Phase 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.1.3 Hard Reset Phase 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.2 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.4 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.4.1 Data Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.4.1.1 CPU to Memory Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.4.1.2 CPU to Memory Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.4.1.3 PCI to Memory Parity Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.4.1.4 CPU to PCI Transaction Data Parity Errors . . . . . . . . . . . . . . . . . . . . 133
6.4.2 Illegal CPU cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.4.3 SERR, I/O Channel Check, and NMI Logic . . . . . . . . . . . . . . . . . . . . . . 133
6.4.4 Out of Bounds PCI Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.4.5 No Response on CPU to PCI Cycles -- Master Abort . . . . . . . . . . . . 133
6.4.6 CPU to PCI Cycles That Are Target Aborted . . . . . . . . . . . . . . . . . . . . 134
6.4.7 Error Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.4.8 Reporting Error Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.4.9 Errant Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.4.10 Special Events Not Reported as Errors . . . . . . . . . . . . . . . . . . . . . . . . . 135
Section 7 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.1 CPU Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.1.1 CPU Card Clock Repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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7.1.2 CPU Clock Physical Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.2 CPU Clock Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.2.1 Clock Logic Input