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DIS V03A DIS/UMA BLOCK DIAGRAM
DDRIII-SODIMM1 DDRIII 1333 MT/s
A 00 PAGE 16 Nvidia
A
PCIEx16 A
CPU N12P-GE (128bit)
DDRIII-SODIMM2 DDRIII 1333 MT/s 29mm X 29mm
Sandy Bridge 45W BGA 969
A 01 PAGE 17
PGA 989
PAGE 18~22
PAGE 4~8
DDR3 1GB/2GB PAGE 26 PAGE 26
FDI LINK DMI LINK 128Mx16bitx8
2.5GT /s 2.5GT /s PG 23,24
iGFX Interfaces
SATA4 300MB /S
PAGE 27
B 1600 x 900 (HD) PAGE 25 B
PAGE 27
SATA0 300MB /S
Mobile Intel
PAGE 28
PAGE 27 PAGE 25 PAGE 29 PAGE 35 PAGE 34
Series 6 Chipset
USB2.0 USB[0] USB[11] USB[8] USB[10] USB[12]
SATA1 300MB /S
USB[8]
PAGE 28 PCH
PAGE 03 IO Board PAGE 02
SMBUS HM67
PAGE 28
USB[4] USB[5] PCIE[3] EXP Board
Couger Point
PAGE 05 PAGE 04 PAGE 06 LED Board Charger
PAGE 42
PCIE[1] PCIE[2]
BGA 989
PCIE[5] 3/5V
C
25 mm X 25 mm PAGE 05 PAGE 07
PB Board PAGE 43 C
USB[6] 1.5V_SUS/0.75V_DDR
32.768KHz PAGE 44
PAGE 08
TP Board
Batt/DC-IN
IHDA PAGE 09 USB[2] PAGE 41
LPC PAGE 9~15
PAGE 35
PAGE 10 HotKey Board 1.05V_PCH
25MHz PAGE 45
SPI VCCSA
PAGE 35 PAGE 46
25MHz 32.768KHz
DGFX_CORE
PAGE 30 PAGE 48
PAGE 34
PAGE 36
PAGE 32
CPU_CORE
PAGE 47
D D
1.8V_RUN
PAGE 45
PAGE 38 PAGE 34 PAGE 32 PAGE 32 PAGE 32
PAGE 33
Quanta Computer Inc.
PROJECT : R03A/V03A
Size Document Number Rev
2A
BLOCK DIAGRAM
Date: Friday, December 31, 2010 Sheet 1 of 50
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+RTC_CELL +DC_IN +VCHGR +5V_SUS +VCC_CORE
+DC_IN_SS +PWR_SRC +3.3V_SUS +VCC_GFX_CORE
power +PWR_SRC +5V_ALW_2 +1.5V_SUS +1.05V_PCH
+5V_ALW_2 +3.3V_ALW +1.5V_CPU +5V_RUN
+3.3V_ALW +5V_ALW +DDR_VTTREF +3.3V_RUN
+5V_ALW +15V_ALW
+3.3V_LAN (for R03) +1.8V_RUN
A
+15V_ALW +3.3V_LAN (for V03) A
+3.3V_LAN (for V03) +1.5V_RUN
+VCCSA
+0.75V_DDR_VTT
+LCDVCC
State +VCC_DGFX_CORE
ON ON ON ON ON
S0
S1
S3 ON ON ON ON OFF
B B
ON ON
S4/S5 AC
S4/S5 ON ON OFF OFF
DC Only
AC/DC ON OFF OFF OFF OFF
No Exist
C C
SMBCLK
SMBDATA
SMB_CLK_ME1
SMB_DAT_ME1
AB1A_CLK
AB1A_DATA
D D
Quanta Computer Inc.
PROJECT : R03A/V03A
Size Document Number Rev
2A
Power Rails
Date: W ednesday, October 27, 2010 Sheet 2 of 50
1 2 3 4 5 6 7 8
5 4 3 2 1
D D
C C
B B
A A
Quanta Computer Inc.
PROJECT : R03A/V03A
Size Document Number Rev
2A
BLANK
Date: W ednesday, October 06, 2010 Sheet 3 of 50
5 4 3 2 1
5 4 3 2 1
DP & PEG Compensation
+1.05V_PCH
Sandy Bridge Processor (DMI,PEG,FDI)
U17A
PEG_ICOMPO 12mil
D J22 PEG_COMP PEG_ICOMPI, PEG_RCOMPO 4mil, D
PEG_ICOMPI R309 24.9/F_4 EDP_COMP
PEG_ICOMPO J21
[9] DMI_TXN0 B27 DMI_RX#[0] PEG_RCOMPO H22
[9] DMI_TXN1 B25 DMI_RX#[1] PEG_RXN[0..15] [18] eDP_COMPIO and ICOMPO signals should
[9] DMI_TXN2 A25 DMI_RX#[2] be shorted near balls and
B24 K33 PEG_RXN0
[9] DMI_TXN3 DMI_RX#[3] PEG_RX#[0] routed within 500 mils
M35 PEG_RXN1
PEG_RX#[1] PEG_RXN2
[9] DMI_TXP0 B28 DMI_RX[0] PEG_RX#[2] L34
B26 J35 PEG_RXN3
[9] DMI_TXP1 DMI_RX[1] PEG_RX#[3]
DMI
A24 J32 PEG_RXN4
[9] DMI_TXP2 DMI_RX[2] PEG_RX#[4] +1.05V_PCH
B23 H34 PEG_RXN5
[9] DMI_TXP3 DMI_RX[3] PEG_RX#[5]
H31 PEG_RXN6
PEG_RX#[6] PEG_RXN7
[9] DMI_RXN0 G21 DMI_TX#[0] PEG_RX#[7] G33
E22 G30 PEG_RXN8
[9] DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PEG_RXN9 R55 24.9/F_4 PEG_COMP
[9] DMI_RXN2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PEG_RXN10
[9] DMI_RXN3 DMI_TX#[3] PEG_RX#[10]
E32 PEG_RXN11
PEG_RX#[11] PEG_RXN12
[9] DMI_RXP0 G22 DMI_TX[0] PEG_RX#[12] D33
D22 D31 PEG_RXN13
[9] DMI_RXP1 DMI_TX[1] PEG_RX#[13]
PCI EXPRESS* - GRAPHICS
F20 B33 PEG_RXN14
[9] DMI_RXP2 DMI_TX[2] PEG_RX#[14]
C21 C32 PEG_RXN15 PEG_RXP[0..15] [18] PEG_ICOMPI and RCOMPO signals should
[9] DMI_RXP3 DMI_TX[3] PEG_RX#[15]
be routed within 500 mils
J33 PEG_RXP0
PEG_RX[0] PEG_RXP1
PEG_RX[1] L35
K34 PEG_RXP2 PEG_ICOMPO signals should
PEG_RX[2] PEG_RXP3
[9] FDI_TXN0 A21 FDI0_TX#[0] PEG_RX[3] H35 be routed within 500 mils
H19 H32 PEG_RXP4
[9] FDI_TXN1 FDI0_TX#[1] PEG_RX[4]
E19 G34 PEG_RXP5
[9] FDI_TXN2 FDI0_TX#[2] PEG_RX[5]
F18 G31 PEG_RXP6
Intel(R) FDI
[9] FDI_TXN3 FDI0_TX#[3] PEG_RX[6]
C B21 F33 PEG_RXP7 C
[9] FDI_TXN4 FDI1_TX#[0] PEG_RX[7]
C20 F30 PEG_RXP8
[9] FDI_TXN5 FDI1_TX#[1] PEG_RX[8]
D18 E35 PEG_RXP9
[9] FDI_TXN6 FDI1_TX#[2] PEG_RX[9]
E17 E33 PEG_RXP10
[9] FDI_TXN7 FDI1_TX#[3] PEG_RX[10]
F32 PEG_RXP11
PEG_RX[11] PEG_RXP12
PEG_RX[12] D34
A22 E31 PEG_RXP13
[9] FDI_TXP0 FDI0_TX[0] PEG_RX[13]
G19 C33 PEG_RXP14
[9]
[9]
FDI_TXP1
FDI_TXP2 E20
FDI0_TX[1]
FDI0_TX[2]
PEG_RX[14]
PEG_RX[15] B32 PEG_RXP15
PEG_TXN[0..15] [18]
eDP Hot-plug (Disable)
[9] FDI_TXP3 G18 FDI0_TX[3]
B20 M29 PEG_TXN0_C C214 0.1U/10V_4 PEG_TXN0
[9] FDI_TXP4 FDI1_TX[0] PEG_TX#[0] +1.05V_PCH
C19 M32 PEG_TXN1_C C184 0.1U/10V_4 PEG_TXN1
[9] FDI_TXP5 FDI1_TX[1] PEG_TX#[1]
D19 M31 PEG_TXN2_C C173 0.1U/10V_4 PEG_TXN2
[9] FDI_TXP6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PEG_TXN3_C C158 0.1U/10V_4 PEG_TXN3
[9] FDI_TXP7 FDI1_TX[3] PEG_TX#[3]
L29 PEG_TXN4_C C129 0.1U/10V_4 PEG_TXN4
PEG_TX#[4] PEG_TXN5_C C141 0.1U/10V_4 PEG_TXN5
[9] FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31
J17 K28 PEG_TXN6_C C101 0.1U/10V_4 PEG_TXN6 R304
[9] FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6]
J30 PEG_TXN7_C C78 0.1U/10V_4 PEG_TXN7 *10K_4_NC
PEG_TX#[7] PEG_TXN8_C C61 0.1U/10V_4 PEG_TXN8
[9] FDI_INT H20 FDI_INT PEG_TX#[8] J28
H29 PEG_TXN9_C C69 0.1U/10V_4 PEG_TXN9
PEG_TX#[9] PEG_TXN10_C C53 0.1U/10V_4 PEG_TXN10 INT_EDP_HPD
[9] FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#[10] G27
H17 E29 PEG_TXN11_C C45 0.1U/10V_4 PEG_TXN11
[9] FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
F27 PEG_TXN12_C C39 0.1U/10V_4 PEG_TXN12
PEG_TX#[12] PEG_TXN13_C C38 0.1U/10V_4 PEG_TXN13
PEG_TX#[13] D28
F26 PEG_TXN14_C C34 0.1U/10V_4 PEG_TXN14
PEG_TX#[14] PEG_TXN15_C C29 0.1U/10V_4 PEG_TXN15
PEG_TX#[15] E25 PEG_TXP[0..15] [18] CAD Note: Place PU resistor within 2 inches
eDP_ICOMPO 12mil EDP_COMP
A18 eDP_COMPIO PEG_TXP0_C C232 0.1U/10V_4 PEG_TXP0 of CPU
A17 eDP_ICOMPO PEG_TX[0] M28
eDP_COMPIO 4mil INT_EDP_HPD B16 M33 PEG_TXP1_C C203 0.1U/10V_4 PEG_TXP1
B eDP_HPD PEG_TX[1] PEG_TXP2_C C169 0.1U/10V_4 PEG_TXP2 B
PEG_TX[2] M30
PEG_TXP3_C C157 0.1U/10V_4 PEG_TXP3
This signal can be left as no connect if
PEG_TX[3] L31
C15 L28 PEG_TXP4_C C128 0.1U/10V_4 PEG_TXP4 entire eDP interface is disabled.
eDP_AUX PEG_TX[4] PEG_TXP5_C C140 0.1U/10V_4 PEG_TXP5
D15 eDP_AUX# PEG_TX[5] K30
eDP
K27 PEG_TXP6_C C100 0.1U/10V_4 PEG_TXP6
PEG_TX[6] PEG_TXP7_C C75 0.1U/10V_4 PEG_TXP7
PEG_TX[7] J29
C17 J27 PEG_TXP8_C C66 0.1U/10V_4 PEG_TXP8
eDP_TX[0] PEG_TX[8] PEG_TXP9_C C68 0.1U/10V_4 PEG_TXP9
F16 eDP_TX[1] PEG_TX[9] H28
Programing Disable eDP interface(BIOS) C16 G28 PEG_TXP10_C C47 0.1U/10V_4 PEG_TXP10
eDP_TX[2] PEG_TX[10] PEG_TXP11_C C41 0.1U/10V_4 PEG_TXP11
G15 eDP_TX[3] PEG_TX[11] E28
F28 PEG_TXP12_C C40 0.1U/10V_4 PEG_TXP12
PEG_TX[12] PEG_TXP13_C C35 0.1U/10V_4 PEG_TXP13
C18 eDP_TX#[0] PEG_TX[13] D27
E16 E26 PEG_TXP14_C C33 0.1U/10V_4 PEG_TXP14
eDP_TX#[1] PEG_TX[14] PEG_TXP15_C C27 0.1U/10V_4 PEG_TXP15
D16 eDP_TX#[2] PEG_TX[15] D25
F15 eDP_TX#[3]
0.22uF AC coupling Caps for PCIE GEN1/2/3
Sandy Bridge_rPGA_4SODIMM_Rev1p0
A A
Quanta Computer Inc.
PROJECT : R03A/V03A
Size Document Number Rev
2A
Sandy Bridge 1/5
Date: Friday, January 07, 2011 Sheet 4 of 50
5 4 3 2 1
5 4 3 2 1
Sandy Bridge Processor (CLK,MISC,JTAG)
U17B
BCLK A28 CLK_CPU_BCLKP [13]
MISC
CLOCKS
TP43 C26 PROC_SELECT# BCLK# A27 CLK_CPU_BCLKN [13]
+1.05V_PCH
R186 62/F_4 H_PROCHOT# AN34 R310 1K_4
D [30] H_CPUDET# SKTOCC#
A16 CLK_DP_P_R R305 *0_4_NC CLK_DP_P [13]
Schematic C/L_v1.0, P56 (PU,PD 1k/J) D
DPLL_REF_CLK CLK_DP_N_R R306 *0_4_NC
DPLL_REF_CLK# A15
R311 1K_4
CLK_DP_N [13] (Intel and PD3)
+1.05V_PCH
Reserve (Intel confirm now)
TP_CATERR# AL33
TP34 CATERR#
THERMAL
[30] PECI_EC R445 43/J_4 H_PECI_R AN33 R8 CPU_DRAMRST#
PECI SM_DRAMRST#
DDR3
MISC
[30,42,47] H_PROCHOT# R181 56/J_4 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R153 140/F_4
PROCHOT# SM_RCOMP[0] SM_RCOMP_1 R312 25.5/F_4
SM_RCOMP[1] A5
SM_RCOMP_2 R313 200/F_4
SM_RCOMP_0, SM_RCOMP_1 20mil
SM_RCOMP[2] A4
SM_RCOMP_2 15mil,
Over 130 degree C will [14] PM_THRMTRIP# AN32 THERMTRIP#
drive low
+1.05V_PCH
PRDY# AP29
PREQ# AP27
XDP_TMS R452 51/J_4
AR26 XDP_TCLK XDP_TDI R450 51/J_4
TCK
PWR MANAGEMENT
XDP_TMS XDP_TDO R201 51/J_4
JTAG & BPM
TMS AR27
[9] H_PM_SYNC AM34 AP30 XDP_TRST# R447 51/J_4
PM_SYNC TRST#
C AR28 XDP_TDI C
TDI XDP_TDO XDP_TCLK R202 51/J_4
TDO AP26
[14] H_PW RGOOD AP33 +3.3V_RUN
UNCOREPWRGOOD
R189 10K/J_4
AL35 XDP_DBRST# R443 1K_4
SM_DRAMPW ROK DBR#
V8 SM_DRAMPWROK
XDP_DBRST# use a 1k pull-up to 3.3V_S
BPM#[0] AT28 TRST# use a 51ohm pull down.
+1.05V_PCH R192 *75/J_4_NC AR29
BPM#[1]
BPM#[2] AR30
CPU_PLTRST# R193 *43/J_4_NC
CPU_PLTRST#_R AR33 AT30
RESET# BPM#[3]
BPM#[4] AP32
BPM#[5] AR31
+3.3V_SUS AT31
BPM#[6]
IN OUT BPM#[7] AR32
L L
H High-Z C333
U8 *0.1U/10V/X7R_4_NC Sandy Bridge_rPGA_4SODIMM_Rev1p0
1 NC VCC 5
[12,18,30,31] PLTRST# 2 IN Boot S3 S3 RSM
3 4 CPU_PLTRST#
GND OUT
R556 *74LVC1G07GW _NC
B
1.5K +1.5V_CPU B
1%
CPU_PLTRST#_R voltage level Ckt.
DRAM_PWRGD
CPU_PLTRST#_R
100 ns after +1.5V_CPU
1% SYS_PWROK reaches 80%
750
SM_DRAMPWROK
R557
Follow #DG1.0 436735 P107 +1.5V_SUS
DRAMRST# Routing Illustration
R72 R54 *0_4_NC
1K/F_4
Change OD part same with PDC R8239, R8241 change to 5% R63 Q5 BSS138-7-F
1K/F_4
Pin1 Pin2 Pin4 DDR3_DRAMRST#_R 3 1 CPU_DRAMRST#
Copy from PDC +3.3V_SUS [16,17] DDR3_DRAMRST#
L L L
2
+1.5V_CPU
L H L