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5 4 3 2 1
ZY7 SYSTEM BLOCK DIAGRAM
CPU CORE ISL6265A
PAGE 29
D D
NB CORE (RT8202) DDRII-SODIMM1 DDRII 667/800 MHz Lion CPU THERMAL CPU Fan
PAGE XX PAGE 7 AMD Griffin Sabie SENSOR
S1G2 Processor PAGE 5 14.318MHz
DDR II SMDDR_VTERM
DDRII-SODIMM2 DDRII 667/800 MHz 638P (uPGA)/35W
1.8VSUS(TPS51116REGR) PAGE 7 PAGE 3,4,5,6 CPU_CLK
PAGE 31
LVDS LVDS NBGFX_CLK CLOCK GEN
PAGE 18 NBGPP_CLK ICS9LPRS476AKLFT-->HP
SYSTEM POWER
HT3 SBLINK_CLK SLG8SP626VTR-->HP
ISL6237 LINK
RTM880N-795 -->HP
PAGE 28 PAGE 2
SYSTEM CHARGER MXM PCI-E
CRT
(ISL6251A)
PAGE 27
SWITCH Connector NORTH BRIDGE PCIE2 / 3
X2
PCIE1
X1
PCIE4
X1
PCIE5
X1
HDMI PCI-Express 16X
PAGE 17 RX780 / RS780M Mini PCI-E Express LAN JMB385 4 IN 1
CARD READER
21mm X 21mm, 528pin BGA Card Card PCIE-LAN RJ45
Wireless /TV
Internal LVDS (NEW CARD) BCM5764M PAGE 21
C
DVI-D HDMI selector (10/100/GagaLAN)
C
CRT
PAGE 26 PAGE 18
Resistor HDMI PAGE 19 PAGE 19 PAGE 21 PAGE 24
PAGE 8,9,10,11
PAGE 17
CRT CRT
PAGE 26 PAGE 18 PCIE X4 SBSRC_CLK
1,11 5
AUDIO SATA - HDD
M/B USB2.0
PAGE 26
PAGE 20 SATA0 3,4 6 2 10 7
8,0
LAN SOUTH BRIDGE
USB2.0 Ports Bluetooth PC-cam Fingerprint USB Docking
PAGE 26
SATA - HDD SB700 x4 PAGE 19 x1 PAGE 19 x1 PAGE 18 x1 PAGE 19 x1 PAGE 19
PAGE 20 SATA1
USB 21mm X 21mm, 528pin BGA
PCI BUS / 33MHz O2 OZ601 PCMCIA
PAGE 26 4.5W(Ext) CARD BUS
PAGE 23
4.3W(Int) PAGE 23
ODD(SATA)
DOCKING PAGE 20 SATA4 PAGE 12,13,14,15,16 Azalia
PCI ROUTING
TABLE IDSEL INTERUPT DEVICE
B REQ0# / GNT0# AD20 INTF# OZ601 B
LPC Azalia AudioController MDC 1.5
RealTek ALC268
PAGE 22
PAGE 22
Keyboard
PAGE 25 KBC
(WPCE775)
Audio
Int MIC
Amplifier
PCB STACK UP PAGE 25
LAYER 1 : TOP
LAYER 2 : SGND Speaker SPIDF/Phone Line in MIC Jack
Jack
LAYER 3 : IN1 Touch SPI
Pad ROM
LAYER 4 : IN2 PAGE 20 PAGE 25
LAYER 5 : SVCC
A LAYER 6 : BOT A
Quanta Computer Inc.
PROJECT : ZY7
Size Document Number Rev
1A
Block Diagram
Date: Thursday, June 26, 2008 Sheet 1 of 35
5 4 3 2 1
5 4 3 2 1
CLK_GEN_SLG8SP628
+3V +3V_CLK_VDD +1.2V +1.2V_CLK_VDDIO
L39 L42
BK1608HS600 BK1608HS600
C365 C373 C364 C394 C409 C390 C402 C381 C405 C378 C406 C408 C374 C389
C399 C407
D 22U-10V_8 .1u/10V_4 .1u/10V_4 .1u/10V_4 .1u/10V_4 .1u/10V_4 .1u/10V_4 .1u/10V_4 .1u/10V_4 22U-10V_8 .1u/10V_4 .1u/10V_4 .1u/10V_4 .1u/10V_4 .1u/10V_4 .1u/10V_4 D
Change C1000/C1008 from 10u to 22u.-1001
ICS9LPRS480 P/N : Clock chip has internal serial terminations
for differencial pairs, external resistors are
SLG8SP628 P/N : AL8SP628000 reserved for debug purpose.
RTM880N-796 P/N : AL000880000
Place within 0.5" CHECK
of CLKGEN R255
U14
*261/F_4
4 50 CPUCLKP_R RP25 1 2 0X2 CPU_CLKP
+3V_CLK_VDD VDDDOT CPUK8_0T CPU_CLKP 5
16 49 CPUCLKN_R 3 4 CPU_CLKN To CPU
VDDSRC CPUK8_0C CPU_CLKN 5
26 VDDATIG
35 VDDSB_SRC
40 30 NBGFX_CLKP_R RP35 1 2 0X2
VDDSATA ATIG0T NBGFX_CLKP 10
48 29 NBGFX_CLKN_R 3 4 To NB
+3V +3V_CLK_48 VDDCPU ATIG0C NBGFX_CLKN 10
55 28 CLK_PCIE_MXM_R RP34 1 2 *EV^0X2
VDDHTT ATIG1T CLK_PCIE_MXM 17
L38 56 27 CLK_PCIE_MXM#_R 3 4 To MXM Card
VDDREF ATIG1C CLK_PCIE_MXM# 17
63 VDD48
BK1608HS600 External VGA Card only
1
C 37 SBLINK_CLKP_R RP30 1 2 0X2 C
SB_SRC0T SBLINK_CLKP 10
C363 11 36 SBLINK_CLKN_R 3 4 To NB
+1.2V_CLK_VDDIO VDDSRC_IO0 SB_SRC0C SBLINK_CLKN 10
2.2U/6.3V/06 17 32 SBSRC_CLKP_R RP36 1 2 0X2 SBSRC_CLKP 12
2
VDDSRC_IO1 SB_SRC1T SBSRC_CLKN_R To SB
25 VDDATIG_IO SB_SRC1C 31 3 4 SBSRC_CLKN 12
34 VDDSB_SRC_IO
47 VDDCPU_IO
C367 22 NBGPP_CLKP_R RP33 1 2 *EV^0X2
SRC0T NBGPP_CLKP 10
CG_XIN 21 NBGPP_CLKN_R 3 4
SRC0C NBGPP_CLKN 10
1 20 CLK_PCIE_NEW_R RP32 1 2 0X2
GND48 SRC1T CLK_PCIE_NEW 19
2
20p/50V_4 7 19 CLK_PCIE_NEW#_R 3 4 To New Card
GNDDOT SRC1C CLK_PCIE_NEW# 19
Y3 10 15 CLK_PCIE_MINI_R RP31 1 2 0X2
GNDSRC0 SRC2T CLK_PCIE_MINI 19
14.318MHZ 18 14 CLK_PCIE_MINI#_R 3 4 To Mini PCIE Slot
GNDSRC1 SRC2C CLK_PCIE_MINI# 19
C366 CLK_PCIE_TV_R RP29 0X2
24 QFN64 13 1 2 CLK_PCIE_TV 19
1
CG_XOUT GNDATIG SRC3T CLK_PCIE_TV#_R To TV PCIE Slot
33 GNDSB_SRC SRC3C 12 3 4 CLK_PCIE_TV# 19
43 9 CLK_PCIE_LAN_R RP27 1 2 0X2
GNDSATA SRC4T CLK_PCIE_LAN 21
20p/50V_4 46 8 CLK_PCIE_LAN#_R 3 4 To LAN Controller
GNDCPU SRC4C CLK_PCIE_LAN# 21
52 GNDHTT
60
Follow CLK 14.318 Check 20p 11/19 GNDREF
SRC6T/SATAT
SRC6C/SATAC
42
41
CLK_PCIE_CR_R
CLK_PCIE_CR#_R
RP28 1
3
2 0X2
4
CLK_PCIE_CR 24
CLK_PCIE_CR# 24
To Card Reader Controller
CG_XIN 61 6 T82
+3V_CLK_VDD CG_XOUT X1 SRC7T/27M_SS
62 X2 SRC7C/27M_NS 5 T81
R272 8.2K_4 NEW_CLKREQ#
R286 8.2K_4 LAN_CLKREQ# CGCLK_SMB 2 54 NBHT_REFCLKP_R RP26 1 2 0X2
SMBCLK HTT0T/66M NBHT_REFCLKP 10
R264 8.2K_4 CLK_PD# CGDAT_SMB 3 53 NBHT_REFCLKN_R 3 4 To NB
SMBDAT HTT0C/66M NBHT_REFCLKN 10
R277 8.2K_4 MINI_CLKREQ# CLK_48M_USB_R C372 *10p_4
R283 8.2K_4 TV_CLKREQ#
CLK_PD# 51 64 CLK_48M_USB_R R268 33_4 To SB SEL_27 C350 22P/50V_4
PD# 48MHz_0 CLK_48M_USB 13
T87 23 59 SEL_HTT66
B CLKREQ0# REF0/SEL_HTT66 SEL_SATA B
13,19 NEW_CLKREQ# 45 CLKREQ1# REF1/SEL_SATA 58 REV B:Change to Stuff 22PF for
New Card CLKREQ# 44 57 SEL_27 R265 158/F_4 To NB
19 MINI_CLKREQ# CLKREQ2# REF2/SEL_27 EXT_NB_OSC 10 EMI request --0215
39 R250 90.9/F_4
19 TV_CLKREQ# CLKREQ3#
21 LAN_CLKREQ# 38 CLKREQ4#
NB CLOCK INPUT TABLE
TGND0
TGND1
TGND2
TGND3
TGND4
TGND5
TGND6
TGND7
TGND8
TGND9
R1004/R1005 (value may change) NB CLOCKS RX780 RS780
SLG8SP628 NB_OSC HT_REFCLKP 100M DIFF 100M DIFF
65
66
67
68
69
70
71
72
73
74
RES CHIP 82.5 1/16W +-1%(0402) --> CS08252FB11 HT_REFCLKN 100M DIFF 100M DIFF
RX780 1.8V 82.5R/130R RES CHIP 130 1/16W +-1%(0402)L-F --> CS11302FB15
REFCLK_P 14M SE (1.8V) 14M SE (1.1V)
RES CHIP 158 1/16W +-1%(0402) --> CS11582FB00
RS780 1.1V 158R/90.9R RES CHIP 90.9 1/16W +-1%(0402) --> CS09092FB15 REFCLK_N NC vref
+3V
GFX_REFCLK 100M DIFF 100M DIFF(IN/OUT)*
Clock Gen I2C GPP_REFCLK 100M DIFF NC or 100M DIFF OUTPUT
+3V_CLK_VDD GPPSB_REFCLK 100M DIFF 100M DIFF
Q26 R275
RHU002N06
2
10K_4
PDAT_SMB 3 1 CGDAT_SMB
7,13,18,19 PDAT_SMB
1 66 MHz 3.3V single ended HTT clock
R260 SEL_HTT66
*8.2K_4 0* 100 MHz differential HTT clock
+3V
SEL_SATA 1* 100 MHz non-spreading differential SRC clock
A Check Chipset Power Domain SEL_HTT66 SEL_SATA A
SEL_27 0 100 MHz spreading differential SRC clock
R274 1 27MHz and 27M SS outputs
Q25 R259 R258 R249 SEL_27
RHU002N06 10K_4 8.2K_4 8.2K_4 8.2K_4 0* 100 MHz SRC clock
2
* default
7,13,18,19 PCLK_SMB
PCLK_SMB 3 1 CGCLK_SMB Quanta Computer Inc.
PROJECT : ZY7
Size Document Number Rev
1A
CLOCK GENERATOR_SLG8SP628
Date: Thursday, June 26, 2008 Sheet 2 of 35
5 4 3 2 1
5 4 3 2 1
HOLE14 HOLE5 HOLE2 HOLE23
*H-C295D118P2 *H-C295D118P2 *H-C295D118P2 *H-C295D118P2
2 5 2 5 2 5
3 6 3 6 3 6
HOLE27 HOLE28 HOLE36 HOLE37 4 7 4 7 4 7
HT_RXD#[15..0] HT_TXD[15..0] *MINI_HOLE MINI_HOLE MINI_HOLE MINI_HOLE
8 HT_RXD#[15..0] 8 HT_TXD[15..0]
8
1
9
8
1
9
8
1
9
1
HT_RXD[15..0] HT_TXD#[15..0]
8 HT_RXD[15..0] 8 HT_TXD#[15..0]
D D
HOLE4 HOLE35 HOLE25 HOLE24
PROCESSOR HYPERTRANSPORT INTERFACE
1
1
1
1
*H-C295D118P2 *H-C295D118P2 *H-C295D118P2 *H-C295D118P2
2 5 2 5 2 5 2 5
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER 3 6 3 6 3 6 3 6
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED HOLE9 HOLE10 HOLE19 HOLE20 4 7 4 7 4 7 4 7
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE CPU_HOLE CPU_HOLE CPU_HOLE CPU_HOLE
8
1
9