Text preview for : 2767 Pulse.pdf part of Keithley 2767 Pulse Keithley Appnotes 2767 Pulse.pdf
Back to : 2767 Pulse.pdf | Home
A G R E AT E R M E A S U R E O F C O N F I D E N C E anisms is the key to understanding channel
mobility degradation and device reliability
problems. However, traditional DC testing
techniques may not accurately characterize
these mechanisms.
Limitation of DC Characterization
Techniques
As charges are trapped in the gate dielec-
tric, the threshold voltage of the transistor
increases due to the built-in voltage in the
gate capacitor; therefore, the drain current
decreases. It appears that charge trapping
and de-trapping times strongly depend on
Pulsed
the composition of the gate stacks, i.e., physi-
cal thickness of the interfacial SiO2 layer and
high-k film, as well as process techniques
Characterization
[16-18]. The time scale varies from several
microseconds to tens of milliseconds [19].
The de-trapping of the charges is also strong-
of Charge-trapping
ly gate voltage and polarity dependent.
The wide dynamic range of charge trap-
ping, and the voltage dependent trapping
Behavior in High-k
and de-trapping, make it very difficult to use
one type of characterization technique (es-
pecially a DC technique) to get a complete
Gate Dielectrics
picture of what is going on inside the stacked
gate dielectric. For example, commonly used
methods employ a double sweep in either DC
Vgs-Id or high frequency C-V measurements.
These techniques involve ramping gate volt-
Yuegang Zhao, Keithley Instruments, Inc. age back and forth while drain current or
gate capacitance is measured. If hysteresis is
Chadwin D Young, Rino Choi, and Byoung Hun Lee, seen on the resulting I-V or C-V curves, it is
SEMATECH High-k Material Research a clear indication of charge trapping inside
the gate stacks.
The issue with this technique is that the
This article discusses the nature of the be made thicker than SiO2 while achieving hysteresis is strongly dependent on measure-
charge trapping and the limitation of DC the same capacitance. The result is leakage ment time. The hysteresis measured in the
characterization techniques in quantifying current that can be lower by as much as sev- DC I-V test could be different from that in
trappedcharge.Then,itdescribesanultra- eral orders of magnitude. However, there are a C-V test, because the time taken for each
fast pulse I-V technique for characterizing still technical challenges to overcome, such measurement may be dramatically different.
the intrinsic ("trap free") performance of as Vt instability [2-4], carrier channel mobil- This is illustrated by dual sweep C-V meas-
high-k gate transistors that exhibit the fast ity degradation [5-9], and long-term device urements taken at different speeds (Figure
transientchargingeffect(FTCE). reliability [10-13]. 1). Test speed is strongly dependent on in-
One of the important issues preventing strumentation and not easily controlled.
Development of High-k Gates for implementation of high-k gates is the trap- Even if it were, there is no model to quan-
Advances CMOS Devices ping of charges in the pre-existing traps tify how much charge is really trapped in the
High dielectric constant (high-k) materi- inside these dielectrics [14-15]. When the gate during the test; i.e., hysteresis cannot
als, such as hafnium oxide (HfO2), zirconium transistor is turned on, some of the chan- quantify the amount of charge trapped, since
oxide (ZrO2), alumina (Al2O3), and their sili- nel carriers will be accumulated in the gate a significant portion of the fast transient trap-
cates, have drawn a great deal of attention in dielectric due to the vertical electrical field, ping could be lost in the DC measurement.
recent years for potential use as gate dielec- resulting in a shift of threshold voltage and a Another method involves DC stress volt-
trics in advanced CMOS processes [1]. With reduction in drain current. Fully understand- age to inject charges intentionally into the
high dielectric constants, gate dieletrics can ing charge-trapping and these related mech- gate, then the use of C-V or I-V method to
Pulsed Characterization of Charge-trapping Behavior in High-k Gate Dielectrics May2006
1.40E