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A B C D E
1 1
2
Compal Confidential 2
KAW60 Schematics Document
AMD AM2 / RS690MC / SB600
2008 / 07 / 25 Rev:0.2 FOR PVT
3 3
4 4
Security Classification Compal Secret Data
Issued Date 2005/05/09 Deciphered Date 2006/03/08 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, July 25, 2008 Sheet 1 of 50
A B C D E
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Compal confidential
Project Code: KAW60 AMD AM2 CPU
Thermal Sensor Clock Generator DDRII 533/667 DDRII-SO-DIMM X2
File Name : LA-4661P
ADM1032ARM ICS951462 940P PGA page 10,11
page 6,7,8,9
page 8 page 17 Dual Channel
D D
H_A#(3..31) H_D#(0..63)
HT 16x16 1000MHZ
SIG1 : 35mm x 35mm x (2.20mm+2.11mm) 638pin
CRT & TV-OUT AM2 : 40mm x 40mm x (4.56mm+2.11mm) 940pin
page 24 ATI-RS690MC
465 BGA RS485 : 21mm x 21mm (19.2mm x 19.2mm) x2.33mm 465pin
RS690 : 21mm x 21mm (19.2mm x 19.2mm) x2.33mm 465pin
Mini card LCD CONN
page 12,13,14,15,16
page 25 SB460 : 27mm x 27mm (21.6mm x 21.6mm) x2.33mm 549pin
page 31 SB600 : 23mm x 23mm (21.6mm x 21.6mm) x2.33mm 549pin
A-Link Express
4 x PCIE
PCIE X1
PCIE X1
USB 2.0 USB conn x 2 / New card / Camera
C
page 34 page 31 C
ATI-SB600 USB 2.0 BT Conn
page 38
PCI BUS 549 BGA
HDA Codec
HD Audio AMP & Audio Jack
ALC268 page 40
Realtek page 18,19,20,21,22 page 39 APA2057
Mini PCI Socket RTL8100CL ENE Controller 1394 Controller MDC Conn.
Mini card RTL8110SCL CB714 VT6311S page 41
page 31 page 26 page 35
page 32
SATA HDD Conn.
page 23
Realtek 6in1 CardReader LPC BUS
RJ45 CONN Slot 0 1394
B RTL8102EL Slot Conn. B
page 27 page 33 page 33 page 35
page 26 SATA
CDROM Conn.
page 23
Power On/Off CKT / LID switch / Power OK CKT
page 37
SMsC LPC47N207 ENE KB926
page 36 page 28
DC/DC Interface CKT. CIR/LED RTC CKT.
page 41 page 38 page 18
Int. KBD
Power Circuit DC/DC FIR module page 29
page 42~48
page 36 Touch Pad
CONN. page 29
SPI BIOS
A
page 30 A
Security Classification Compal Secret Data
Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
BLOCK DIAGRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sunday, July 20, 2008 Sheet 2 of 50
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SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
D D
B+ AC or battery power rail for power circuit. N/A N/A N/A
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.2V_HT 1.2V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8VALW 1.8V always on power rail ON ON ON* Board ID / SKU ID Table for AD channel
+1.8V 1.8V power rail for DDR ON ON OFF Vcc 3.3V +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON* 0 0 0 V 0 V 0 V
+3VS 3.3V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VALW 5V always on power rail ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VS 5V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+VSB VSB always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+RTCVCC RTC power ON ON ON 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
C C
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
BOARD ID Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices Board ID PCB Revision BTO Option Table
Device IDSEL# REQ#/GNT# Interrupts
0
BTO Item BOM Structure
1
WITH AMD HDT Debug port HDT@
2
WITH USBx2 USB2@
3
USBX1 WITH CHOKE EMI@
4
USBX1 WITHOUT CHOKE WOEMI@
5
USBx2 WITH CHOKE USB2EMI@
6
USBx2 WITHOUT CHOKE USB2WOEMI@
7
WITH MODEM MDC@
B B
SPI ROM under SB600 SB600SPI@
EC SM Bus1 address EC SM Bus2 address SKU ID Table
Device Address Device Address SKU ID SKU
Smart Battery 0001 011X b ADM1032 1001 100X b 0
EEPROM(24C16/02) 1010 000X b 1
(24C04) 1011 000X b 2
3
4
5
SB600 SM Bus address 6
7
Device Address
Clock Generator 1101 001Xb
(ICS951462)
A DDR DIMM0 A
1001 000Xb
DDR DIMM2 1001 010Xb
Security Classification Compal Secret Data
Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
TABLE OF CONTENTS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HCW51 LA-3121P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 24, 2008 Sheet 3 of 50
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D D
DIMM3 DIMM4
PCI CLKFB
PCI CLK
DIMM1 DIMM2
33MHZ
PCI CLK0
PCI SLOT0
3 PAIR MEM CLK
3 PAIR MEM CLK
33MHZ
3 PAIR MEM CLK
3 PAIR MEM CLK
PCI CLK1
PCI SLOT1
33MHZ
HTREFCLK PCI CLK1
PCI SLOT2
66MHZ 33MHZ
ATI NB -RS690 ATI SB
M2 CPU 1 PAIR CPU CLK NB-OSC PCI CLK6
LPC BIOS
200MHZ 14.318MHZ SB600 33MHZ
C
M2 SOCKET 14.318MHZ OSC INPUT C
(OPTION)
14.318MHZ
SB-OSCIN
TVCLKIN
NB PCIE CLK
100MHZ
SB PCIE CLK PCI CLK5 KB_CLK
KEYBOARD
100MHZ 33MHZ SUPER IO
SB-OSCIN SB-OSCIN SIO_CLK IT8712F MS_CLK
EXTERNAL
14.318MHZ 14.318MHZ 24/48MHZ MOUSE
CLK GEN.
PCIE CLK
100MHZ PCIE GFX SLOT - 16 LANES
PCIE CLK
AZ_BITCLK AC97 CODEC 24.576MHZ OSC INPUT
100MHZ PCIE GPP SLOT 1 - 1 LANE
AZALIA
PCIE CLK
100MHZ PCIE GPP SLOT 2 - 1 LANE
PCIE CLK
100MHZ PCIE GBE
25M Hz
B B
PCIE CLK
100MHZ PCIE STAT
PCIE CLK
100MHZ
USB CLK
48MHZ
32.768K Hz
48MHZ OSC INPUT FOR USB
(OPTION)
14.31818MHz
A A
Security Classification Compal Secret Data
Issued Date 2005/10/10 Deciphered Date 2006/10/10 Title
CLOCK DISTRIBUTION
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 17, 2008 Sheet 4 of 50
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CPU_VDDA_RUN (S0, S1) M2
CPU 2.5V SHUNT
REGULATOR VDDA 2.5V 0.1A
ATX P/S WITH 1A STBY CURRENT PW CPU_VDD_RUN (S0, S1) VDDCORE
5VSB 5V 3.3V 12V -12V 12V 0.8-1.55V 80A
+/-5% +/-5% +/-5% +/-5% +/-5% +/-5% CPU_VTT_SUS (S0,S1,S3)
DDRII MEM I/F VTT
CPU_VDDIO_SUS(S0,S1,S3) 0.125A, VDD 3A
VRM SW VLDT 1.2V 0.5A
REGULATOR
DDRII DIMMs
0.9V VTT_DDR
D D
REGULATOR VTT_DDR 2A RS690
+5VDUAL_MEM (S0,S5) 1.8V VDD SW VDDHT 1.2V 0.5A
REGULATOR VDD MEM 12A
PCI-E CORE&VCO
& I/O &PLL 2.25A
NB CORE VDDC
1.2V 5A
1.8V LINEAR +1.8V(S0, S1)
DAC 200mA LVDS
REGULATOR 1.8V 300mA
PLL & DAC-Q 0.1A
VCC 1.2V SW VCC_NB (S0, S1)
PCI-E PLL
REGULATOR
+3.3VSB (S0, S1, S3, S4, S5)
+3.3VDUAL (S0, S1, S3, S4, S5)
+3.3VSB REGULATOR SB600
ACPI CONTROLLER
+5VDUAL (S0, S1, S3, S4, S5) X4 PCI-E 0.8A
C ATA I/O 0.2A C
ATA PLL 0.01A
PCI-E PVDD 80mA
SB CORE 0.6A
1.2V STB LDO +1.2VSB (S5) 1.2V S5 PW 0.22A
REGULATOR
3.3V S5 PW 0.01A
USB CORE I/O 0.2A
3.3V I/O 0.45A
AZALIA CODEC
3.3V CORE 0.3A
5V ANALOG 0.1A
B B
SUPER I/O
+5V SD 0.01A
+5V 0.1A
PCI Slot (per slot) X1 PCIE per X16 PCIE CNR CONNECTOR USB X4 FR USB X6 RL 2XPS/2 GBE SATA
5V 5.0A 3.3V 3.0A 3.3V 3.0A 5V 1.0A VDD VDD 5VDual 3.3V 0.5A (S0, S1) 3.3V 0.3A (S0, S1)
3.3V 7.6A 3.3V 1.0A 5VDual 5VDual 3.3V 0.1A (S3)
12V 0.5A 12V 5.5A 1.0A
12V 0.5A 12V 0.5A 2.0A 2.0A
A
3.3Vaux 0.1A A
3.3Vaux 0.375A 3.3Vaux 1.0A
-12V 0.1A -12V 0.1A
5VDual 0.5A
Security Classification Compal Secret Data
+3.3VDUAL (S0, S1, S3)
Issued Date 2005/10/10 Deciphered Date 2006/10/10 Title
POWER DELIVERY CHART
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 17, 2008 Sheet 5 of 50
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PROCESSOR HYPERTRANSPORT INTERFACE
D D
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
+1.2V_HT
JCPU1A
AJ4 VLDT_06 VLDT_08 H6 1 2 C455
AJ3 H5 4.7U_0805_10V4Z
VLDT_05 VLDT_07
AJ2 H2
AJ1
VLDT_02
VLDT_01
VLDT_04
VLDT_03 H1 FAN Conn
H_CADIP15 U6 Y5 H_CADOP15
12 H_CADIP15 L0_CADIN_H15 L0_CADOUT_H15 H_CADOP15 12
H_CADIN15 V6 Y4 H_CADON15
12 H_CADIN15 L0_CADIN_L15 L0_CADOUT_L15 H_CADON15 12
H_CADIP14 T4 AB6 H_CADOP14
12 H_CADIP14 L0_CADIN_H14 L0_CADOUT_H14 H_CADOP14 12
H_CADIN14 T5 AA6 H_CADON14
12 H_CADIN14 L0_CADIN_L14 L0_CADOUT_L14 H_CADON14 12
H_CADIP13 R6