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5 4 3 2 1
BOM MARK
IV@: INT VGA
Z06 SYSTEM BLOCK DIAGRAM DDR PWR
TPS5116 P34
CHARGER
ISL6251 P30
EV@: STUFF FOR EXT VGA THERMAL 3/5V SYS PWR
SP@: STUFF FOR UMA or VGA X'TAL PROTECTION P37 ISL6237 P31
14.318MHz
Penryn 479 Thermal Sensor Fan Driver 1.5V PWR CPU CORE PWR
D
CLOCK GENERATOR uFCPGA (G780P81U) (G991) DISCHARGER P36 OZ8116LN P33
D
P3, P4 P3 P24
ICS:
SELGO: SLG8SP512TTR VGA CORE
+1.05V
P2 OZ8118 P35 RT8202 P32
FSB
667/800/1067 Mhz
NVIDIA EXT_LVDS
N10M-GE1 EXT_CRT CRT
PCIE 16X P23
VRAM 512MB EXT_HDMI SWITCH
DDRII NB P17-P22 LVDS
P23
SO-DIMM 0 Dual Channel DDR2 CIRCUIT
Cantiga LVDS INT_LVDS
SO-DIMM 1 667/800 MHz
P16 (GM45/ PM45/ GL40) HDMI
RGB INT_CRT P23 P23
C C
P5, P6, P7, P8, P9, P10, P11
HDMI switch
INT_HDMI
(PS8122)
X4 DMI interface P23
HDD (SATA) *1
P24
Ext USB Port x 2
USB 0,1 P25 SATA0
PCI-Express PCIE-1 Mini Card
Int USB Port x 1 ODD (SATA) WLAN
USB 7 P25
P24
SATA1 SB USB2 P25
Bluetooth ICH9M USB8 USB2
USB5 P25
USB 2.0 X'TAL
B PCIE-6 X'TAL B
32.768KHz
CCD Azalia P12,P13,P14,P15
25MHz
USB11 P23
Media Broadcom
LPC Cardreader Giga-LAN
(RTS5158E) (BCM5764)
USB2 P28 P27
Audio CODEC EC (WPC775LDG)
(CX20561) P26 P29
X'TAL
32.768KHz
RJ11 Card Reader Transformer
MDC 1.5 WIRE CONN.
Connector
P26 P28
SPI ROM
P29
RJ45
A P27 A
Audio Amplifier
Touch Pad MMB
G1441 P26 P24 P24
Quanta Computer Inc.
Int.
S/PDIF MIC Jack Int. MIC K/B COON. PROJECT : Z06
Speaker Size Document Number Rev
P26 P26 P26 P23 P29 1A
Block Diagram
Date: Thursday, March 12, 2009 Sheet 1 of 39
5 4 3 2 1
5 4 3 2 1
Clock Generator Modify footprint REV:B
BKP1608HS181T_6_1.5A
+3V +3V_CLK U6 CLK VDD power range 1.05V~3.3V
L23 BKP1608HS181T_6_1.5A
C375 C681 C683 C397 C695 C400 C390 2 12 +1V05_CLK +1.05V
VDD_PCI VDD_I/O
9 VDD_48 VDD_PLL3_I/O 20
.1u/10V_4 *.1u/10V_4 .1u/10V_4 *.1u/10V_4 .1u/10V_4 .1u/10V_4 10u_6 16 26 C381 C376 C696 C684 C682 C694 C697 L21
VDD_PLL3 VDD_SRC_I/O_1
39 VDD_SRC VDD_SRC_I/O_2 36
55 45 10u_6 .1u/10V_4 .1u/10V_4 *.1u/10V_4 .1u/10V_4 .1u/10V_4 .1u/10V_4
C379 33p/50V_4 VDD_CPU VDD_SRC_I/O_3
D EMI 61 VDD_REF VDD_CPU_I/O 49 D
1
CG_XIN 60 37 PM_STPCPU# (14)
C407 *10p/50V_4 PCLK_MINI_R Y1 XTAL_IN CPU_STOP#
Modify REV:D 14.318MHz CG_XOUT PCI_STOP# 38 PM_STPPCI# (14) Pin 56 : It acts as a
59 56 CK_PWRGD (14)
C398 *10p/50V_4 PCLK_591_R XTAL_OUT CKPWRGD/PD# level sensitive strobe
2
C383 27p/50V_4 54 to latch the FS pins
CPU_0 CLK_CPU_BCLK (3)
C399 *10p/50V_4 PCLK_ICH_R 53
CPU_0# CLK_CPU_BCLK# (3) and other multiplexed
(14) SATACLKREQ# R273 475/F_4 SATACLKREQ#_R 1 51
PCI_0/CLKREQ_A# CPU_1_MCH CLK_MCH_BCLK (5)
C401 *10p/50V_4 FSA (27) GLAN_CLKREQ# R274 475/F_4 GLAN_CLKREQ#_R 3 50 inputs.
PCI_1/CLKREQ_B# CPU_1_MCH# CLK_MCH_BCLK# (5)
R275 33_4 PCLK_MINI_R 4 47
(25) PCLK_DEBUG PCI_2 SRC_8/CPU_ITP
C377 *30p/50V_4 FSC R272 33_4 PCLK_591_R 5 46
(29) PCLK_591 PCI_3 SRC_8#/CPU_ITP#
PCLK_PCM_R 6
R276 33_4 PCLK_ICH_R ^PCI_4/LCDCLK_SEL
(13) PCLK_ICH 7 PCIF_5/ITP_EN
CPU_BSEL0 R285 2.2K_4 48
R279 22_4 NC
(14) CLKUSB_48 R287 22_4 FSA
(28) CLK_Card48 10 USB_48MHz/FS_A
MCH_BSEL1 57 FS_B/TEST_MODE CLK_DREFSSCLK_R
LCDCLK/27M 17
CPU_BSEL2 R221 10K_4 18 CLK_DREFSSCLK#_R
R222 33_4 FSC LCDCLK#/27M_SS
(14) 14M_ICH 62 REF/FS_C/TEST_SEL
CLK_DREFCLK_R 13 21
SRC_0/DOT_96 SRC_2 CLK_PCIE_SATA (12)
CLK_DREFCLK#_R 14 22
SRC_0#/DOT_96# SRC_2# CLK_PCIE_SATA# (12)
24 CLK_PCIE_SRC4
SRC_3/CLKREQ_C# T32
+3V CGCLK_SMB 64 25 CLK_PCIE_SRC4#
C SCL SRC_3#/CLKREQ_D# T31 C
CGDAT_SMB 63 27
SDA SRC_4 CLK_PCIE_LAN (27)
SRC_4# 28 CLK_PCIE_LAN# (27)
SRC_6 41 CLK_PCIE_ICH (13)
SRC_6# 40 CLK_PCIE_ICH# (13)
R225 R224 44 CLK_PCIE_SRC7
SRC_7/CLKREQ_F# T29
Q11 8 43 CLK_PCIE_SRC7#
VSS_PCI SRC_7#/CLKREQ_E# T28
2
2N7002E 10K_4 10K_4 11 30
VSS_48 SRC_9 CLK_PCIE_MINI1 (25)
15 VSS_I/O SRC_9# 31 CLK_PCIE_MINI1# (25)
3 1 CGDAT_SMB 19 34
(14,16,25,27) PDAT_SMB VSS_PLL3 SRC_10 CLK_PCIE_3GPLL (6)
23 VSS_SRC_1 SRC_10# 35
CLK_MCH_OE#_C R227 475/F_4
CLK_PCIE_3GPLL# (6) Add REV:C
29 VSS_SRC_2 SRC_11/CLKREQ_H# 33 CLK_MCH_OE# (6)
42 32 CLK_PCIE_SRC11# R615 475/F_4
VSS_SRC_3 SRC_11#/CLKREQ_G# MINI_CLKREQ# (25)
52 VSS_CPU
+3V 58 RN53
VSS_REF CLK_DREFCLK_R 1 2 IV@0_4P2R CLK_DREFCLK (6)
Q10 CLK_DREFCLK#_R 3 4 CLK_DREFCLK# (6)
2
2N7002E From GMCH RN52
CLK-GEN_SLG8SP512TTR CLK_DREFSSCLK_R 1 2 IV@0_4P2R CLK_DREFSSCLK (6)
3 1 CGCLK_SMB CLK_DREFSSCLK#_R 3 4
(14,16,25,27) PCLK_SMB CLK_DREFSSCLK# (6)
RN28
CLK_DREFCLK_R 3 4 EV@0_4P2R CLK_MXM (17)
CLK_DREFCLK#_R 1 2 CLK_MXM# (17)
From MXM RN29
CLK_DREFSSCLK_R 3 4 EV@33_4P2R 27M_NONSS (19)
CLK_DREFSSCLK#_R 1 2 27M_SS (19)
B Modify REV:B B
+3V
CPU Clock select Strap table
BSEL Frequency Select Table Pin 1 : CLKREQ_A# Control SRC_0 & SRC_2
R249 10K_4 SATACLKREQ#_R
FSC FSB FSA Frequency Pin 3 : CLKREQ_B# Control LCDCLK & SRC_4
Pin 10/57/62 : For Pin CPU frequency selection R250 10K_4 GLAN_CLKREQ#_R
0 0 0 266Mhz R268 *10K_4 PCLK_MINI_R R243 *10K_4 Reserve overclocking
CPU_BSEL0 R290 SHORT_4
(3) CPU_BSEL0 MCH_BSEL0 (6)
0 0 1 133Mhz R616 10K_4 CLK_PCIE_SRC11# Add REV:C
0 1 1 166Mhz R235 EV@10K_4 PCLK_PCM_R R238 IV@10K_4
CPU_BSEL1 R223 SHORT_4
(3) CPU_BSEL1 MCH_BSEL1 (6)
0 1 0 200Mhz Pin 6 : For Pin 13/14 and 17/18 selection
0 = LCDCLK & DOT96 for internal graphic controller support
1 1 0 400Mhz 1 = 27M & 27M_SS &SRC_0 for external graphic controller support
CPU_BSEL2 R220 SHORT_4
(3) CPU_BSEL2 MCH_BSEL2 (6)
1 1 1 Reserved
PCLK_ICH_R R269 10K_4
A A
Modify REV:B
1 0 1 100Mhz
1 0 0 333Mhz Pin 7 : For Pin 46/47 selection
1 = CPU_ITP
Quanta Computer Inc.
0 = SRC_8 PROJECT : Z06
CLOCK GENERATOR Size
Date:
Document Number
CLOCK GENERATOR
Thursday, March 12, 2009 Sheet 2 of 39
Rev
2A
5 4 3 2 1
5 4 3 2 1
(5) H_A#[3..16]
U24A
H_A#3 J4 H1
A[3]# ADS# H_ADS# (5)
ADDR GROUP_0
H_A#4 L5 E2 H_D#[0..15] U24B H_D#[32..47]
A[4]# BNR# H_BNR# (5) (5) H_D#[0..15] H_D#[32..47] (5)
H_A#5 L4 G5 H_D#0 E22 Y22 H_D#32
A[5]# BPRI# H_BPRI# (5) D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 A[6]# H_D#2 D[1]# D[33]# H_D#34
M3 A[7]# DEFER# H5 H_DEFER# (5) E26 D[2]# D[34]# V24
DATA GRP 0
H_A#8 N2 F21 H_D#3 G22 V26 H_D#35
H_DRDY# (5)
DATA GRP 2
H_A#9 A[8]# DRDY# H_D#4 D[3]# D[35]# H_D#36
J1 A[9]# DBSY# E1 H_DBSY# (5) F23 D[4]# D[36]# V23
H_A#10 N3 H_D#5 G25 T22 H_D#37
H_A#11 A[10]# H_D#6 D[5]# D[37]# H_D#38
P5 A[11]# BR0# F1 H_BREQ# (5) E25 D[6]# D[38]# U25
H_A#12 P2 H_D#7 E23 U23 H_D#39
D A[12]# D[7]# D[39]# D
CONTROL
H_A#13 L2 D20 H_IERR# R97 56_4 +1.05V H_D#8 K24 Y25 H_D#40
H_A#14 A[13]# IERR# H_D#9 D[8]# D[40]# H_D#41
P4 A[14]# INIT# B3 H_INIT# (12) G24 D[9]# D[41]# W22
H_A#15 P1 H_D#10 J24 Y23 H_D#42
H_A#16 A[15]# H_D#11 D[10]# D[42]# H_D#43
R1 A[16]# LOCK# H4 H_LOCK# (5) J23 D[11]# D[43]# W24
M1 H_D#12 H22 W25 H_D#44
(5) H_ADSTB#0 ADSTB[0]# D[12]# D[44]#
C1 H_D#13 F26 AA23 H_D#45
(5) H_REQ#[0..4] RESET# H_CPURST# (5) D[13]# D[45]#
H_REQ#0 K3 F3 H_D#14 K22 AA24 H_D#46
REQ[0]# RS[0]# H_RS#0 (5) D[14]# D[46]#
H_REQ#1 H2 F4 H_D#15 H23 AB25 H_D#47
REQ[1]# RS[1]# H_RS#1 (5) D[15]# D[47]#
H_REQ#2 K2 G3 J26 Y26
REQ[2]# RS[2]# H_RS#2 (5) (5) H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 (5)
H_REQ#3 J3 G2 H26 AA26
REQ[3]# TRDY# H_TRDY# (5) (5) H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 (5)
H_REQ#4 L1 H25 U22
REQ[4]# (5) H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 (5)
(5) H_A#[17..35] HIT# G6 H_HIT# (5)
H_A#17 Y2 E4 H_D#[16..31] H_D#[48..63]
A[17]# HITM# H_HITM# (5) (5) H_D#[16..31] H_D#[48..63] (5)
H_A#18 U5 H_D#16 N22 AE24 H_D#48
H_A#19 A[18]# XDP_BPM#0 H_D#17 D[16]# D[48]# H_D#49
R3 AD4 T23 K25 AD24
A[19]# BPM[0]# D[17]# D[49]#
ADDR GROUP_1
H_A#20 W6 AD3 XDP_BPM#1 T24 H_D#18 P26 AA21 H_D#50
H_A#21 A[20]# BPM[1]# XDP_BPM#2 H_D#19 D[18]# D[50]# H_D#51
H_A#22
U4 A[21]# BPM[2]# AD1
XDP_BPM#3
T25
H_D#20