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A B C D E

1 1

2
Compal Confidential 2

G470/G570 UMA M/B Schematics Document
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH

3 2010-10-22 3

LA-6752P / LA-6754P
REV:0.2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6752P
Date: Friday, November 26, 2010 Sheet 1 of 50
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A B C D E

Compal confidential For 14"(Page 4x) For 15"(Page 4x+1)
File Name : G470/G570 LS6753P PWR/B LS6753P PWR/B
LS6751P CardReader/B LS6751P CardReader/B
LS6754P LED/B
LS6755P ODD/B
Intel
1 Sandy Bridge 1

DDR3 SO-DIMM *2
Socket-rPGA988B BANK 0, 1, 2, 3 Page12-13
37.5mm*37.5mm
Dual Channel Up to 8GB
HDMI Page33 Page5-11 DDR3 1066MHz(1.5V)
DDR3 1333MHz(1.5V)
Connector
100MHz
Page32 2.7GT/s FDI *8 DMI *4
CRT
Connector Audio Codec 2 channel speaker
Intel
AZALIA Conexant
LVDS Page31 Cougar Point CX20671
Int. MIC
2 Connector FCBGA 989 2

Audio Jacks
25mm*25mm Page39

LAN Page35 PCI-E x1 *6 USB2.0 *14
Athros Camera Conn.
AR8151-B(GLAN)
AR8152-B(10/100) SATA *6 BlueTooth Conn.
Page42
Page14-22
RJ-45 Page36
SPIROM Mini Card Slot *1
Page34
Connector BIOS
LPC BUS Card Reader
PCI Express PCI-E(WLAN)
Page40 Reltek
Mini Card Slot *1
EC RTS5139
3 USB(WiMAX) ENE KB930 SDXC/MMC/MS/xD 3

WLAN ENE KB9012
WiMAX Page34 USB2.0 *1(Right)
USB2.0 *2(Left)
Touch Pad Int. KBD

Thermal Sensor SPI ROM
Page41
eSATA+USB(Left) Page42
EMC1403 Page37
SATA3 HDD (Port 0/Port 1 support SATA3)
Page38

SATA ODD Page38
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6752P
Date: Friday, November 26, 2010 Sheet 2 of 50
A B C D E
A B C D E

SIGNAL
Voltage Rails STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+5VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+3VS
power S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane +1.5VS
1
+VCCP S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1

+5VALW +1.5V +CPU_CORE
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +VGA_CORE
+3VALW +GFX_CORE
BOARD ID Table Board ID / SKU ID Table for AD channel
+1.8VS
State +0.75VS Board ID PCB Revision Vcc 3.3V +/- 5%
+1.05VS 0 0.1 Ra/Rc/Re 100K +/- 5%
1 Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
2 0 0 0 V 0 V 0 V EVT
3 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V DVT
4 2 18K +/- 5% 0.436 V 0.503 V 0.538 V PVT
5 3 33K +/- 5% 0.712 V 0.819 V 0.875 V MP
S0 6 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
O O O O
7 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
S3 7 NC 2.500 V 3.300 V 3.300 V
O O O X
2 2

S5 S4/AC
O O X X USB Port Table
S5 S4/ Battery only 3 External
O X X X USB 2.0 USB 1.1 Port BOM Structure Table
USB Port
S5 S4/AC & Battery
BTO Item BOM Structure
X X X X 0 USB/B (Right Side)
don't exist UHCI0 CAMERA DEVICE CMOS@
1 USB Port (Left Side)
Address Blue Tooth BT@
EC SM Bus1 address EC SM Bus2 address 2 USB Port (Left Side)
UHCI1 eSATA ESATA@
3 USB Port (Left Side)
EHCI1 COMMON HDMI HDMI@
Device Device Address 4
UHCI2 Connector ME@
Smart Battery 0001 011X b 5 Camera
Thermal Sensor EMC1403-2 1001_101xb 45 LEVEL 45@
6
UHCI3 10/100 LAN 8152@
7
GIGA LAN GIGA@
PCH SM Bus address 8 Mini Card(WLAN)
UHCI4
9
Device Address 10
DDR DIMM0
EHCI2 UHCI5
3
1001 000Xb 11 Card Reader 3
DDR DIMM2 1001 010Xb 12
UHCI6
13 Blue Tooth

SMBUS Control Table
Thermal
WLAN Sensor Unpop @
SOURCE VGA BATT KE930 SODIMM WWAN PCH

SMB_EC_CK1
SMB_EC_DA1
KB930 X V
+3VALW
X X X X X
+3VALW
SMB_EC_CK2
SMB_EC_DA2
KB930 X X X X X X V
+3VS
+3VALW
SMBCLK
SMBDATA
PCH X X X V
+3VS +3VS
V X X
+3VALW
SML0CLK
SML0DATA
PCH X X X X X X X
+3VALW
4 4
SML1CLK
SML1DATA
PCH
+3VALW +3VS
V X V
+3VS
X X V
+3VS
X

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6752P
Date: Friday, November 26, 2010 Sheet 3 of 50
A B C D E
5 4 3 2 1

Power-Up/Down Sequence
All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up
Without BACO option :
sequence, though a shorter ramp-up duration is preferred. PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
VDDR3 should ramp-up before or simultaneously with VDDC.
For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
BACO option :
DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. PE_GPIO0 : High ->Normal operation (dGPU is not reseton BACO mode)
D
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High) D
The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and
VDD_CT have ramped up.
dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
ramp-up (or vice versa).) PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA
DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
DPLL_PVDD, MPV18, and SPV18

PCIE_VDDC(1.0V) DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 575mA
SPV10
PCIE_VDDC 1.0V OFF ON 2A
VDDR3(3.3VGS) Note: Do not drive any IOs before VDDR3 is ramped up.
VDDR3 , and A2VDD 3.3V OFF ON 190mA
BIF_VDDC (current consumption = [email protected], in Same as OFF ON 70mA
BACO mode) VDDC Same as
VDDR1(1.5VGS) PCIE_VDDC
VDDR1 1.5V OFF OFF 2.8A
VDDC/VDDCI 1.12V OFF OFF 12.9A
VDDC/VDDCI(1.12V)
Power Sequence
C
+1.0V SI4800
+1.0VGS C
VDD_CT(1.8V) BACO(jmp)
EN
+3.3VALWMOS
+3.3VGS
PERSTb BACO(jmp)

+1.5V SI4800
+1.5VGS
REFCLK
EN
+B Regulator
+VGA_CORE
Straps Reset
1.12V
+1.8V SI4800
+1.8VGS PX_mode
Straps Valid BACO(jmp) PE_EN
Regulators
BACO Switch
EN P25 PWRGOOD
VDDC/VDDCI
BIF_VDDC VDDR1
Global ASIC Reset
PE_GPIO1
PE_GPIO0

T4+16clock

B iGPU dGPU B

P24

A A

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CLOCK GENERATOR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6752P
Date: Friday, November 26, 2010 Sheet 4 of 50
5 4 3 2 1
5 4 3 2 1

D D
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
+1.05VS impedance = 43 mohms
PEG_ICOMPO signals should be routed with -

1
max length = 500 mils
R1
24.9_0402_1%
- typical impedance = 14.5 mohms
JCPU1A

2
J22 PEG_COMP
PEG_ICOMPI
J21
PEG_ICOMPO
<16> DMI_CRX_PTX_N0 B27 H22
DMI_RX#[0] PEG_RCOMPO
<16> DMI_CRX_PTX_N1 B25 DMI_RX#[1]
<16> DMI_CRX_PTX_N2 A25
DMI_RX#[2]
<16> DMI_CRX_PTX_N3 B24 DMI_RX#[3] PEG_RX#[0] K33
M35
PEG_RX#[1]
<16> DMI_CRX_PTX_P0 B28 L34
DMI_RX[0] PEG_RX#[2]
<16> DMI_CRX_PTX_P1 B26 J35
DMI_RX[1] PEG_RX#[3]

DMI
<16> DMI_CRX_PTX_P2 A24 DMI_RX[2] PEG_RX#[4] J32
<16> DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34
H31
PEG_RX#[6]
<16> DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33
<16> DMI_CTX_PRX_N1 E22 G30
DMI_TX#[1] PEG_RX#[8]
<16> DMI_CTX_PRX_N2 F21 F35
DMI_TX#[2] PEG_RX#[9]
<16> DMI_CTX_PRX_N3 D21 DMI_TX#[3] PEG_RX#[10] E34
PEG_RX#[11] E32
<16> DMI_CTX_PRX_P0 G22 D33
DMI_TX[0] PEG_RX#[12]
<16> DMI_CTX_PRX_P1 D22 D31
C DMI_TX[1] PEG_RX#[13] C

PCI EXPRESS* - GRAPHICS
<16> DMI_CTX_PRX_P2 F20 DMI_TX[2] PEG_RX#[14] B33
<16> DMI_CTX_PRX_P3 C21 C32
DMI_TX[3] PEG_RX#[15]

PEG_RX[0] J33
PEG_RX[1] L35
K34
PEG_RX[2]
<16> FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
<16> FDI_CTX_PRX_N1 H19 H32
FDI0_TX#[1] PEG_RX[4]
<16> FDI_CTX_PRX_N2 E19 FDI0_TX#[2] PEG_RX[5] G34
F18 G31

Intel(R) FDI
<16> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]
<16> FDI_CTX_PRX_N4 B21 FDI1_TX#[0] PEG_RX[7] F33
<16> FDI_CTX_PRX_N5 C20 F30
FDI1_TX#[1] PEG_RX[8]
<16> FDI_CTX_PRX_N6 D18 FDI1_TX#[2] PEG_RX[9] E35
<16> FDI_CTX_PRX_N7 E17 E33
FDI1_TX#[3] PEG_RX[10]
F32
PEG_RX[11]
D34
PEG_RX[12]
<16> FDI_CTX_PRX_P0 A22 E31
FDI0_TX[0] PEG_RX[13]
<16> FDI_CTX_PRX_P1 G19 C33
FDI0_TX[1] PEG_RX[14]
<16> FDI_CTX_PRX_P2 E20 B32
FDI0_TX[2] PEG_RX[15]
<16> FDI_CTX_PRX_P3 G18 FDI0_TX[3]
<16> FDI_CTX_PRX_P4 B20 M29
FDI1_TX[0] PEG_TX#[0]
<16> FDI_CTX_PRX_P5 C19 M32
FDI1_TX[1] PEG_TX#[1]
<16> FDI_CTX_PRX_P6 D19 M31
FDI1_TX[2] PEG_TX#[2]