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5 4 3 2 1
CPU CORE ISL6265A
PAGE 26 ZY5/ZY5D SYSTEM BLOCK DIAGRAM
NB CORE +1.1V
PAGE 27
NB RUN +1.1V
PAGE 28
D D
DDR II SMDDR_VTERM DDRII-SODIMM1
INT or EV DDRII 667/800 MHz Lion CPU THERMAL
1.8VSUS(TPS51116REGR) CPU Fan
PAGE 29 selector PAGE 6 AMD Griffin Sabie SENSOR
PAGE 17
Resistor
S1G2 Processor PAGE 4
SYSTEM POWER
DDRII-SODIMM2 DDRII 667/800 MHz 638P (uPGA)/35W
ISL6237 PAGE 25 PAGE 6 PAGE 2,3,4,5
SYSTEM CHARGER HT3
(ISL6251A)
LINK
PAGE 24 ZY5D NO USED
MXM
DISCHARGER Connector PCI-E
/ +1.1V_S5, +1.2V,+2.5V PCI-Express 16X
PAGE 30 PAGE 14
X1 X1 X1 X1 X1
RJ45/RJ11
Mini PCI-E Mini PCI-E Express Card Card reader LAN
LVDS
Card Card (NEW CARD) BroadCom PAGE 15
PCIE-LAN
C
CRT (TV TUNER) JMicron C
(Wireless LAN) USB2.0 Ports BCM5787/5764
ZY5D NO USED
NORTH BRIDGE & USB2.0 x1
x2
JMB385-LGEZ0A
(10/100/GigaLAN) CABLE DOCK
HDMI
LVDS SOUTH BRIDGE PAGE 16 PAGE 16 PAGE 16 PAGE 20 PAGE 18
LAN/VGA/DVI/USB/AUDIO
PAGE 22
PAGE 15
SN74CBTLV3257PWR TS3DV520RHUR SATA - HDD
SATA0 USB2.0
Switch Switch PAGE 17
PAGE 15 PAGE 15 MCP77M
SATA - HDD
SATA1 USB2.0 Ports Bluetooth CCD Fingrprinter CABLE DOCK USB
PAGE 17 27mm X 27mm,
836pin BGA
CRT
HDMI
x2 PAGE 16 x1 PAGE 16 x1 PAGE 15 x1 PAGE 16 x1 PAGE 22
DVI-D PCI
ODD(PATA)
PAGE 17 SATA2
PAGE HDA
14.318MHz
CRT 7,8,9,10,11,12,13 Card Bus
CABLE DOCK HDMI CONN.
B
PAGE 15 PAGE 22 PAGE 15 PCMCIA B
O2 Micro
OZ601TN
PAGE 23
Azalia AudioController MDC 1.5
LPC RealTek ALC268/888
PAGE 19
PAGE 19
Keyboard B TEST MODIFY
PAGE 21 KBC
(WPCE775CA0DG)
Audio Int MIC
CIR Amplifier
PAGE 16
PCB STACK UP PAGE 21
LAYER 1 : TOP
Speaker SPIDF/Phone Line in MIC Jack
LAYER 2 : SGND1 Jack
LAYER 3 : IN1 Touch SPI
A
Pad ROM A
LAYER 4 : IN2 PAGE 17 PAGE 21
LAYER 5 : VCC
CABLE DOCK
LAYER 6 : GND AUDIO
PAGE 22
Quanta Computer Inc.
PROJECT : ZY5D
Size Document Number Rev
3B
Block Diagram
Date: Wednesday, July 30, 2008 Sheet 1 of 35
2 1
5 4 3 2 1
HOLE10 HOLE9 HOLE19 HOLE20
*CPU_HOLE *CPU_HOLE *CPU_HOLE *CPU_HOLE HOLE3 HOLE4 HOLE1 HOLE23
*H-C295D118P2 *H-C295D118P2 *H-C295D118P2 *H-C295D118P2
2 5 2 5 2 5
3 6 3 6 3 6
HT_RXD#[15..0] HT_TXD[15..0] 4 7 4 7 4 7
7 HT_RXD#[15..0] 7 HT_TXD[15..0]
HT_RXD[15..0] HT_TXD#[15..0]
7 HT_RXD[15..0] 7 HT_TXD#[15..0]
1
1
1
1
8
1
9
8
1
9
8
1
9
1
D D
HOLE36 HOLE37 HOLE27 HOLE28
PROCESSOR HYPERTRANSPORT INTERFACE *MINI_HOLE *MINI_HOLE *MINI_HOLE *MINI_HOLE HOLE2 HOLE5 HOLE25 HOLE32
*H-C295D118P2 *H-C295D118P2 *H-C295D118P2 *H-C295D118P2
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER 2 5 2 5 2 5 2 5
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED 3 6 3 6 3 6 3 6
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE 4 7 4 7 4 7 4 7
1
1
1
1
8
1
9
8
1
9
8
1
9
8
1
9
REV:B Modify
ADOGND
VLDT_RUN HOLE8 HOLE17 HOLE7 HOLE16
*MXM_HOLE *MXM_HOLE *MXM_HOLE *MXM_HOLE HOLE34 HOLE35 HOLE33 HOLE14
*H-C295D118P2 *H-C295D118P2 *H-C295D118P2 *H-C295D118P2
2 5 2 5 2 5 2 5
U25A 3 6 3 6 3 6 3 6
4 7 4 7 4 7 4 7
C496
D1 VLDT_A0 HT LINK VLDT_B0 AE2
D2 AE3
1
1
1
1
8
1
9
8
1
9
8
1
9
8
1
9
VLDT_A1 VLDT_B1
D3 VLDT_A2 VLDT_B2 AE4
D4 AE5 4.7u/6.3V_6
VLDT_A3 VLDT_B3
HT_RXD0 E3 AD1 HT_TXD0 HOLE11 HOLE13 HOLE6 HOLE21 HOLE38
C L0_CADIN_H0 L0_CADOUT_H0 C
HT_RXD#0 E2 AC1 HT_TXD#0 *MDC_HOLE *MDC_HOLE *MXM1_HOLE *MXM1_HOLE *FAN_HOLE HOLE15 HOLE24
HT_RXD1 L0_CADIN_L0 L0_CADOUT_L0 HT_TXD1 *NONP_HOLE1 *H-C295D118P2
E1 L0_CADIN_H1 L0_CADOUT_H1 AC2
HT_RXD#1 F1 AC3 HT_TXD#1 2 5
HT_RXD2 L0_CADIN_L1 L0_CADOUT_L1 HT_TXD2
G3 L0_CADIN_H2 L0_CADOUT_H2 AB1 3 6
HT_RXD#2 G2 AA1 HT_TXD#2 4 7
HT_RXD3 L0_CADIN_L2 L0_CADOUT_L2 HT_TXD3
G1 L0_CADIN_H3 L0_CADOUT_H3 AA2
HT_RXD#3 H1 AA3 HT_TXD#3
1
1
1
1
1
1
8
1
9
HT_RXD4 L0_CADIN_L3 L0_CADOUT_L3 HT_TXD4
J1 L0_CADIN_H4 L0_CADOUT_H4 W2
HT_RXD#4 K1 W3 HT_TXD#4
HT_RXD5 L0_CADIN_L4 L0_CADOUT_L4 HT_TXD5
L3 L0_CADIN_H5 L0_CADOUT_H5 V1
HT_RXD#5 L2 U1 HT_TXD#5
HT_RXD6 L0_CADIN_L5 L0_CADOUT_L5 HT_TXD6 PAD2 PAD3 HOLE18 HOLE22 HOLE26 HOLE30 HOLE29 HOLE31
L1 L0_CADIN_H6 L0_CADOUT_H6 U2
HT_RXD#6 M1 U3 HT_TXD#6 *ODD1_HOLE *ODD1_HOLE *HDD1_HOLE *HDD1_HOLE *HDD2_HOLE *HDD2_HOLE
HT_RXD7 L0_CADIN_L6 L0_CADOUT_L6 HT_TXD7 *EMIPAD *EMIPAD
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
HT_RXD#7 N2 R1 HT_TXD#7
HT_RXD8 L0_CADIN_L7 L0_CADOUT_L7 HT_TXD8
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
HT_RXD#8 F5 AD3 HT_TXD#8
1
1
HT_RXD9 L0_CADIN_L8 L0_CADOUT_L8 HT_TXD9
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5
HT_RXD#9 F4 AC5 HT_TXD#9
1
1
1
1
1
1
HT_RXD10 L0_CADIN_L9 L0_CADOUT_L9 HT_TXD10
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
HT_RXD#10 H5 AB3 HT_TXD#10
HT_RXD11 L0_CADIN_L10 L0_CADOUT_L10 HT_TXD11
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5 MODIFY 10/17,ALEX
HT_RXD#11 H4 AA5 HT_TXD#11
HT_RXD12 L0_CADIN_L11 L0_CADOUT_L11 HT_TXD12
B K3 L0_CADIN_H12 L0_CADOUT_H12 Y5 B
HT_RXD#12 K4 W5 HT_TXD#12 +1.2V VLDT_RUN
HT_RXD13 L0_CADIN_L12 L0_CADOUT_L12 HT_TXD13
L5 L0_CADIN_H13 L0_CADOUT_H13 V4
HT_RXD#13 M5 V3 HT_TXD#13 L45
HT_RXD14 L0_CADIN_L13 L0_CADOUT_L13 HT_TXD14 Note:on MCP77,(HT=+1.1V) and CPU(HT=+1.2V)
M3 L0_CADIN_H14 L0_CADOUT_H14 V5
HT_RXD#14 M4 U5 HT_TXD#14 FBJ3216HS800_1206 and therefore cannot be connected to the
HT_RXD15 L0_CADIN_L14 L0_CADOUT_L14 HT_TXD15
N5 L0_CADIN_H15 L0_CADOUT_H15 T4 same HT power rail.
HT_RXD#15 P5 T3 HT_TXD#15 L48
L0_CADIN_L15 L0_CADOUT_L15
J3 Y1 FBJ3216HS800_1206
7 HT_CPU_UPCLK0 L0_CLKIN_H0 L0_CLKOUT_H0 HT_CPU_DWNCLK0 7
7 HT_CPU_UPCLK#0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 HT_CPU_DWNCLK#0 7
J5 Y4 80 ohm(4A) C528 C533 C544 C502 C497 C538
7 HT_CPU_UPCLK1 L0_CLKIN_H1 L0_CLKOUT_H1 HT_CPU_DWNCLK1 7
K5 Y3 4.7u/6.3V_6 4.7u/6.3V_6 .22u/6.3V_4 .22u/6.3V_4 180P_4 180P_4
7 HT_CPU_UPCLK#1 L0_CLKIN_L1 L0_CLKOUT_L1 HT_CPU_DWNCLK#1 7
7 HT_CPU_UPCTL0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 HT_CPU_DWNCTL0 7
7 HT_CPU_UPCTL#0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 HT_CPU_DWNCTL#0 7
7 HT_CPU_UPCTL1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 HT_CPU_DWNCTL1 7
7 HT_CPU_UPCTL#1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 HT_CPU_DWNCTL#1 7 LAYOUT: Place bypass cap on topside of board
NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
Athlon 64 S1g2 SOCKET_638_PIN TO OTHER HT POWER PINS
Athlon 64 S1g2 PLACE CLOSE TO VLDT0 POWER PINS
NO STUB
A R189 R187 Processor Socket A
for HT3 *51/F_4 *51/F_4
SOCKET_638_PIN
Quanta Computer Inc.
VLDT_RUN
PROJECT : ZY5D
Size Document Number Rev
3B
AMD Griffin HT I/F
Date: Wednesday, May 21, 2008 Sheet 2 of 35
5 4 3 2 1
A B C D E
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
Processor DDR2 Memory Interface
U25C
+SMDDR_VTERM +SMDDR_VTERM MEM:DATA
6 M_B_DQ[0..63] M_A_DQ[0..63] 6
M_B_DQ0 C11 G12 M_A_DQ0
U25B M_B_DQ1 MB_DATA0 MA_DATA0 M_A_DQ1
PLACE THEM CLOSE TO A11 MB_DATA1 MA_DATA1 F12
M_B_DQ2 A14 H14 M_A_DQ2
4 CPU WITHIN 1" +1.8VSUS M_B_DQ3 MB_DATA2 MA_DATA2 M_A_DQ3
4
D10 W10 B14 G14
VTT1 MEM:CMD/CTRL/CLK VTT5 M_B_DQ4 MB_DATA3 MA_DATA3 M_A_DQ4
C10 VTT2 VTT6 AC10 G11 MB_DATA4 MA_DATA4 H11
B10 AB10 M_B_DQ5 E11 H12 M_A_DQ5
VTT3 VTT7 M_B_DQ6 MB_DATA5 MA_DATA5 M_A_DQ6
AD10 AA10 D12 C13
R378 39.2/F_4 VTT4 VTT8 R113 M_B_DQ7 MB_DATA6 MA_DATA6 M_A_DQ7
VTT9 A10 A13 MB_DATA7 MA_DATA7 E13
1 2 M_ZP AF10 M_B_DQ8 A15 H15 M_A_DQ8
M_ZN MEMZP MB_DATA8 MA_DATA8
+1.8VSUS 2 1 AE10 MEMZN VTT_SENSE Y10 CPU_VTT_SUS_FB T25
1K/F_4 M_B_DQ9 A16 MB_DATA9 MA_DATA9 E15 M_A_DQ9
R379 39.2/F_4 M_B_DQ10 A19 E17 M_A_DQ10
MEM_MA_RESET# H16 CPU_M_VREF M_B_DQ11 MB_DATA10 MA_DATA10 M_A_DQ11
T50 RSVD_M1 MEMVREF W17 A20 MB_DATA11 MA_DATA11 H17
M_B_DQ12 C14 E14 M_A_DQ12
MB_DATA12 MA_DATA12
6 M_A_ODT0 T19 MA0_ODT0 RSVD_M2 B18 MEM_MB_RESET# T61
M_B_DQ13 D14 MB_DATA13 MA_DATA13 F14 M_A_DQ13
V22 C178 C101 R114 M_B_DQ14 C18 C17 M_A_DQ14
6 M_A_ODT1 MA0_ODT1 MB_DATA14 MA_DATA14
M_A1_ODT0 U21 W26 M_B_DQ15 D18 G17 M_A_DQ15
T34 MA1_ODT0 MB0_ODT0 M_B_ODT0 6 MB_DATA15 MA_DATA15
M_A1_ODT1 V19 W23 .1u/10V_4 1000p_4 1K/F_4 M_B_DQ16 D20 G18 M_A_DQ16
T29 MA1_ODT1 MB0_ODT1 M_B1_ODT0 M_B_ODT1 6 M_B_DQ17 MB_DATA16 MA_DATA16 M_A_DQ17
MB1_ODT0 Y26 T28 A21 MB_DATA17 MA_DATA17 C19
T20 M_B_DQ18 D24 D22 M_A_DQ18
6 M_A_CS#0 MA0_CS_L0 MB_DATA18 MA_DATA18
U19 V26 M_B_DQ19 C25 E20 M_A_DQ19
6 M_A_CS#1 MA0_CS_L1 MB0_CS_L0 M_B_CS#0 6 MB_DATA19 MA_DATA19
M_A1_CS#0 U20 W25 M_B_DQ20 B20 E18 M_A_DQ20
T30 MA1_CS_L0 MB0_CS_L1 M_B_CS#1 6 MB_DATA20 MA_DATA20
M_A1_CS#1 V20 U22 M_B1_CS#0 M_B_DQ21 C20 F18 M_A_DQ21
T32 MA1_CS_L1 MB1_CS_L0 T33 M_B_DQ22 MB_DATA21 MA_DATA21 M_A_DQ22
B24 B22
M_B_DQ23 MB_DATA22 MA_DATA22 M_A_DQ23
6 M_A_CKE0 J22 J25 M_B_CKE0 6 C24 C23
MA_CKE0 MB_CKE0 M_B_DQ24 MB_DATA23 MA_DATA23 M_A_DQ24
6 M_A_CKE1 J20 H26 M_B_CKE1 6 E23 F20
MA_CKE1 MB_CKE1