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8 7 6 5 4 3 2 1
Version 0A
Cover Sheet
Block Diagram
1
2
MS-6513 06/21/2001 Update
INTEL (R) Brookdale Chipset
GPIO Spec. 3
D
Willamette/Northwood 478pin mPGA-B Processor Schematics D
Clock CY28324 & ATA100 IDE CONNECTORS 4
mPGA478-B INTEL CPU Sockets 5-6
INTEL Brookdale MCH -- North Bridge 7-8
INTEL ICH2 -- South Bridge 9 - 10
LPC I/O W83627HF 11 CPU:
Willamette/Northwood mPGA-478B Processor
PCI AUDIO-CMI8738 12
AC'97 Codec 13
C
System Brookdale Chipset: C
Audio Amp TL072 & GAME 14
INTEL MCH (North Bridge) +
FWH -- BIOS & CNR RISER 15 INTEL ICH2 (South Bridge)
SDR DIMM-168PIN DIMM1,2 16 On Board Chipset:
AGP 4X SLOT (1.5V) 17 BIOS -- FWH
PCI SLOT 1 & 2 & 3 18 LPC Super I/O -- W83627HF
Front Panel & Connectors 19 Clock Generation -- CY28324
USB & FAN Connectors 20 PCI SOUND -- C-MEDIA CMI8738
B B
RESERVED 21
Votlage Regulator 22 Expansion Slots:
AGP2.0 SLOT * 1
HIP6301V CPU Power ( PWM )-VRM9.2 23
PCI2.2 SLOT * 3
IO Connectors 24
PCI3 with two
Realtek RTL8100(L) LAN 25 masters
DDR Damping 26
DDR Termination 27
A A
DDR Termination Power 28
Title Rev
Jumper setting 29 Micro-Star MS-6513 0A
Document Number
Power Delivery Map 30 Cover Sheet
Last Revision Date:
Thursday, June 21, 2001 Sheet 1 of 35
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
(478PINS)
(100MHz)
Power
Supply VRM Willamette/Northwood CK408 Clock
CONN 9.2 Socket (mPGA478-B) (100MHz)
(400MHz) Scalable Bus Scalable Bus/2
AGP 4X (66MHz) AGP
4X(1.5V) AGP 4X
(1.5V) MCH: Memory
AGP CONN
Controller HUB
(593PINS/FCBGA) (133MHz)
DDR 1:2
( 66MHz X 4 ) HUB Interface
(14.318MHz)
C Heceta Hardware SM Bus C
Monitor PCI (33MHz)
ICH2: I/O
PCI Slots 1:3
(360PINS/EBGA)
Controller HUB
IDE CONN 1&2
PCI Audio /
(48MHz) SPDIF/OUT
C-MEDIA
CMI8738
(33MHz)
(33MHz)
AMP
Telephone In
LPC Bus MIC In Line Out
USB Port 0:3 6 channel
Audio In
Line In
CD-ROM
FWH: Firmware HUB
PCI LAN / SIO
Realtek
RTL8100
B B
PS2 Mouse & Parallel (1) Floppy Disk
Keyboard Serial (2) Drive CONN
A A
Title Rev
Micro-Star MS-6513 0A
Document Number
Block Diagram
Last Revision Date:
Thursday, June 21, 2001 Sheet 2 of 35
8 7 6 5 4 3 2 1
5 4 3 2 1
General Purpose I/O Spec.
D D
ICH2
GPIO Pin Type Function
GPIO 0 I Non Connect
GPIO 1 I Non Connect
GPIO 2~4 I Not Implemented
DEVICE ICH INT Pin IDSEL
GPIO 5 I Non Connect
GPIO 6 I Non Connect
FWH PCI Slot 1 INTA# AD16
GPIO Pin Type Function INTB#
GPIO 7 I None
INTC#
C
GPI 0 I ATA IDE 1 Detect C
GPIO 8 I LAN Wake Up INTD#
GPI 1 I ATA IDE 2 Detect
GPIO 9 I AC'97 Serial Data In
PCI Slot 2 INTB# AD17
GPI 2 I Reserved
GPIO 10 I Non Connect INTC#
GPI 3 I Reserved INTD#
GPIO 11 I Non Connect
INTA#
GPIO 12 I External SMI
PCI Slot 3 INTC# AD18
GPIO 13 I LPC PME DLED-Super I/O INTD#
AD19
GPIO 14~15 I Not Implemented GPIO Pin Type Function INTA#
INTB#
GPIO 16 O Non Connect GP32 I/OD Not Implemented
GPIO 17 O Non Connect GP24 I/OD Not Implemented PCI Audio INTD#/INTE# AD23
INTA#
B
GPIO 18 O Not Implemented GP34 I/OD Not Implemented B
INTB#
GPIO 19 O Not Implemented GP33 I/OD Not Implemented INTC#
GPIO 20 O Not Implemented
PCI Lan INTC#/INTF# AD22
GPIO 21 O Not Implemented INTD#
INTA#
GPIO 22 O Non
INTB#
GPIO 23 OD BIOS Locked/Unlocked
GPIO 24 O Non
GPIO 25 O Non
GPIO 26 O Non
GPIO 27 I/O Non
A A
GPIO 28 I/O non
GPIO 29~31 I/O Not Implemented Title Rev
Micro-Star MS-6513 0A
Document Number
GPIO Spec.
Last Revision Date:
Thursday, June 21, 2001 Sheet 3 of 35
5 4 3 2 1
8 7 6 5 4 3 2 1
*Trace less 0.5"
CLOCK GENERATOR BLOCK Shut Source Termination Resistors Pull-Down Capacitors
for good filtering from 10K~1M
CPUCLK R233 49.9
U18 CPUCLK# R234 49.9
FB18 X_600 39 41 R246 33 CPUCLK MCHCLK R229 49.9
VCC3 CPU_VDD CPU0 CPUCLK 5
R247 33 CPUCLK# MCHCLK# R230 49.9
+
40 CPUCLK# 5
CB145 Rubycon CT34 CB144 CB154 CPU0# ITP_CLK R232 X_49.9
0.1u 1u 0.1u 36 38 R239 33 MCHCLK ITP_CLK# R236 X_49.9
CPU_GND CPU1 MCHCLK 7
X_COPPER 37 R240 33 MCHCLK# CN16
CPU1# MCHCLK# 7
D CP600 10u D
46 X_10p
MREF_VDD C_STP R243 X_33 ITP_CLK MCH_66
3VMREF/CPU_STP#
45 ITP_CLK 5 Trace less 0.2" 1 2
CB151 44 P_STP R244 X_33 ITP_CLK# ICH_66 3 4
3VMREF#/PCI_STP# ITP_CLK# 5
0.1u 43 49.9ohm for 50ohm M/B impedance AGPCLK 5 6
MREF_GND
7 8
32 31 1 2 MCH_66
3V66_VDD 3V66_0 MCH_66 7
30 RN17 3 4 ICH_66 CN18
3V66_1 ICH_66 10
CB153 33 AGPCLK X_10p
R228 0.1u 29
3V66_2
28
27
5
7
6
8 C157 10p
AGPCLK 17 CLOCK STRAPPING RESISTORS SIO_PCLK 8 7
for good filtering from 10K~1M X_0 3V66_GND 3V66_3 3V66_3 RN25 FWH_PCLK 6 5
6 FS2 7 8 ICH_PCLK 4 3
FB20 X_600 VCC3V FS2/PCI_F0 FS3 ICH_PCLK FS4 R324 10K VCC3V
VCC3 9 7 5 6 ICH_PCLK 9 2 1
PCI_VDD FS3/PCI_F1 MODE FWH_PCLK FS3 R334 10K VCC3V
+
8 3 4 FWH_PCLK 15
CB166 Rubycon CT36 CB178 CB183 MODE/PCI_F2 SIO_PCLK CN17
1 2 SIO_PCLK 11
0.1u 1u 0.1u 5 10 FS4 FS1 R282 X_10K VCC3V X_10p
X_COPPER PCI_GND FS4/PCI0 R308 33 PCICLK4 R283 10K PCICLK0
11 PCICLK4 12 7 8
PCI1
CP601 10u 18 12 R309 33
X_33 PCICLK5
PCICLK5 18
PCICLK1 5 6
PCI_VDD PCI2 PCICLK0 PCICLK2
14 7 8 PCICLK0 18 3 4
CB177 PCI3 RN24 5 PCICLK1 FS0 R321 10K VCC3V PCICLK3
15 6 PCICLK1 18 1 2
0.1u PCI4 33 PCICLK2 R322 X_10K
13 16 3 4 PCICLK2 18
PCI_GND PCI5 17 1 2 PCICLK3 PCICLK4
*Put GND copper under Clock Gen. PCI6 PCICLK3 25
FS2 R326 X_10K C176 X_10p
connect to every GND pin 24 R325 10K VCC3V
48_VDD FS0 R307 33 ICH_48 PCICLK5 C177 X_10p
* 40 mils Trace on Layer 4 FS0/48MHz
22 ICH_48 10
CB164 23 FS1 R281 33 SIO_48 MODE R336 10K
with GND copper around it FS1/24_48MHz SIO_48 11
0.1u 21 AUDIO_14 C179 X_10p
48_GND
* put close to every power pin
C 2 C
REF_VDD MUL0 R251 33 ICH_14 MUL0 R241 X_10K VCC3V ICH_48 C175 10p
* Trace Width 7mils. CB165 MUL0/REF0
48
MUL1 R314 33 AUDIO_14
ICH_14 10
R231 10K SIO_48 C169 10p
1 AUDIO_14 12
0.1u 47 MUL1/REF1
* Same Group spacing 15mils REF_GND MUL1 R316 X_10K VCC3V
* Different Group spacing 30mils 34 3 C171 18p R315 10K
CORE_VDD X1 32pF
* Different mode spacing 7mils on itself CB152 X1 14M-32pf-HC49S-D
0.1u 33 4 C166 18p CRST# R305 10K VCC3V ICH_14 C164 10p
CORE_GND X2
SMBCLK 26 35 R227 475
10,11,16 SMBCLK SCLK IREF
R323 VTT_GD# SMBDATA 25 SMBCLK R255 4.7K used only for EMI issue
VCC3 10,11,16 SMBDATA SDATA VCC3
10K 20 CRST# R306 0 CLK_RST# SMBDATA R254 4.7K
RST# CLK_RST# 19
R318 X_1KVTT_GD# 19 42 R245 4.7K VCC3V Trace less 0.2"
VTT_GD# PWR_DN# VCC3V
Q36
VCCP
NPN-3904LT1-S-SOT23 CYP-CY28324 C_STP R242 1K VCC3V VCC3V R638 47K
R304 220 ICS950208 P_STP R235 1K
CY28323
PRIMARY IDE BLOCK SECONDARY IDE BLOCK
ATA100 IDE CONNECTORS
R190 4.7K IDE2 R186 4.7K IDE1
D2x20-1:21-WH-SBT D2x20-1:21-BL-ZBT
HD_RST# R188 33 1 2 HD_RST# R187 33 1 2
PDD7 3 4 PDD8 SDD7 3 4 SDD8
B 10 PDD[0..7] PDD[8..15] 10 10 SDD[0..7] SDD[8..15] 10 B
PDD6 5 6 PDD9 SDD6 5 6 SDD9
PDD5 7 8 PDD10 SDD5 7 8 SDD10
PDD4 9 10 PDD11 SDD4 9 10 SDD11
PDD3 11 12 PDD12 SDD3 11 12 SDD12
PDD2 13 14 PDD13 SDD2 13 14 SDD13
PDD1 15 16 PDD14 SDD1 15 16 SDD14
PDD0 17 18 PDD15 SDD0 17 18 SDD15
19 19
10 PD_DREQ 21 22 10 SD_DREQ 21 22
10 PD_IOW# 23 24 10 SD_IOW# 23 24
10 PD_IOR# 25 26 10 SD_IOR# 25 26
27 28 R129 470 27 28 R128 470
10 PD_IORDY 10 SD_IORDY
10 PD_DACK# 29 30 10 SD_DACK# 29 30
9 IRQ14 31 32 9 IRQ15 31 32
10 PD_A1 33 34 PD_DET 15 10 SD_A1 33 34 SD_DET 15
10 PD_A0 35 36 PD_A2 10 10 SD_A0 35 36 SD_A2 10
10 PD_CS#1 37 38 PD_CS#3 10 10 SD_CS#1 37 38 SD_CS#3 10
R189 33 39 40 R101 33 39 40
19 PD_LED 19 SD_LED
C79 R119 C76 C81 R120 C77
R191 8.2K 220p 10K X_4700p R103 8.2K 220p 10K X_4700p
VCC5 VCC5
VCC3 VCC3
R407 1K
VCC5_SB VCC5
A RESET BLOCK PCIRST# 9
14
8 HD_RST# A
7
U21D
VCC5_SB 7407-SOIC14
R388 330 Title Rev
VCC3
14
9 PCIRST#
PCIRST# 1 2 PCIRST#1 7,11,12,15,25
VCC5_SB Micro-Star MS-6513 0A
7 R197 330
VCC3
U21A 14 Document Number
7407-SOIC14 C199 PCIRST# 3 4 Clock CY28323/4 & ATA100 IDE
PCIRST#2 17,18
7
X_10p U21B Last Revision Date:
7407-SOIC14 Friday, June 15, 2001 Sheet 4 of 35
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU SIGNAL BLOCK CPU GTL REFERNCE VOLTAGE BLOCK
VCCPS+ 23 VCCP
7 HA#[3..31] VCCPS- 23
ITP_CLK# 4
R81
ITP_DBR#
ITP_CLK 4
2/3*Vccp 49.9
VID[0..4] 11,23
GTLREF1
HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3
VID2
VID1
VID0
VID4
VID3
C49 C48 C58 R79
220p 220p 1u 100
AD26
AC26
AE25
D D
AB1
AE1
AE2
AE3
AE4
AE5
W2
W1
M1
M4
M3
M6
U4