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TDA7293
120V - 100W DMOS AUDIO AMPLIFIER WITH MUTE/ST-BY
VERY HIGH OPERATING VOLTAGE RANGE (±50V) DMOS POWER STAGE HIGH OUTPUT POWER (100W @ THD = 10%, RL = 8, VS = ±40V) MUTING/STAND-BY FUNCTIONS NO SWITCH ON/OFF NOISE VERY LOW DISTORTION VERY LOW NOISE SHORT CIRCUIT PROTECTED (WITH NO INPUT SIGNAL APPLIED) THERMAL SHUTDOWN CLIP DETECTOR MODULARITY (MORE DEVICES CAN BE EASILY CONNECTED IN PARALLEL TO DRIVE VERY LOW IMPEDANCES) DESCRIPTION The TDA7293 is a monolithic integrated circuit in Multiwatt15 package, intended for use as audio class AB amplifier in Hi-Fi field applications (Home Stereo, self powered loudspeakers, TopFigure 1: Typical Application and Test Circuit MULTIPOWER BCD TECHNOLOGY
Multiwatt15 ORDERING NUMBER: TDA7293V
class TV). Thanks to the wide voltage range and to the high out current capability it is able to supply the highest power into both 4 and 8 loads. The built in muting function with turn on delay simplifies the remote operation avoiding switching on-off noises. Parallel mode is made possible by connecting more device through of pin11. High output power can be delivered to very low impedance loads, so optimizing the thermal dissipation of the system.
C7 100nF R3 22K C2 R2 22µF 680 C1 470nF +Vs IN2 7 BUFFER DRIVER 11
+Vs
C6 1000µF
+PWVs 13 14 OUT BOOT LOADER C5 22µF 6 5 BOOTSTRAP CLIP DET VCLIP (*)
IN+
3
+ 12
R1 22K SGND (**) VMUTE R5 10K MUTE 10 MUTE VSTBY R4 22K 1 STBY-GND C3 10µF C4 10µF 8 -Vs C9 100nF -Vs 15 -PWVs C8 1000µF STBY 9 STBY THERMAL SHUTDOWN S/C PROTECTION 4
D97AU805A
(*) see Application note (**) for SLAVE function
October 2000
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TDA7293
PIN CONNECTION (Top view)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 -VS (POWER) OUT +VS (POWER) BOOTSTRAP LOADER BUFFER DRIVER MUTE STAND-BY -VS (SIGNAL) +VS (SIGNAL) BOOTSTRAP CLIP AND SHORT CIRCUIT DETECTOR SIGNAL GROUND NON INVERTING INPUT INVERTING INPUT STAND-BY GND
TAB CONNECTED TO PIN 8
D97AU806
QUICK REFERENCE DATA
Symbol VS GLOOP Ptot SVR Parameter Supply Voltage Operating Closed Loop Gain Output Power Supply Voltage Rejection VS = ±45V; RL = 8; THD = 10% VS = ±30V; RL = 4; THD = 10% Test Conditions Min. ±12 26 140 110 75 Typ. Max. æ 50 40 Unit V dB W W dB
ABSOLUTE MAXIMUM RATINGS
Symbol VS V1 V2 V2 - V3 V3 V4 V5 V6 V9 V10 V11 V12 IO Ptot Top Tstg, Tj Parameter Supply Voltage (No Signal) VSTAND-BY GND Voltage Referred to -VS (pin 8) Input Voltage (inverting) Referred to -VS Maximum Differential Inputs Input Voltage (non inverting) Referred to -VS Signal GND Voltage Referred to -VS Clip Detector Voltage Referred to -VS Bootstrap Voltage Referred to -VS Stand-by Voltage Referred to -VS Mute Voltage Referred to -VS Buffer Voltage Referred to -VS Bootstrap Loader Voltage Referred to -VS Output Peak Current Power Dissipation T case = 70°C Operating Ambient Temperature Range Storage and Junction Temperature Value ±60 90 90 ±30 90 90 120 120 120 120 120 100 10 50 0 to 70 150 Unit V V V V V V V V V V V V A W °C °C
THERMAL DATA
Symbol Rth j-case 2/13 Description Thermal Resistance Junction-case Typ 1 Max 1.5 Unit °C/W
TDA7293
ELECTRICAL CHARACTERISTICS (Refer to the Test Circuit VS = ±40V, RL = 8, Rg = 50 ; T amb = 25°C, f = 1 kHz; unless otherwise specified).
Symbol VS Iq Ib VOS IOS PO Parameter Supply Range Quiescent Current Input Bias Current Input Offset Voltage Input Offset Current RMS Continuous Output Power d = 1%: R L = 4; VS = ± 29V, d = 10% R L = 4 ; VS = ±29V d ISC SR GV GV eN Ri SVR TS Total Harmonic Distortion (**) Current Limiter Threshold Slew Rate Open Loop Voltage Gain Closed Loop Voltage Gain (1) Total Input Noise Input Resistance Supply Voltage Rejection Thermal Protection f = 100Hz; Vripple = 0.5Vrms DEVICE MUTED DEVICE SHUT DOWN STAND-BY FUNCTION (Ref: to pin 1) VST on VST off ATTst-by Iq st-by VMon VMoff ATTmute Duty Stand-by on Threshold Stand-by off Threshold Stand-by Attenuation Quiescent Current @ Stand-by Mute on Threshold Mute off Threshold Mute AttenuatIon Duty Cycle ( pin 5) THD = 1% ; RL = 10K to 5V THD = 10% ; RL = 10K to 5V ICLEAK SLAVE FUNCTION pin 4 (Ref: to pin 8 -VS) VSlave VMaster SlaveThreshold Master Threshold 3 1 V V PO = 50W 3.5 60 80 10 40 1 3.5 70 90 0.5 1.5 1.5 V V dB mA V V dB % % µA A = curve f = 20Hz to 20kHz 100 75 150 160 PO = 5W; f = 1kHz PO = 0.1 to 50W; f = 20Hz to 15kHz VS ± 40V 80 80 100 100 0.005 0.1 6.5 15 80 30 1 2 5 -10 Test Condition Min. ±12 30 0.3 1 10 0.2 Typ. Max. ±50 Unit V mA µA mV µA W W % % A V/µs dB dB µV µV k dB °C °C
MUTE FUNCTION (Ref: to pin 1)
CLIP DETECTOR
Note (1): GVmin 26dB Note: Pin 11 only for modular connection. Max external load 1M/10 pF, only for test purpose Note (**): Tested with optimized Application Board (see fig. 2)
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TDA7293
Figure 2: Typical Application P.C. Board and Component Layout (scale 1:1)
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TDA7293
APPLICATION SUGGESTIONS (see Test and Application Circuits of the Fig. 1) The recommended values of the external components are those shown on the application circuit of Figure 1. Different values can be used; the following table can help the designer.
COMPONENTS R1 (*) R2 R3 (*) R4 SUGGESTED VALUE 22k 680 22k 22k PURPOSE INPUT RESISTANCE LARGER THAN SUGGESTED INCREASE INPUT IMPEDANCE SMALLER THAN SUGGESTED DECREASE INPUT IMPEDANCE
CLOSED LOOP GAIN DECREASE OF GAIN INCREASE OF GAIN SET TO 30dB (**) INCREASE OF GAIN DECREASE OF GAIN ST-BY TIME CONSTANT MUTE TIME CONSTANT INPUT DC DECOUPLING FEEDBACK DC DECOUPLING MUTE TIME CONSTANT ST-BY TIME CONSTANT BOOTSTRAPPING LARGER MUTE ON/OFF TIME LARGER ST-BY ON/OFF TIME LARGER ST-BY ON/OFF TIME LARGER MUTE ON/OFF TIME SMALLER ST-BY ON/OFF TIME; POP NOISE SMALLER MUTE ON/OFF TIME HIGHER LOW FREQUENCY CUTOFF HIGHER LOW FREQUENCY CUTOFF SMALLER MUTE ON/OFF TIME SMALLER ST-BY ON/OFF TIME; POP NOISE SIGNAL DEGRADATION AT LOW FREQUENCY
R5 C1
10k 0.47µF
C2
22µF
C3 C4
10µF 10µF
C5
22µFXN (***)
C6, C8 C7, C9
1000µF 0.1µF
SUPPLY VOLTAGE BYPASS SUPPLY VOLTAGE BYPASS DANGER OF OSCILLATION
(*) R1 = R3 for pop optimization (**) Closed Loop Gain has to be 26dB (***) Multiplay this value for the number of modular part connected
Slave function: pin 4 (Ref to pin 8 -VS)
-VS +3V
MASTER
-VS +1V
UNDEFINED
Note: If in the application, the speakers are connected via long wires, it is a good rule to add between the output and GND, a Boucherot Cell, in order to avoid dangerous spurious oscillations when the speakers terminal are shorted. The suggested Boucherot Resistor is 3.9/2W and the capacitor is 1µF.
-VS
SLAVE
D98AU821
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TDA7293
INTRODUCTION In consumer electronics, an increasing demand has arisen for very high power monolithic audio amplifiers able to match, with a low cost, the performance obtained from the best discrete designs. The task of realizing this linear integrated circuit in conventional bipolar technology is made extremely difficult by the occurence of 2nd breakdown phoenomenon. It limits the safe operating area (SOA) of the power devices, and, as a consequence, the maximum attainable output power, especially in presence of highly reactive loads. Moreover, full exploitation of the SOA translates into a substantial increase in circuit and layout complexity due to the need of sophisticated protection circuits. To overcome these substantial drawbacks, the use of power MOS devices, which are immune from secondary breakdown is highly desirable. The device described has therefore been developed in a mixed bipolar-MOS high voltage technology called BCDII 100/120. 1) Output Stage The main design task in developping a power operational amplifier, independently of the technology used, is that of realization of the output stage. The solution shown as a principle shematic by Fig3 represents the DMOS unity - gain output buffer of the TDA7293. This large-signal, high-power buffer must be capable of handling extremely high current and voltage levels while maintaining acceptably low harmonic distortion and good behaviour over frequency response; moreover, an accurate control of quiescent current is required. A local linearizing feedback, provided by differential amplifier A, is used to fullfil the above requirements, allowing a simple and effective quiescent current setting. Proper biasing of the power output transistors alone is however not enough to guarantee the absence of crossover distortion. While a linearization of the DC transfer characteristic of the stage is obtained, the dynamic behaviour of the system must be taken into account. A significant aid in keeping the distortion contributed by the final stage as low as possible is provided by the compensation scheme, which exploits the direct connection of the Miller capacitor at the amplifier's output to introduce a local AC feedback path enclosing the output stage itself. 2) Protections In designing a power IC, particular attention must be reserved to the circuits devoted to protection of the device from short circuit or overload conditions. Due to the absence of the 2nd breakdown phenomenon, the SOA of the power DMOS transistors is delimited only by a maximum dissipation curve dependent on the duration of the applied stimulus. In order to fully exploit the capabilities of the power transistors, the protection scheme implemented in this device combines a conventional SOA protection circuit with a novel local temperature sensing technique which " dynamically" controls the maximum dissipation.
Figure 3: Principle Schematic of a DMOS unity-gain buffer.
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TDA7293
Figure 4: Turn ON/OFF Suggested Sequence
+Vs (V) +40
-40
-Vs VIN (mV)
VST-BY PIN #9 (V)
5V
VMUTE PIN #10 (V)
5V
IQ (mA)
VOUT (V)
OFF ST-BY PLAY MUTE MUTE
D98AU817
ST-BY
OFF
In addition to the overload protection described above, the device features a thermal shutdown circuit which initially puts the device into a muting state (@ Tj = 150 oC) and then into stand-by (@ Tj = 160 oC). Full protection against electrostatic discharges on every pin is included. Figure 5: Single Signal ST-BY/MUTE Control Circuit
mute functions, independently driven by two CMOS logic compatible input pins. The circuits dedicated to the switching on and off of the amplifier have been carefully optimized to avoid any kind of uncontrolled audible transient at the output. The sequence that we recommend during the ON/OFF transients is shown by Figure 4. The application of figure 5 shows the possibility of using only one command for both st-by and mute functions. On both the pins, the maximum applicable range corresponds to the operating supply voltage. APPLICATION INFORMATION HIGH-EFFICIENCY Constraints of implementing high power solutions are the power dissipation and the size of the power supply. These are both due to the low efficiency of conventional AB class amplifier approaches. Here below (figure 6) is described a circuit proposal for a high efficiency amplifier which can be adopted for both HI-FI and CAR-RADIO applications.
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MUTE MUTE/ ST-BY
10K 20K 30K
STBY
1N4148
10µF
10µF
D93AU014
3) Other Features The device is provided with both stand-by and
TDA7293
The TDA7293 is a monolithic MOS power amplifier which can be operated at 100V supply voltage (120V with no signal applied) while delivering output currents up to ±6.5 A. This allows the use of this device as a very high power amplifier (up to 180W as peak power with T.H.D.=10 % and Rl = 4 Ohm); the only drawback is the power dissipation, hardly manageable in the above power range. The typical junction-to-case thermal resistance of the TDA7293 is 1 oC/W (max= 1.5 oC/W). To avoid that, in worst case conditions, the chip temperature exceedes 150 oC, the thermal resistance of the heatsink must be 0.038 oC/W (@ max ambient temperature of 50 oC). As the above value is pratically unreachable; a high efficiency system is needed in those cases where the continuous RMS output power is higher than 50-60 W. The TDA7293 was designed to work also in higher efficiency way. For this reason there are four power supply pins: two intended for the signal part and two for the power part. T1 and T2 are two power transistors that only operate when the output power reaches a certain threshold (e.g. 20 W). If the output power increases, these transistors are switched on during the portion of the signal where more output voltage swing is needed, thus "bootstrapping" the power supply pins (#13 and #15). The current generators formed by T4, T7, zener diodes Z1, Z2 and resistors R7,R8 define the minimum drop across the power MOS transistors of the TDA7293. L1, L2, L3 and the snubbers C9, R1 and C10, R2 stabilize the loops formed by the "bootstrap" circuits and the output stage of the TDA7293. By considering again a maximum average output power (music signal) of 20W, in case of the high efficiency application, the thermal resistance value needed from the heatsink is o 2.2 C/W (Vs =±50 V and Rl= 8 Ohm). All components (TDA7293 and power transistors T1 and T2) can be placed on a 1.5oC/W heatsink, with the power darlingtons electrically insulated from the heatsink. Since the total power dissipation is less than that of a usual class AB amplifier, additional cost savings can be obtained while optimizing the power supply, even with a high heatsink . BRIDGE APPLICATION Another application suggestion is the BRIDGE configuration, where two TDA7293 are used. In this application, the value of the load must not be lower than 8 Ohm for dissipation and current capability reasons. A suitable field of application includes HI-FI/TV subwoofers realizations.
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The main advantages offered by this solution are: - High power performances with limited supply voltage level. - Considerably high output power even with high load values (i.e. 16 Ohm). With Rl= 8 Ohm, Vs = ±25V the maximum output power obtainable is 150 W, while with Rl=16 Ohm, Vs = ±40V the maximum Pout is 200 W. APPLICATION NOTE: (ref. fig. 7) Modular Application (more Devices in Parallel) The use of the modular application lets very high power be delivered to very low impedance loads. The modular application implies one device to act as a master and the others as slaves. The slave power stages are driven by the master device and work in parallel all together, while the input and the gain stages of the slave device are disabled, the figure below shows the connections required to configure two devices to work together. The master chip connections are the same as the normal single ones. The outputs can be connected together without the need of any ballast resistance. The slave SGND pin must be tied to the negative supply. The slave ST-BY and MUTE pins must be connected to the master ST-BY and MUTE pins. The bootstrap lines must be connected together and the bootstrap capacitor must be increased: for N devices the boostrap capacitor must be 22µF times N. The slave IN-pin must be connected to the negative supply. THE BOOTSTRAP CAPACITOR For compatibility purpose with the previous devices of the family, the boostrap capacitor can be connected both between the bootstrap pin (6) and the output pin (14) or between the boostrap pin (6) and the bootstrap loader pin (12). When the bootcap is connected between pin 6 and 14, the maximum supply voltage in presence of output signal is limited to 100V, due the bootstrap capacitor overvoltage. When the bootcap is connected between pins 6 and 12 the maximum supply voltage extend to the full voltage that the technology can stand: 120V. This is accomplished by the clamp introduced at the bootstrap loader pin (12): this pin follows the output voltage up to 100V and remains clamped at 100V for higher output voltages. This feature lets the output voltage swing up to a gate-source voltage from the positive supply (VS -3 to 6V)
TDA7293
Figure 6: High Efficiency Application Circuit
+50V D6 1N4001 D1 BYW98100 +25V R17 270 L1 1µH C12 330nF R20 20K C1 1000µF 63V C3 100nF C5 1000µF 35V C7 100nF R22 10K GND C9 330nF R1 2 PLAY ST-BY R23 10K C8 100nF R2 2 C10 330nF D5 1N4148 IN R12 13K 4 C13 10µF 9 R13 20K R14 30K R15 10K 10 C14 10µF 1 8 15 12 3 7 13 2 T1 BDX53A
T3 BC394
R4 270 T4 BC393
R5 270 T5 BC393 R6 20K
D3 1N4148 Z1 3.9V R3 680 R16 13K C11 22µF
L3 5µH
R7 3.3K
C16 1.8nF OUT
TDA7293
14 6 R18 270 C15 22µF R8 3.3K Z2 3.9V C17 1.8nF
P ot
R21 20K
C2 1000µF 63V
C4 100nF
C6 1000µF 35V
L2 1µH
D4 1N4148 T7 BC394 R9 270 R10 270 T8 BC394 R11 20K
D2 BYW98100 -25V D7 1N4001 -50V
R19 270 T2 BDX54A
T6 BC393
D97AU807C
Figure 6a: PCB and Component Layout of the fig. 6
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TDA7293
Figure 6b: PCB - Solder Side of the fig. 6.
Figure 7: Modular Application Circuit
C7 100nF +Vs C6 1000µF
MASTER
C2 22µF R2 680 C1 470nF R1 22K SGND VMUTE VSTBY R4 22K R5 10K MUTE STBY
R3 22K BUFFER DRIVER 7 11
+Vs IN2
+PWVs 13 14 OUT BOOT LOADER C10 100nF R7 2
IN+
3
+ 12
4 10 MUTE 9 STBY 1 C4 10µF STBY-GND 8 -Vs C9 100nF THERMAL SHUTDOWN S/C PROTECTION 15 -PWVs C8 1000µF -Vs +Vs C7 100nF BUFFER DRIVER 7 11 C6 1000µF 6 5
C5 47µF BOOTSTRAP CLIP DET
C3 10µF
+Vs IN2
+PWVs 13 14 OUT BOOT LOADER
IN+
3
+ 12
SLAVE
SGND MUTE 4 10 9 STBY 1 STBY-GND 8 -Vs C9 100nF -Vs
MUTE STBY THERMAL SHUTDOWN S/C PROTECTION 15 -PWVs C8 1000µF
6 5
BOOTSTRAP
D97AU808D
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TDA7293
Figure 8a: Modular Application P.C. Board and Component Layout (scale 1:1) (Component SIDE)
Figure 8b: Modular Application P.C. Board and Component Layout (scale 1:1) (Solder SIDE)
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TDA7293
mm MIN. TYP. MAX. 5 2.65 1.6 1 0.49 0.66 1.02 17.53 19.6 20.2 21.9 21.7 17.65 17.25 10.3 2.65 4.25 4.63 1.9 1.9 3.65 4.55 5.08 22.2 22.1 17.5 10.7 22.5 22.5 18.1 17.75 10.9 2.9 4.85 5.53 2.6 2.6 3.85 0.862 0.854 0.695 0.679 0.406 0.104 0.167 0.182 0.075 0.075 0.144 0.179 0.200 0.874 0.870 0.689 0.421 1.27 17.78 0.55 0.75 0.019 0.026 0.050 0.700 0.039 0.022 0.030 0.060 0.710 0.795 0.886 0.886 0.713 0.699 0.429 0.114 0.191 0.218 0.102 0.102 0.152 MIN. inch TYP. MAX. 0.197 0.104 0.063
DIM. A B C D E F G G1 H1 H2 L L1 L2 L3 L4 L7 M M1 S S1 Dia1
OUTLINE AND MECHANICAL DATA
1.52 0.040 18.03 0.690 0.772
Multiwatt15 V
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TDA7293
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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