Text preview for : 501_917_01A.pdf part of Keithley 501 917 01A Keithley Misc 501_917_01A.pdf
Back to : 501_917_01A.pdf | Home
TRGI
Analog Trigger Module
introduction
The TRGl Analog Trigger Module (Figure 1) contains circuitry for one channel of real-time,
hardware-based triggering of analog data acquisition. The TRGl module is designed for use with
the Keithley AMMlA or AMM2 Analog Master Measurement module, revision D or later, which
will be referenced hereout as "AMM module".
The TRGl controls the AMM module's high-speed "auto-acquire" mode which is driven by a crystal
oscillator located on the AMM. The TRGl provides an A/D start signal which travels over a dedi-
cated pathway and initiates A/D conversion on the AMM module. As an alternative to triggering
on an analog input, the TRGl can also initiate A/D conversion in response to a global strobe com-
mand sent from the data acquisition mainframe.
The TRGl module has input ranges of 0 to + IV, 0 to -IV, 0 to + lOV, and 0 to -lOV with an input
resistance of 10 megohms. Coupling is selectable for AC or DC signals. Input signals are applied to
the TRGl external signal input through a quick-disconnect screw terminal block located on the
module, or to the TRGl global amplifier input via a cable which connects to the AMM global
amplifier output. The TRGl triggering threshold is set by a programmable, 8-bit D/A converter. A
programmable low-pass falter provides input liltering with eight cut-off frequencies from 3OOHz to
lMHz. This filter can be used to eliminate noise on the trigger signal which may otherwise cause
false triggering.
Beside starting an A/D conversion, the TRGl trigger signal can also assert an Interrupt Request
(IRQ) to the host computer via the IBIN interface card, which can then be used to implement
special-purpose, user-written service routines. Check the documentation and revision level of your
IBIN interface to determine whether this feature is implemented on the IBIN.
The number of possible trigger configurations is a function of the number of TRGl modules in the
system, and how the mode, reset, and cycling features are programmed. These programming tasks
are handled automatically by higher-level languages such as Keithley's KDACSOO.
U"~UIII"IIC A.u AI"". ., . .a,7-01 R&y0 -A-
nnawmmnt Nnqnhc=-+ 501-W
Copyright (c) 1989 Keithley Instruments, Inc., Cleveland, OH 44139 (216)248-0400
TRGl-1
,
OO 0 I
ol3oonlYoooooooo I
0
0
0
cz
dl
I
,
,
,
,
,
,
, omo
(
<
(
(
(
C
C
E
omo
!C
C
C
C
C
C
C
,
C
f
omc
00
(
,
:
&O
0
:
o-lo
030
oEiilo omo
I
:
0
00
:
a
0
FIGURE 1. TRGl MODULE
TRGl-2
The TRGl offers two trigger modes:
1. Single-event Mode, in which the TRGl generates a single trigger start command the first time
the programmed trigger condition is met, or
2. Normal Mode, in which the TRGl generates a trigger start command each time the programmed
trigger condition is met.
The trigger level generated by the TRGl is latched when the programmed trigger condition is met.
This trigger latch can be reset in one of two ways. The desired reset method must be programmed
by writing the appropriate bits to the TRGl CMDA register:
1. Manual reset - reset by reading of the CMDB control register, and
2. Automatic reset - reset automatically when the trigger condition is no longer met.
The cycling of the trigger operation can be programmed for two modes:
1. One-shot - take a single reading
2 Continuous - take readings continuously as long as the trigger condition is met.
Typical trigger modes include, but aren't limited to, the following (see Figure 2):
1. Trigger at a user-defined threshold on the falling slope of the trigger signal. Stop when the pres-
cribed number of points has been acquired.
2 Trigger at a user-defined threshold on the rising slope of the trigger signal, and acquire data only
when the signal is above the threshold. Stop when the prescribed number of points has been
acquired.
3. Trigger at a user-defined threshold on the falling slope of the trigger signal, and acquire data only
the first time the signal is below the threshold level. Stop when the signal rises above the threshold.
4. Trigger at a user-defined threshold on the rising slope of the trigger signal and take only one
reading. (Normally used to trigger a reading off another channel.)
5. Trigger at a user-defined threshold on the falling slope of the trigger signal and acquire one read-
ing. Repeat each time the trigger condition is met until the prescribed number of points has been
acquired. (Normally used to synchronize readings to an external event.)
Information for implementing these trigger setups is included later in this manual.
TRGl - 3
DATA ACQUISITION & CONTROL
TRGI 0 PROGRAMMABLE
TRIGGER MODULE
1. Trig(lera! a use+deiined
threshold the fallii slopeof he trigger
on
s&d. Slopwhen prescribed
the number pin!s havebean
of aaqhd.
FIGURE 2. TYPICAL TRGl TRIGGER MODES
TRGl - 4
Hardware Compatibility
The TRGl module is compatible with the Keithley 5OOA,5OOP,and 575 data acquisition systems.
When used with these systems, the TRGl module requires that a revision D or later AMMlA or
AMM2 Analog Master Measurement module be mounted in slot 1.
When one TRGl module is to be used with a Model 500A or 5oOP, it must be used in slot 2. The
500~series systems can operate with two TRGl modules, in which case the second TRGl must be
plugged into slot 3. The TRGl pair can perform various trigger operations based on ANDing or
ORing of the trigger input signals.
The Model 575 contains the equivalent of a TRGl module built into its main circuit board. A
TRGl may be mounted in the Model 575 option slot (assigned as slot 3) to obtain the functionality
of two TRGl modules.
The TRGl module is not compatible with the System 570, with the original AMMl (pre rev "A
version) module, or with older AIMl/ADMx analog input module sets.
Software Compatibility
The TRGl module can be programmed and operated using Keithley's KDACSOO software pack-
ages, or with any software which specifically supports the TRGl. All TRGl features, such as input
range, AC/DC input coupling, input filtering, and edge sensitivity are controlled through software.
In using the TRGl module, you must decide whether you want to trigger from an input applied to
the TRGl external input terminals, or the TRGl global amplifier input connector. Each method
facilitates different trigger setups which may be better suited to a given application. This input
selection is controlled through software.
When operated under KDACSOO, the trigger function requires simultaneous use of the KDACSOO
ANINQ and ANTRIG commands. To trigger from a signal connected to a TRGl external input
channel 52, set up an IONAME for ANTRIG which references the slot (and channel 0) of the
specific TRGl. This automatically informs the software that triggering is to be based on the TRGl
external input 52.
Use of the TRGl global amp input permits the TRGl to trigger from any analog input signal con-
nected to any AMM or AIM analog input module. Set up an IONAME parameter for ANTRIG
which references the desired analog input slot and channel. This automatically sets the software for
triggering on the signal at the TRGl global amp input 53 or 54. That signal will automatically be
routed through the global amplifier of the AMM module to the global amplifier input of the TRGl
module.
You may also program the TRGl module by directly accessing its command registers. See Table 1
later in this manual for a complete listing of TRGl command registers and functions.
Keithley's Soft500 and Quick500 do not directly support the TRGl, although BASIC PEEK and
POKE commands can be used to access the TRGl command locations.
TRGl-5
Specifications
Channels: 1, differential input
Trigger Source: External trigger input terminals, Global Amplifier output of AMMlA or AMM2
analog module, or Software Strobe.
Input Ranges: 0 to + IV, 0 to -IV, 0 to + lOV, or 0 to -lOV.
Resolution: 8 bits
Level Accuracy: 22% + 1 L.SB
Input Impedance: 10 Mfl (external trigger input)
Input Protection: ?3OV maximum (powered); +15V maximum (unpowered)
Input Coupling: AC or DC
Trigger: Rising or falling edge (positive or negative slope)
Input Connector: 3-pin quick-disconnect screw terminal block for external input. Cable (CA-85-l)
to AMM card global amplifier (supplied).
Input Filter: Software-selectable single pole low-pass filter with the following characteristics:
-3dB Frequency Settling Time to l/2 LSB
1 MHz 1PS
300 kHz 3.3 j.Ls
100 kHz 10 /J-Is
30 kHz 33 ps
10 kHz 100 /.Ls
3kHz 333 ps
1kHZ 1mS
3OOHz 3.3 mS
Output: 1. Low-true trigger signal to motherboard connector for triggering AMMlA or
AMM2 in adjacent slot,
2. Interrupt Request (IRQ) to the host computer,
3. Status register
Note: IRQ is open-collector low-true pulse 500 nS typical. A/D trigger signal is
software selectable to be either a 5OOnSlow-true pulse, or a low-true level.
Note: The TRGl requires a + 1OV reference signal to be present on the back-
plane, which is typically provided by an AMMlA or AMM2 module used in slot 1.
If one TRGl is used in a system, it must be placed in slot 2. If two TRGl modules
are used in a system, they must be placed in slots 2 and 3.
TRGl-6
Trigger Signal Connection
The trigger input signal may be connected to the TRGl module by two methods.
The first method involves simply connecting the trigger signal leads to the external analog trigger
input 52. This is a quick-disconnect block located on the rear of the TRGl module. Three screw ter-
minals provide for one channel of differential input. Connect the high (+) side of the trigger input
signal to the HI terminal screw of 52. Connect the low (-) side of the trigger input signal to the LO
terminal screw of 52. Connector 52 includes a ground terminal for connecting the shield of the input
cable.
CAUTION: The differential inputs of the TRGl module must both be within flOV of module
ground for proper operation. If either side of the signal is greater than 23OV, the TRGl may be
damaged.
The second method for connecting a trigger input is to attach a cable between the TRGl Global
Amplifier Input, 53 or 54, and the AMM module Global Amplifier Output 57. A special shielded
cable CA-85-l is supplied with the TRGl module for this purpose. The (X-85-1 cable is con-
structed with a chamfer on one corner of the plastic housing which terminates the cable. This cham-
fer indicates the center, signal-carrying conductor of the cable, and should be positioned toward the
front of the data acquisition system where the cable connects to the TRGl, and toward the rear of
the system where the cable connects to the AMM module (see Figure 3).
AMM Module - Slot I
FlGURE 3. TRIGGER CABLE CA-851
TRGl-7
In a 500-series system with two TRGls, or a Model 575 with one TRGl, the trigger signals may be
connected to the AMM global amp by using a pair of CA-85-l cables. The high and low sides of 53
and 54 on the TRGl are connected in parallel. For this application, connect 57 of the AMM to 53 of
the first TRGl module. Connect 54 of the first TRGl module to 53 or 54 of the second TRGl.
CAUTION: Improper connection of the trigger cable may degrade the signal or introduce
excessive noise into measurements.
Installation
Installation of the TRGl module involves configuration, jumper placement, and interconnection of
the TRGl and AMM modules.
CAUTION: Turn off power to the data acquisition system before you insert or remove any module.
To minimize the possibility of EMI radiation, always operate the data acquisition system with the
cover in place and properly secured.
Installation of One or `lko TRGl Modules in a 500A or 500P
The TRGl may be operated in slot 2, or slots 2 and 3 of a 500A or 500P data acquisition system. To
install the TRGl in a 500-series system, first remove the top cover.
Single Trigger Input - to trigger an AMM module off a single trigger signal, plug the TRGl module
into slot 2. Set jumpers and connections as follows:
TRGl module - Locate the Cpin jumper Wl. Jumper pin 1 to pin 2. Connect the trigger signal to
the TRGl external or global input.
AMM module - place jumper 53 over pins 1 and 2. Connect the signal of interest to one of the
AMM input channels.
Dual Trigger Inputs - to trigger an AMM module off some combination of two trigger signals, plug
TRGl modules into slots 2 and 3. Set jumpers and connections as follows:
"OR" Operation (data will be acquired when the trigger conditions assigned to either trigger input is
satisfied):
Slot 2 TRGl module - Locate the 4-pin jumper Wl on the TRGl module. Jumper pin 1 to pin 2,
and pin 3 to pin 4 (2 jumper blocks required). Connect one trigger signal JO the TRGl external or
global input.
Slot 3 TRGl module - Locate the 4-pin jumper Wl on the TRGl module. Jumper pin 1 to pin 2,
and pin 3 to pin 4 (2 jumper blocks required). Connect the other trigger signal to the TRGl
external or global input.
TRGl-8
AMM module - place the jumper 53 over pins 1 and 2. Connect the signal of interest to one of the
AMM input channels.
"AND"Operation (data will be acquired only when the trigger conditions assigned to both trigger
inputs are satisfied):
Slot 2 TRGl module - Locate the cl-pin jumper Wl on the TRGl module. Jumper pin 2 to pin 3 (1
jumper block required). Connect one trigger signal to the TRGl external or global input.
Slot 3 TRGl module - Locate the 4-pin jumper Wl on the TRGl module. Connect pin 1 to pin 2,
and pin 3 to pin 4 (2 jumper blocks required). Connect the other trigger signal to the TRGl
external or global input.
AMM module - place the jumper 53 over pins 1 and 2. Connect the signal of interest to one of the
AMM input channels.
Installation of TRGl in the Model 575
You may add a TRGl to the Model 575 for dual triggering capability. The TRGl will involve addi-
tional jumper configurations on the AMM module and Model 575 motherboard. See the 575
manual for more information on jumper placement.
NOTE: Your Model 575 manual may identify TRGl jumper Wl as "53".`Ibis is an earlier jumper
designation. Wl is the only 4-pin jumper on the TRGl.
NOTE: To gain access to the jumpers on the AMM module and 575 motherboard, you must
remove the AMM module from slot 1. The TRGl will occupy the option slot 3.
Dual Trigger Inputs - to trigger an AMMlA or AMM2 analog input module off some combination
of two trigger signals, add a TRGl module to slot 3. Set jumpers and connections as follows:
"OR"Operation (data will be acquired when the trigger condition assigned to either trigger input is
satisfied):
575 trigger jumpers - Locate W201. Jumper pin 1 to pin 2, and pin 3 to pin 4 (2 jumper blocks
required). Connect one trigger signal to the 575 external or global trigger input.
Optional TRGl module - Locate 4-pin jumper Wl. Jumper pin 1 to pin 2, and pin 3 to pin 4 (2
jumper blocks required). Connect the other trigger signal to the TRGl external or global input.
AMM module - place the jumper 53 over pins 1 and 2. Connect the signal of interest to one of the
AMM input channels.
"AND"Operation (data will be acquired only when the trigger conditions assigned to both trigger
inputs are satisfied):
575 trigger jumpers - Locate W201. Jumper pin 2 to pin 3 (1 jumper block required). Connect one
trigger signal to the 575 external or global trigger input.
TRGl-9
Optional TRGl module - Locate the 4-pin jumper Wl. Connect pin 1 to pin 2, and pin 3 to pin 4 (2
jumper blocks required). Connect the other trigger signal to the TRGl external or global input.
AMM module - place the jumper 53 over pins 1 and 2. Connect the signal of interest to one of the
AMM input channels.
Theory of Operation
Refer to the TRGl schematic drawings at the end of this manual for the following discussion:
The triggering circuit can be divided into three sections: the command decoding circuitry, the
analog input and comparator circuitry, and the trigger/level selection circuitry.
In the command circuitry, input data from the PC bus is latched by octal latch/buffers U13, U14,
and Ill5 (74LS273). Output data to the bus is buffered out by the octal transparent latch Ill.5
(74LS373). Command and read/write information is decoded by Ull, U12, and U16. Analog input
selection is accomplished by quad analog SPST switch Ul (DG211). Component U23 (74LSl.53)
selects either analog inputs (determined by Ul) or digital (Global Strobe) triggering inputs, and
provides the logic input for chaining two TRGl modules together.
The CMDA write cycle controls trigger input and configures the trigger and IRQ outputs. The
CMDB write cycle controls the selection of filter, range, AC or DC coupling, and triggering edge.
The CMDC write cycle latches the trigger level data (in counts) into the D/A converter U8
(AD7523JN) by the octal latch/buffer U24 (74LS273).
The CMDA read cycle passes the trigger status information to the PC data bus with Ul.5. The
CMDB read cycle also retrieves status information. Additionally, it performs a manual reset of the
trigger and IRQ latching circuits. A CMDC read is not implemented.
There are four possibilities of input selection: external analog input (EXT TRIG IN) at J2, global
amplifier input (GLOBAL IN) at 53 and 54, update from the global strobe, and no trigger input.
Input selection is accomplished by electrically switching the input with the quad SPST analog switch
Ul; by disabling both inputs and strobing the addressing of the demultiplexer at U23, or deselecting
all inputs. Gain selection is performed by switching precision resistors in and out of the feedback
circuitry of the dual JFET op amp U2 (LF412CN) with analog switch U3A. Input coupling for AC
is selected by opening the analog switch U3B.
The trigger threshold voltage is subtracted from the amplified trigger signal via U4A which moves
the trigger voltage to zero volts. Components Ql, Q2, R12, and Dl through D6 form an anti-
saturation clamp circuit for the output of the differential amplifier U4A, which prevents the output
of U4A from exceeding the + 1OV or -lOV clamp reference voltages provided by U6A and U6B.
Filtering of the input signal is accomplished by a series of precision resist,ors (R2l3 through R219),
an &channel analog demultiplexer U5 (IH6108) and a capacitor (C24l2). The filter cap is fed by
switching in one of the seven (or no) resistors to form a single-pole low pass filter with cut-off fre-
quencies of 3OOHz, lkHz, 3kHz, lOkHz, 3OkHz, lOOkHz, 3OOkHz, and 1 MHz. The eighth resistor is
not used for the 1MHz filter because the ON resistance of U5 functions as the filter resistor.
TRGl-l0
Polarity selection is performed by switching the reference voltage on the D/A converter US
between + 10 and -10 volts. Edge selection is performed by demultiplexing the inputs from the dual
one shot U17 (74LS221) in the 4-to-2 demultiplexer U18 (74ISl.53) to separate IRQ and trigger
pulses dependent upon the trigger region status. The POS PULSE output from U17A is enabled
whenever the input is above the trigger voltage. This 5OOnsecpulse is switched to the 2Y output of
U18 when triggering on the rising edge is selected, Similarly, the NEG PULSE output from U17B
is switched to the 2Y output when the input is below the trigger voltage and triggering on the fallmg
edge is selected. The IRQ is handled similarly but is dependent upon the selection of IRQ on trig-
ger start or trigger ftnished.
For input to the trigger circuit from the AMM global amplifier, a low-loss transmission line is
included with the TRGl module. Since the global output amplifier on the AMM card is capable of
amplifying at relatively high frequency, a low capacitance connection is required to minimize distor-
tion of the input to the trigger circuit. For low frequency applications, a regular wired connection
would be sufficient. In any case, a wired path must be provided to the global amp input of the trig-
ger circuit (ii used) as none is provided on the motherboard.
Two jumpers are located on the TRGl board in a single 4 pin header identified as Wl. Applications
using one or two trigger circuits require that these jumpers be set properly. Where a TRGl module
is used with a Model 575, the 575 trigger is functionally equivalent to a TRGl module in slot 2. The
TRGl in the 575 option slot is functionally equivalent to a TRGl in slot 3.
One Trigger Circuit
Jumper pins 1 to 2, and 3 to 4 to enable A/D triggering on the AMM module installed in slot 1.
lb0 Trigger Circuits
The use of two trigger circuits permits triggering A/D on (A or B) or (A and B).
LOGICAL OR (A or B) - Jumper pins 1 to 2 and 3 to 4 on the TRGl in both slots.
LOGICAL AND (A and B) - Jumper pins 2 to 3 on the slot 2 TRGl. Jumper pins 1 to 2 and 3 to 4
on the slot 3 TRGl.
TRGI Power-On State
The TRGl module uses a power-up reset circuit to insure that the module energizes in a known
state. All bits in the CMDA, CMDB, and CMDC control registers are set to 0, which results in the
following power-up conditions:
The trigger voltage is OV on the 1V range
Polarity is negative
No trigger input is selected
IRQ and A/D trigger are disabled
TRGl - 11
The trigger is set up for continuous mode on all events of the trigger condition
Trigger latching is disabled.
The 1MHz filter is selected
Trigger is set for falling edge and DC coupling.
TRGI Commands and Command Locations
The command locations (control addresses) associated with the trigger function are Commands A,
B, and C (CMDA, CMDB, and CMDC) for slots 2 and 3 of the 5OOA,500P or Model 575. Any soft-
ware packages which specifically support the TRGl will normally communicate with these
addresses directly, and the process will be transparent to the user.
In some cases, you may want to access the TRGl command locations directly. An typical example
might be where you are writing a program "from scratch" using only a general-purpose language
such as BASIC, C, Assembler, etc.
See the following charts for detailed information.
TABLE 1. TRGl COMMAND LOCATIONS AND FUNCTIONS
Read Functions:
COMMAND FUNCTION
CMDA Read trigger status
CMDB Read trigger status and reset TRG/IRQ latches
Write Functions:
COMMAND PUNCTION
CMDA Interrupt and trigger setup
CMDB Select filter, range, coupling, and edge
CMDC Set trigger voltage
TRGl-Il.2
TABLE 1. TRGI COMMAND LOCATIONS AND FUNCTIONS, cont'd
TRGl
Global Global Strobe
FILTERS
Input Source Instr. Amp
CMDA Range, Polarity Filter Select
CMDB CMDA
DIVRITE) Coupling
CMDB DIIRW
(WRITE)
- 8 BITLATCH + A/D Trigger
DO -- &
D7 - DIA uxx ---km
Trigger Voltage IRCXTrig Setup
CMDA,CMDB
(WRI-W
CMDA (write) - IRQ and Trigger setup
D7 D6 D5 D4 D3 D2 Dl DO
Interrupt request(IRQ) :Enable(l), Disable(O)
IRQ on trigger: Finished(l), Start(O)
A/D Trigger: Enable (11, Disable(O)
Trigger Latch: Enable(l), Disable(O)
Trigger Periodicity: One shot(l), COntinUOUS(O)
Trigger Mode: Single event(l), Normal(O)
Trigger Input: None.(O)
Global Strobe(l),
Global Amp Output(2),
Ext. Analog input(3)
CMDB (write) - Select Filter, Range, Coupling, Edge
D7 D6 D5 D4 03 D2 Dl DO
Filter: 1MHz (O), 300KHz (l),
1OOKHz (21, 30KHz (31,
1OKHz (4), 3KHz : (5),
1KHZ (6), 300Hz (7)
Trigger Voltage Range: 0-lOV(l), 0-lV(O)
Trigger Range Polarity: Positive(l), Negative(O)
Coupling: AC(l), DC(O)
Trigger Edge: Rising(l), Falling(O)
TRGl - 13
TABLE 1. TRG1 COMMAND LOCATIONS AND FUNCTIONS, concluded
CMDC (write) - Trigger Voltage (0 - 255)
CMDA (read) - Read Status
D7 D6 D5 D4 D3 D2 Dl p
Interrupt request(IRQ) :Enabled(l), Disabled(O)
IRQ on trigger: Finished(l), Start(O)
A/D Trigger: Enabled(l), Disabled(O)
Trigger Latch: Enabled(l), Disabled(O)
Trigger Valid (1) - signal in trigger region
IRQ was asserted (1)
Trigger was asserted (1)
TRGl now triggered (1)
CMDB (read) - Reset Trigger and One Event Latch
Data same as CMDA Read Above
CMDC (read) - Not used
TRGl - 14
Command Locations in Numeric Order
The following information offers more details on the use of command locations for the TRGl
module, as well as applicable locations associated with the AMMlA and AMM2 analog input
modules. The addresses shown presume that the TRGl module is mounted in slot 2. For a TRGl
mounted in slot 3, use the second set of addresses which are shown in parentheses 0.
The fast three characters of each memory location are shown as "xxx".Normally, these characters
would be "CFF', assuming that the IBIN interface card memory map switch is set for address
CFFSO.
For a further discussion of analog input commands, also refer to your AMM module manual.
CMDlA, Address xx60 - SELECT A/D CHANNEL
The SELECT CHANNE L command is used to control the local signal multiplexer on the AMM
module installed in slot 1. Refer to the appropriate AMMlA or AMM2 manual for a discussion of
this command.
CMDlB, Address xxxS1 - SELECT SLOT
The SELECT SLOT command controls the global multiplexer on the AMM module installed in
slot 1. Refer to the appropriate AMM manual for a discussion of this command.
CMD2A, (CMD3A) - ANALOG TRIGGER AND IRQ CONFIGURATION
Control addresses are xxxS2 for CMD2A, or xxxS4 for CMD3A.
The analog trigger circuit can produce two separate outputs: a trigger signal that can start A/D
conversion on the AMM module installed in slot 1, and an Interrupt Request (IRQ) that can divert
the processor in the host PC to a servicing routine to perform programmed functions in the back-
ground.
Trigger input can come from any of 3 sources: from asserting a GLOBAL STROBE, from the
external analog input (at J2), or from the output of the global amplifier on the AMM module in slot
1. The four possible selections for input include those mentioned above in addition to a no input
setting, used at power up of the circuit.
Writing to this command location configures the interrupt request, trigger mode, and selects the
trigger input for the analog trigger circuit. Reading this command location returns the contents of
the trigger status register.
The triggering and IRQ output can operate in several modes. IRQ can be enabled or disabled, and
asserted either on the beginning of a trigger condition, or when the trigger condition is no longer
true. IRQ can operate even if the trigger is disabled. However, the triggering parameters must still
be configured as if triggering were going to be used. Triggering can be enabled or disabled. The
triggering can be latched or automatically reset. Additionally, the triggering can be used in one shot
mode, where the trigger pulses for 500 nS when a triggering condition is satisfied, or in a continuous
TRGl - 15
mode where the trigger is latched into an asserted state until the triggering condition is no longer
satisfied. Finally, the trigger can be set to trigger as a single event (where a reset must be performed
before a trigger can be asserted again) or in a normal mode where the trigger asserts with each
entry into the trigger region.
Reading from this location returns a byte that can be interpreted as the TRIGGER STATUS word.
This should be used if status information is desired, but no reset of the trigger is to be asserted.
CMD;?B, (CMD3B) - ANALOG TRIGGER INPUT CONFIGURATION
Control addresses are xxxS3 for CMD2B, or xc&5 for CMD3B.
Writing to this command location allows the configuration of the input to the analog trigger circuit;
selection of the input filter, trigger voltage range, trigger voltage polarity, input coupling, and trig-
gering edge are selected by the appropriate binary data word. Reading this command location also
returns the contents of the status register, and additionally performs a reset of the trigger and one
event latch if the trigger is configured for one event or single mode triggering.
The main feature of the analog triggering circuit is its ability to provide a triggering signal with con-
trol similar to that of an oscilloscope. Therefore, the object input signal must be analyzed to
determine if it meets a triggered condition. These conditions include input magnitude, input
polarity, and whether the signal is on a rising edge or falling edge. These conditions, as well as
filtering (8 ranges, from 300 Hz to 1 MHz) and input coupling, are selectable by writing to location
CMD2B (CMD3B).
Performing a read of the CMD2B (CMD3B) location will return the same TRIGGER STATUS
word as reading location CMD2A (CMD3A). However, reading the CMD2B (CMD3B) register
will reset all the latches on the card.
CMD2C, (CMD3C) - ANALOG TRIGGER VOLTAGE (O-255 COUNTS)
Control addresses are xxx98 for CMD2C, or xxx99 for CMD3C.
Writing to this command location sets the output of the D/A converter in the analog triggering cir-
cuit to a voltage between 0 and 10 volts, with a resolution of approximately 47mV (1 part in 256).
To determine the counts necessary, use the following formula:
COUNTS = ABS[(VOLTS / RANGE) x 2561
where volts = the desired trigger voltage, range = the setting of the range bit (1OV or IV), and
counts = number of DAC counts necessary for the desired output. This information must be writ-
ten to CMDC for the desired slot.
Writing to this location sets the absolute magnitude at which triggering will occur in DAC counts. A
conversion, based upon selected range and level, will give the proper number of counts (see the
command description given above for the formula).
TRGl - 16
CMDlC, Address x&A - GLOBAL GAIN
The GLOBAL GAIN command controls the PGA (Programmable Gain Amplifier) located on the
AMM module installed in slot 1. For a discussion of this command, refer to the appropriate AMM
manual.
CMDlD, Address xxx9B - A/D START/STATUS
Writing to this command location starts A/D conversion on the AMM module installed in slot 1.
Any value can be written to trigger conversion; however, a value of 255 should be written to mini-
mize noise. Reading this location returns the status byte of the A/D conversion (busy or ready). A
value of 255 (FF in hex) indicates that the conversion process is under way. A value of 127 (7F hex)
indicates that the conversion is complete.
Typical Applications
The following examples illustrate some typical triggering modes. These are shown if Figure 4.
These routines can be implemented in any language by accessing the various command registers of
the AMM and TRGl modules. Higher level languages which support the TRGl (such as
KDAC500) will have commands which facilitate different trigger set-ups without requiring low-level
access of the TRGl and AMM command registers. The following information will still be useful in
programming different trigger configurations.
The registers on the AMMlA or AMM2 module are identical, so all explanations are valid for both.
In all the following examples, the program must go through four routines to acquire trigger-initiated
data. The first example is described in detail. The other four examples note only the differences
from the first example.
The first three examples presume that the input signal is a 6 Volt peak-to-peak 2 Hz sine wave con-
nected to single-ended input channel 3 on the AMMx module. Triggering and acquisition are done
on the same signal. The triggering threshold is set at +0.9 Volt.
TRGl - 17
Example 1. Trigger at a user-defined threshold on the falling slope of the trigger signal. Stop when
the prescribed number of points has been acquired.
This example can be accomplished by a program which performs four main routines: setup, ena-
bling of triggered acquisition, acquisition, and exit from the program.
Routine 1: Setup
The hardware is setup with the following sequence:
CMDlA (write) address x&30, binary data = 01010011
CMDlB (write) address xxx81, binary data = 00110001
CMD2A (write) address xxx82: binary data = 10001000
CMD2B (write) address x&3: binary data = 00010000
CMD2C (write) address xxx98: binary data = 11100110
CMDlA (read) address xxx80, discard data
(optional settling time loop here if needed)
The first two writes set up the AMMx card for the following conditions:
Bit CMDA CMDB
DO Select channel 3 Select Slot 1
II II
Dl
D2 11
D3 " II
D4 Single ended inputs Read Data
D5 Local Gain Xl k 1OV Range
D6 50 kHz Auto Acquire Global Gain Xl
D7 100 kHz filter (not used)
The next three writes set up the following conditions in the TRG1:
Bit CMDA CMDB
DO IRQ disabled 1 MHz filter
Dl (don't care) I,
D2 A/D trigger disabled "
D3 Trigger latching enabled 0 to 1 Volt range
D4 (don't care) Positive range
polarity
D5 (don't care) DC coupling
D6 trigger input is Falling slope
D7 global amp output (not used)
TRGl - 19
CMDC data is figured to give a 0.9V threshold on the 1V range with the formula:
(0.9V / IV) * 256 = 230 counts = binary 11100110
The read that follows the live writes is needed because the A/D converter must be reset and the
previous old reading cleared out. This is done by reading an A/D data register and discarding the
data.
The final step of the setup is waiting for the input filter to settle. The filter begins its settling time
as soon as the initial setup conditions are written. Since this example uses the 1 MHz filter, the
specified settling time is 1 PSec. More than 1 @ec elapses during the resetting process for the
A/D converter, so no time delay is necessary for this example.
Routine 2: Enable Triggered Acquisition
Before acquisition is enabled, the program will typically test the TRGl to determine if the input sig-
nal is out of the trigger region that was just set up. The test would be a loop as follows:
Loop: CMD2B (read) address xxx83, data is STATUS
If D4 of STATUS is 1, repeat Loop
This loop will wait for the input signal to be out of the trigger region before enabling the A/D. (If
the input signal is in the trigger region when acquisition is enabled, acquisition will begin immedi-
ately. This is undesirable for this application.)
In this example, we have defined a trigger region of all voltages below +0.9 volts by setting the trig-
ger threshold of +0.9 volts and selecting the falling slope. Bit D4 in the TRGl status register indi-
cates that the signal is in the trigger region. Reading CMDB on the TRGl in a loop which repeats
if bit D4 is 1 will continually reset the trigger circuit until the input signal leaves the trigger region.
Once D4 of the TRGl Status register reads 0, the acquisition can be enabled. This is done by writ-
ing to the TRGl CMDA register the same data as during setup with the exception that D2 bit will
be a 1 to enable the A/D trigger. If the IRQ were also used, it would be enabled at the same time
by setting DO to a 1 also. The program should perform the following write:
CMD2A (write) address xxx82: binary data = 10001100
The acquisition will not begin until the trigger condition is satisfied.
Routine 3: Acquire data
The A/D status register is now polled to determine when a reading is completed. For this example,
once the first reading has been triggered, the A/D will acquire readings at a 50 kHz rate until it is
reset. The program must execute fast enough to be able to store readings at thii acquisition rate.
TRGl - 20
A typical high speed acquisition program would perform the following steps:
Loop: CMDlD (read) address xxx9B, data is A/D STATUS
if D7 of A/D STATUS is a 1, repeat Loop
CMDlA (read) address xxx80, data is A/D low data byte
CMDlB (read) address xxx81, data is A/D high data byte
Store both A/D data bytes to memory
Routine 4: Exit
After every A/D data reading is stored, a test must be made to determine if the prescribed number
of data points has been acquired. The program must:
Increment memory pointer, stop acquisition if enough data has been
acquired. Otherwise, go back to Loop for next reading if not done.
The acquisition process is stopped when the desired number of readings have been taken.
Example 2. Trigger at a user-defined threshold on the rising slope of the trigger signal, and
acquire data only when the signal is above the threshold. Stop when the prescribed number of
points has been acquired.
This example is implemented the same way as the first example with the exception of the data writ-
ten to the TRGl in the setup routine. The setup for this example would be:
CMDlA (write) address xxx80, binary data = 01010011
CMDlB (write) address xxx81, binary data = 00110001
CMD2A (write) address xxx82: binary data = 10000000
CMD2B (write) address xxx83: binary data = 01010000
CMD2C (write) address xxx98: binary data = 11100110
CMDlA (read) address xxx80, discard data
(optional settling time loop here if needed)
There is a difference in the data written to address xxx82 and address xxx83. The D3 bit in CMDA
is 0, which disables the trigger latching function, and bit D6 in CMDB is 1, which selects the rising
slope. The trigger region is defined as voltages above +0.9 volts, and acquisition will proceed at a
50 kHz rate whenever the trigger voltage is above that level. Acquisition will halt when the trigger
voltage falls below that level. This starting and stopping will continue until the prescribed number
of samples has been taken.
TRGl - 21
Example 3. Trigger at a user-defined threshold on the falling slope of the trigger signal, and
acquire data only the first time the signal goes below the threshold level. Stop when the signal
goes above the threshold level.
This example operates the same way as example 1 with the exception of the way the acquisition pro-
cess is terminated. The TRGl will enable the A/D to take readings the fast time the trigger signal
falls below the threshold. The acquisition wilI proceed at a 50 kHz rate until the trigger signal rises
above the trigger threshold. The TRGl will then stop the acquisition and latch itself off, preventing
further acquisition until it is reset.
There are two choices for how to terminate the program. The first choice has the program poll the
TRGl during the acquisition to determine when acquisition is to be stopped, and the second choice
uses the IRQ to interrupt the computer when acquisition is finished. Both choices are described
below.
Thefiist choicerequireszddiig attest-to the acquisition~bop~which ~pollstheA/D forconversion~
done, then reads the A/D and stores the reading to memory. A second test is added to the loop
just after the test for A/D conversion done which reads the TRGl CMDA status register, and stops
acquisition when bit D7 is a 0. A drawback to this approach is the additional time is required to
execute the additional code. Slower computers may not be able to execute the loop fast enough to
keep up with the 50 kHz acquisition rate.
An implementation of the first choice requires changing the setup and acquire data routines as fol-
lows:
Routine 1: Setup
CMDlA (write) address xxxS0, binary data = 01010011
CMDlB (write) address xxxS1, binary data = 00110001
CMD2A (write) address xxxgk binary data = 10100000
CMD2B (write) address xx&33 binary data = 00010000
CMD2C (write) address xxx9& binary data = 11100110
CMDlA (read) address x&30, discard data
(optional settling time loop here if needed)
Routine 3: Acquire data
Begin: CMDlD (read) address xxx!3B,data is A/D STATUS
if D7 of A/D STATUS is a 0, go to Read:
if D7 of A/D STATUS is a 1, go back to Begin
Loop: CMDlD (read) address xxx!JB, data is A/D STATUS
if D7 of A/D STATUS is a 0, go to Read:
if D7 of A/D STATUS is a 1, go to Done?:
Done?: CMD2A (read) address xxxS2: data is TRGl STATUS
if D7 of TRGl STATUS is a 1, repeat Loop
if D7 of TRGl STATUS is a 0, stop acquisition
Read: CMDlA (read) address xxxg0, data is A/D low data byte
CMDlB (read) address xxxN, data is A/D high data byte
TRGl - 22
Store both A/D data bytes to memory
The only difference in the setup routine is in CMDA of the TRGl. D3 is a 0, which disables the
trigger latching, and D5 is a 1, which selects the single event mode. The changes in the acquire data
routine are more extensive. The first three lines cause the program to wait for the trigger condition
to become true before the first reading is taken. The next six lines take subsequent readings as long
as the trigger signal is in the defined trigger region, and stops the acquisition when the signal goes
out of the trigger region.
The second choice is to use the IRQ to interrupt the computer when the acquisition is completed.
The TRGl is set up to generate an IRQ when the trigger signal leaves the trigger region. The
IBIN-A must be wired to pass through interrupts from the TRGl to the computer's bus by install-
ing jumper W2 on the IBIN-A. The user must turn off other interfering interrupts in the computer
before enabling triggering, and must write an interrupt service routine to handle the IRQ generated
by the TRGl. The IBIN-PS/2 does not support interrupts from the data acquisition mainframe at
the time of this writing.
This example is setup as follows:
Routine 1: Setup
CMDlA (write) address xxx80, binary data = 01010011
CMDlB (write) address xxx81, binary data = 00110001
CMD2A (write) address xxx82: binary data = 10100010
CMD2B (write) address xxx83: binary data = 00010000
CMD2C (write) address xxx!J8:binary data = 11100110
CMDlA (read) address xxx80, discard data
CMDlB (read) address xxx81, discard data
(optional settling time loop here if needed)
Routine 2: Enable Triggered Acquisition
Loop: CMD2B (read) address xxx83, data is STATUS
If D4 of STATUS is 1, repeat Loop
CMD2A (write) address xxx82: binary data = 10100111
The setup routine is different from example 1 only in the data written to the TRGl CMDA register.
Dl is a 1, which selects an IRQ on the conclusion of the triggered acquisition, D3 is a 0, which dis-
ables the trigger latching, and D5 is a 1, which selects the single event mode.
The enable triggered acquisition routine the similar to example 1 except for the data written to the
TRGl CMDA. The IRQ enable bit DO of the TRGl is set to 1 at the same time as the A/D trigger
enable bit D2 is set to 1 to enable the triggering.
TRGl-23
The following two examples presume that the trigger signal and the signal to be acquired are dii-
ferent. The input signal is connected to single-ended input channel 12 on the AMMx module. The
triggering signal is a 6 Volt peak-to-peak 2 Hz sine wave connected to the External Analog Input of
the TRGl. Only the triggering signal is shown in the figure accompanying the examples. The trig-
gering threshold is set to t 0.9 Volt.
Example 4. Trigger at a user-defined threshold on the rising slope of the trigger signal and take
only one reading. (Normally used to trigger a reading of another channel.)
This example will work with any computer, since execution speed is not important. Only one read-
ing is acquired, but it is taken within 1 /..&Sec the trigger condition being satisfied. In a typical
of
application, the trigger signal will be connected to the external input of the TRGl, and a different
signal is actually measured by the A/D. Once the one reading is taken, the program can proceed to
a different setup and take other readings if needed.
Routine 1: Setup
The hardware is setup with following sequence:
CMDlA (write) address xxx80, binary data = 01011100
CMDlB (write) address xxx81, binary data = 00110001
CMD2A (write) address xxx82: binary data = 11110000
CMD2B (write) address xxx83: binary data = OlOlOO!Xl
CMD2C (write) address xxx98: binary data = 11100110
CMDlA (read) address xxx80, discard data
(optional settling time loop here if needed)
The differences between the setup routine of example 1 and this example are as follows. The
AMMx CMDA data bits DO, Dl, D2, and D3 have been changed to select single ended
channel 12 as the input to be acquired. The TRGl CMDA and CMDB have been changed to select
the following conditions:
Bit CMDA CMDB
DO IRQ disabled 1 MHz filter
Dl (don't care) I,
D2 A/D trigger disabled
D3 Trigger latching disabled 0 to 1 Volt range
D4 One Shot periodicity Positive range
polarity
D5 Single Event mode DC coupling
D6 trigger input is Rising slope
D7 Ext Analog Input (not used)
The TRGl CMDC is still set for a 0.9 volt threshold, as in example 1.
TRGl - 24
Routine 2: Enable Triggered Acquisition
The acquisition is enabled the same way as in example 1:
Loop: CMD2B (read) address xxx83, data is STATUS
If D4 of STATUS is 1, repeat Loop
CMD2A (write) address xxxS2: binary data = 11110100
The data written to CMDA reflects the different setup for thii example.
The acquire data routine is the same as in example 1. This example will only acquire one data
point, however.
Routine 4: Exit
There is no exit routine required by this example, since the setup used causes acquisition to stop
after one reading is acquired. The one reading acquired will remain in the AMMx data buffer until
it is read by the program, and further acquisition is initiated.
Example 5. Trigger at a user-defined threshold on the falling slope of the trigger signal and
acquire one reading. Repeat each time the trigger condition is met until the prescribed number of
points has been acquired. (Normally used to synchronize readings with an external event)
The setup for example 5 is the same as the setup for example 4, with the exception that the TRGl
CMDA bit D5 is set to a 0. This allows automatic reset of the triggering latch so that one reading
will be acquired every time the signal crosses the prescribed trigger threshold of 0.9 volts on the
falling slope of the trigger signal.
The enable triggered acquisition routine is the same as that for example 1, with the exception that
the data used for the TRGl CMDA reflects the setup data for thii example with bit D2 set to a 1.
The acquire triggered data routine and exit routine are exactly the same as in example 1. The pro-
gram will operate slightly differently, since the data acquisition rate will not be fmed at 50 kHz. The
data will be acquired at a rate determined by the repetition frequency of the triggering signal, with
one reading being taken every time the triggering signal crosses the trigger threshold going from
above to below the threshold.
Calibration Procedure
There are no calibration procedures associated with the TRGl module. However, the t 1OV preci-
sion reference of the AMMJA or AMM2 must be properly calibrated to insure accurate operation
of the TRGl. The AMM module is calibrated at the factory, and will require additional calibration
only if you specifically suspect a malfunction, or are performing an AMM module repair. Calibra-
tion is covered in the AMM module manual.
TRGl-25
NOTE: If a function which had been working correctly suddenly becomes inaccurate by more than
a few percent, the problem is more likely a malfunction and not a calibration problem. If you can-
not calibrate your hardware after two attempts, you should return it to Keithley for repair or
calibration at the factory.
Troubleshooting
This section contains information to aid in troubleshooting the TRGl. Any suspected or observed
problem with the TRGl module may result from malfunctions in any part of the total system. If you
have spares, a suspected faulty system component can usually be verified most easily through simple
substitution. The hierarchy of possible problem areas includes the following items. Refer to your
data acquisition mainframe manual for additional instructions on troubleshooting the computer,
interface card, cable, and mainframe.
1. Faulty software or applications programs - If a program which had been running properly begins
to behave erratically, there is a possibility that either the supporting software package or the
application program may have been corrupted. Compare your software files and application pro-
gram to a back-up copy, or re-run an earlier, known good version of the software. If you have com-
pleted a new program which does not work as anticipated, review the program design and be
certain that it actually will function as you assume. .
2. Faulty computer - A malfunctioning computer or peripheral may have effects on the data acquisi-
tion software and hardware ranging from minor problems to total failure. These problems may be
continuous or intermittent. If you suspect your computer, remove the data acquisition interface and
run any diagnostics which came with the system to verity the computer's performance. Also try run-
ning other software with which you are familiar.
3. De&xtive data acquisition interface - A bad interface may prevent the computer from booting up
and operating properly, or it can affect only the data acquisition system. Some monitor adapters and
networking adapters may conflict with the Keithley interface. Such problems may result from
address or interrupt conflicts, and will appear with both cards plugged into a syste