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First International Computer,Inc
Protable Computer Group HW Department
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Board name : Mother Board Schematic
c h1. Schematic Page Description :
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Project : 2. PCI & IRQ & DMA Description :
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Version : 3. Block Diagram :
4. Nat name Description :
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B
Initial Date : B
5. Board Stack up Description :
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6. Schematic modify Item and History :
7. power on & off & S3 Sequence :
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8. Layout Guideline :
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9. switch setting
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1. Schematic Page Description :
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1. Title 21. CRT Connector 41. LED / DIP SW
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2. Schematic Page Description 22. TV-Out VT1623M 42. Screw Hole
3. Block Diagram 23. VT8237A PCI/USB (1/3) 43. EC_PMX
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4. ANNOTATIONS 24. VT8237A IDE/AC-LINK (2/3) 44. Power Block
5. Schematic Modify 25. VT8237A V-LINK/MII/LPC (3/3) 45. POWER (CPU CORE)
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6. Timing Diagram 26. Power Good 46. ACIN, BATIN and ADPOUT1
7. DDR Layout Guideline 27. Reset Circuit 47. Charger
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8. Yonah processor (1/2) 28. VT6103L LAN PHY (10/100Ms) 48. DCIN
9. Yonah processor (2/2) 29. USB CNN 49. 5VDDA/S/M, 3VDDA/S/M
10. CPU Thermal 30. MINI / MDC / BT / CCD 50. 1.05VDDM/1.5VDDM
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11. Clock Generator 31. USB2.0 HUB IC 51. 2.5VDDA/M, 1.5VA/1.8VM
12. Clock Buffer 32. AU6366 (Card Reader) 52. DDR 1.8VDDS/0.9VDDM
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13. VN896 Host (1 OF 4) 33. Express Card 53. Daughter Board
14. VN896 DDR2 (2 OF 4) 34. Blank 54. (U) USB Board
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15. VN896 Video (3 OF 4) 35. Firm Ware Hub 55. (F) Finger Printer Board
16. VN896 Power (4 OF 4) 36. INT K/B /LID/GP
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17. DDR2 SO-DIMM0 37. S-ATA HDD / ODD CONN
18. DDR2 SO-DIMM1 38. Azalia VT1708A Codec
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19. VT1634AL LVDS Transmitter 39. AMP MAXIM9789AETJ
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20. LCD Connector 40. HP / MIC IN/ Int. MIC/LINE-IN
2. PCI & IRQ & DMA Description :
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IDSEL CHIP IRQ Channel Desciption DMA Channel Device
IRQ0 System timer DMA0 FIR (disable by default) (MODEM / LAN)
AD17 Mini PCI(Wireless LAN)
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IRQ1 Keyboard DMA1 ECP
AD23 CardBus
IRQ2 (Casacde) DMA2 FLOPPY DISK
IRQ3 LAN / MODEM DMA3 AUDIO
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IRQ4 Serial Port DMA4 (Cascade)
IRQ5 AUDIO / VGA / USB DMA5 Unused
IRQ6 FLOPPY DISK DMA6 Unused
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IRQ7 LPT DMA7 Unused
PCIINT CHIP
IRQ8 RTC
IRQA MiniPCI/NB IRQ9 ACPI
IRQB MiniPCI/CardBus IRQ10 FIR (Disable by default) (MODEM/LAN)
IRQC MiniPCI IRQ11 Cardbus
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IRQD IRQ12 PS/2 mouse
IRQ13 FPU
IRQ14 HDD
BUSMASTER
IRQ15 CDROM
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REQ CHIP
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REQ0 / GNT0 MiniPCI
REQ1 / GNT1 CardBus
REQ2 / GNT2 Mini PCI(Wireless LAN)
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REQ3 / GNT3
REQ4 / GNT4
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3. Block Diagram : CLK ICS93009AFLF-T
P11
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CLK Buffer ICS9P936AFLF-T
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P12
Thermal Intel CPU
CORE SC452
Sensor
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Yonah Celeron-M DDR Pull up
P45
533MHz 25W
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GMT G796 P10
CPU LED/LID/DIP SW
Processor
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VCCP
P8,9 P41
478 PIN P50
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Host Bus MAIN SW CNN
S-VIDEO TV
encoder DDR2 400/533
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P22
VT1623M P22 INTERFACE
Mem Bus P17,P18
VN896
CRT P21
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952 HSBGA
LVDS Tx PCI-E BUS
LCD VT1637 P13~P16 Express Card
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C
USB BUS C
P20 P19
Hub Interface P33
V-Link Bus
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W-LAN PCI-E BUS Audio AMP SPEAKER
(Mini card)
Azalia P39
P30
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P39
LAN Phy CODEC
VT6103L
MII BUS VT8237A IDE BUS CDROM VT1708A HEADPHONE
RJ-45 P28
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P37
P38
ACIN P28 539 BGA P40
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USB 2.0 S-ATA HDD
P46,P48 P37 Mic IN
USB0~2 P23~25
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P40
P29,P31
HDC-Link MDC CNN
3VDDA/5VDDA PMU3V/5V
P30
P49 P49 USB3 LINE IN
to
(USB/B)
B 3VDDS/5VDDS B
P29,P52 P40
P49
LPC BUS
3VDDM/5VDDM
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P49 CAMERA
1.8VDDS/DDM P30
P51,P52 FLASH ROM
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DDR 0.9VDDM Card
PMX (PMU+KBC)
P52 Reader (F/W Hub)
Fujitsu
4M
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VCCP/1.5VDDM AU6366 P32 MB90F372 P35
P50 P36,P43
Over Voltage
Protect Finger
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Print
P30
INT K/B P35 GP P35
Battery FAN CNN
charger P47
P10
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Battery Select Blue
A
P47 Tooth P30
A
BAT CON
RTC P25
P46
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Battery Voltage
sense
P47 Power Good
RESET
P26,P27
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4. Nat name Description : 5.Board Stack up Description
Voltage Rails PCB Layers
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DCIN Primary DC system power supply Layer 1 Component Side, Microstrip signa Layer
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PMU5V 5.0V always on power rail by LATCH or ACIN Layer 2 Power Plane D
PMU3V 3.3V always on power rail by LATCH or ACIN
5VDDA 5.0V always on power rail by DCON o PSUSC0
r Layer 3 Stripline Layer
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3VDDA 3.3V always on power rail by DCON o PSUSC0
r Layer 4 Stripline Layer
3VDDS 3.3V power rail
5VDDS 5.0V power rail Layer 5 Ground Plane
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3VDDM 3.3V switched power rail Layer 6 Component Side,Microstrip signa Layer
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5VDDM 5.0V switched power rail
Vcore_CPU Core Voltage for CPU
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VCCP 1.05V for AGTL+ Termination Voltage
1.8VDDM 1.8V for CPU PLL Voltage
DDR_0.9VDDM 0.9V DDR Termination Voltage
1.5VDDM 1.5V switched power rail
1.5VDDS 1.5V power rail
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1.5VDDA 1.5V always on power rail
2.5VDDS 2.5V power rail for DDR
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C C
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Part Naming Conventions
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C = Capacitor
CN = Connector
D = Diode
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F = Fuse
L = Inductor
Q = Transistor
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R = Resistor
B
RP = Resistor Pack B
U = Arbitrary Logic Device
Y = Crystal and Osc
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Net Name Suffix
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0 = Active Low signal
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Signal Conditioning
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_D_ = Damped (by a resistor)
_Q_ = Isolated (by a Q-switch)
_L_ = Filtered (by an inductor or bead)
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7. power on & off & S3 Sequence :
D Power On Sequencing Timing Diagram
VID
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VR_ON Tsft_star_vcc
Vboot Vid
Vcc-core Tboot
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Tboot-vid-tr
CPU_UP Tcpu_up
Vccp
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Vccp_UP Tvccp_up
Vccgmch
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GMCHPWRGD Tgmch_pwrgd
CLK_ENABLE#
IMVP4_PWRGD Tcpu_pwrgd
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C C
BATTERY ONLY POWER ON TIMING S3 SUSPEND AND RESUME TIMING
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POWSW0
POWSW0
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PMU5V/PMU3V
PMU5V/PMU3V H
DCON DCON H
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VDDA H
VDDA
PM_RSMRST0 H To ICH4_M
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MAINSW0_ICH To ICH4
PM_SLP_S30 From ICH4_M
To ICH4
PM_RSTRST0 PM_SLP_S40/S50 H From ICH4_M
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From ICH4
PSUSC0 H From ASIC_B0
PM_SLP_S30/S40/S50
SUSTAT_B0 From ASIC_B0
From ASIC_B0
PSUSC0
From ASIC_B0
to
VDDS H
SUSTAT_B0
B
VDDM B
VDDM,VDDS
PM_PWROK 1.5VDDS AND
DDR_PWRGD
PM_PWROK SYS_PWROK
VRON_VCCP
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SYS_PWROK
VCCP,1.2VDDM
VRON_VCCP
VCORE_ON
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VCCP/1.2VDDM
VR_ON
VCORE_ON
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VR_ON VCORE_CPU
VCORE_CPU
CK408_PWRGD0
CK408_PWRGD0 To clock Generator
To clock generator PM_VGATE ToICH4 and ODEM
To ODEM and ICH4
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PM_VGATE CPU_PWRGOOD From ICH4 to CPU
From ICH4 to CPU
CPU_PWRGD PCI_RST0 To ODEM/other
PCI_RST0 PCI device
To ODEM/other PCI device AGTL+_CPURST0 From ODEM to CPU
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AGTL+_CPURST0
A From ODEM to CPU A
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8. Layout Guideline :
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Montara-GM DDR Layout Guidelines
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Note that all length matching formulas are based on GMCH die-pad to SO-DIMM pin total length CLOCKS LENGTH TRACE / SPACE NOTES
1. Differentials pairs with
D
DDR Signal Groups Length Matching Formulas HCLKCPU[1..0]
5 / 20 mils
the same length
(within 10 mil) D
HCLKNB[1..0] 2" ~ 8 " (5 mil space 2.CPU & NB trace
Group Signal Name Signal Group Minimum Length Maximum Length between + & - ) mismatch within
s
HCLKITP[1..0] 450 mil
Clocks SCK[5:0] Control to Clock Clock - 1.0" Clock + 0.5"
SCK#[5:0] * 66MCLK_ICH &
Command to Clock Clock - 1.0" Clock + 2.0" 66MCLK_ICH AGPCLK_GMCH
Data SDQ[71:0] 4.5" ~ 9.0 " AGPCLK_ATI
SDQS[8:0] CPC to Clock Clock - 1.0" Clock + 0.5" 66MCLK_GMCH 5 / 20 mils Length mismatch
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SDM[8:0] within 100 mils
Strobe to Clock Clock - 1.0" Clock + 0.5" AGPCLK_ATI MAX : 8.5"
Control SCKE[3:0]
SCS#[3:0] Data to Strobe Strobe - 25 mils Strobe + 25 mils
PCLKICH 1.Making PCI length with
Command SMA[12:6,3:0] minimum various
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SBA[1:0] PCLKCB
SRAS# 2.Max skew = 1ns
SCAS# PCLK1394
SWE#
PCLKUSB20 4.5"~9.0" 5 / 20 mils
CPC SMA[5,4,2,1]
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SMAB[5,4,2,1] PCLKOP
Feedback RCVENOUT# PCLKFWH
RCVENIN#
PCLKSIO
PCLKLAN
Clock Signals Topologies and Routing Guidelines 14MCLK_SIO
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14MCLK_ICH 4.5"~9.0" 5 / 10 mils
SO-DIMM PADS 7 mil trace, 4 mil pair space 14MCLK_AC97
Clock length tolerenve within the pair : +/- 10 mil
Clock to Clock Length Matching : +/- 25 mils
Minimum Pair to Pair Spacing : 20 mils 48MCLK_ICH
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C GMCH Minimum Spacing to other Signals : 20 mils 3.5" ~ 12.5" 5 / 20 mils C
Pin 48MCLK_CB
P1 L1
Min:0.5"
Package Length Max:5.0"
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Range
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SDQ/SDM to SDQS Mapping
Data Signals Topolog ies and Routing Guidelines
Signal Mask Relative To Mismatching
SDQ[7..0] SDM[0] SDQS[0] +/- 25 mil
s
Minimun Spacing to Trace Width Ratio, SDQ/SDM : 2 to 1
SDQS : 3 to1 SDQ[15..8] SDM[1] SDQS[1] +/- 25 mil
L1 L2 L3 L4 Minimum Spacing to other Signals : 20 mils
GMCH SDQ[23..16] SDM[2] SDQS[2] +/- 25 mil
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Pin Trace Length L1 : Min 0.5" , Max 3.75"
56 ohm 5% L2 : Max 0.75" SDQ[31..24] SDM[3] SDQS[3] +/- 25 mil
P1 L3 : Min 0.25" , Max 1.0"
L4 : Max 1.0 " SDQ[39..32] SDM[4] SDQS[4] +/- 25 mil
Package Length
Range Length Matching : SDQS to SCK/SCK# SDQ[56..40] SDM[5] SDQS[5] +/- 25 mil
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SDQS , SODIMM0 P1+L1+L2
SDQS , SODIMM1 P1+L1+L2+L3 SDQ[55..48] SDM[6] SDQS[6] +/- 25 mil
Min : Clock - 1.0" , Max : Clock + 0.5"
SO-DIMM0 SO-DIMM1 SDQ/SDM to SDQS : +/- 25 mils SDQ[63..56] SDM[7] SDQS[7] +/- 25 mil
PADS PADS SDQ[71..64] SDM[8] SDQS[8] +/- 25 mil
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B B
Control Signals Topolog ies and Routing Guidelines
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Trace spacing to trace width ratio : 2 to 1
L1 L2 Minimum Spacing to other Signals : 20 mils
GMCH Trace Length L1 : Min 0.5" , Max 5.5"
Pin L2 : Max 2.0"
56 ohm 5%
P1 Length Matching : CTRL(P1+L1) to SCK/SCK#
Min : Clock - 1.0" , Max : Clock + 0.5"
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Package Length
Range
CPC Signals Topologi es and Routing Guidelines
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SO-DIMM0,1 PADS Trace spacing to trace width ratio : 2 to 1
Minimum Spacing to other Signals : 20 mils
Trace Length L1 : Min 0.5" , Max 5.5"
L2 : Max 2.0"
L1 L2
GMCH Length Matching : CPC(P1+L1) to SCK/SCK#
Min : Clock - 1.0" , Max : Clock + 0.5"
Command Signals To pologies and Routing Guidelines Pin 56 ohm 5%
P1
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Package Length
Trace spacing to trace width ratio : 2 to 1 Range
L1 L3 L4 Minimum Spacing to other Signals : 20 mils
GMCH Trace Length L1 : Min 0.5" , Max 4.0"
Pin L2 : Max 1.0" SO-DIMM0,1 PADS
56 ohm 5% L3 : Max 2.0"
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P1 L2+L3 : Max 3.0"
10 ohm 5% L4 : Max 1.0"
A Package Length Length Matching : CMD to SCK/SCK#
Range CMD , SODIMM0 P1+L1+L2
CMD , SODIMM1 P1+L1+L3
Min : Clock - 1.0" , Max : Clock + 2.0"
L2
SO-DIMM1
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PADS
SO-DIMM0
PADS
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A B C D E
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U36A Topology : FERR#
H_A#3 J4 H1
H_A#4 A[3]# ADS# H_ADS# (13)
L4
A[4]# BNR#
E2 H_BNR# (13) VCCP L1 L2 Rtt Transmission Line
H_A#5 M3 G5 CPU ICH7m
H_A#6 A[5]# BPRI# H_BPRI# (13)
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K5
A[6]# 0.5" - 12" 0" - 3.0" 56 +/-5% Micro-strip
H_A#7 M1 H5 Rtt
H_A#8 A[7]# DEFER# H_DEFER# (13)
ADDR GROUP 0
N2
A[8]# DRDY#
F21 H_DRDY# (13) L1 L2 0.5" - 12" 0" - 3.0" 56 +/-5% Strip-line
H_A#9 J1 E1
H_A#10 A[9]# DBSY# H_DBSY# (13)
N3
H_A#11 A[10]# H_BREQ#0
P5 F1 H_BREQ#0 (13)
H_A#12 A[11]# BR0#
CONTROL
P2 VCCP VCCP
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