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A B C D E
Model Name: KAT00 DIS
PCB NO: LA-5151P
1
PCB P/N: DA80000E400 1
BOM P/N: 43169531L01 (M92)
43169531L02 (M96)
Compal Confidential
2
Schematic Document 2
POITIER Montevina M96/M92
2009 / 06/ 12 Rev:1.0 (A00)
3 3
@ : Nopop component
92@ : Use ATI M92 Graphic solution
96@ : Use ATI M96 Graphic solution
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cover Sheet
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. R10 (A00)
LA-5151P
Date: Friday, June 12, 2009 Sheet 1 of 60
A B C D E
5 4 3 2 1
Block Diagram Clock Generator
CPU ITP Port CK505
Compal confidential FAN Thermal Pentium-M ICS9LPRS387AKLFT
+1.05VS_CK505 P.7 +3VS_CK505
Model : KAT00 +5V_ALW EMC1402 Penryn -4MB (Socket P) +1.05VS_CK505
P.7 +1.5VS P.6
+3V_ALW uFCPGA CPU
+3.3V_ALW P.7 +1.05V_VCCP
+VCC_CORE 478pin P.7,8,9
D
Memory BUS (DDR3) DDRIII-DIMM X2 D
CRT CONN VGA BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
+5VS P.35 H_A#(3..35) H_D#(0..63) P.17,18
System Bus
+1.5V
LVDS CONN LVDS AMD M96(M92) FSB 1066 MHz
+LCDVDD
+3.3V_ALW P.35 Right Front Side.
PCIE-E 16X INTEL To Card-reader
+1.5V 1066 MHz USB Port X1 subboard
+5V_ALW P.32
DP CONN DPA 29 x 29 mm Cantiga
+5VS P.37
Right behind side.
+1.5VS 1329pin BGA USB Port1 X1 To Single USB
+5V_ALW
DPB +1.05V_VCCP subboard P.30
HDMI CONN P.38,39,40,41,42 +3.3VS
+5VS P.36 P.10,11,12,13,14,15,16
Bluetooth
P.30
VRAM 64Mx16 DMI
(M92x4 / M96x8)
P.43,44 Touch Screen
+1.5VS P.32
C C
100MHz
To Card-reader subboard P.32
Camera P.30
USB2.0
8 IN 1 CONN +5V_ALW INTEL
S-ATA(1)
+3VS
CardBus +5VS
ICH9-M Charge USB/E-SATA
+RTC_CELL PCI-E
+3VS
OZ888GS0 +3.3VS
Ports X1
IEEE1394 +1.8VS 676pin BGA Azalia I/F +5V_ALW P.30
+3.3V_ALW_ICH
+1.5VS S-ATA(3)
PCI Express BUS +1.05V_VCCP
P.19,20,21,22,23
Express Card SATA2 SATA1 SATA0 RTL8111DL RJ45
GPIO5
P.28 +3.3V_ALW P.24
LPC BUS E-ODD S-HDD-2 S-HDD-1
+3VS
FFS +3VS
PCIE3 PCIE2 P.20 +5VS P.29 +5VS P.29 +5VS P.29
33MHz
B Azalia Codec AMP Speaker
B
Mini Card 3 Mini Card 2 Mini Card 1 92HD73C MAX9736A
16Mx1sector +3.3VS B+ P.26
TV tuner WLAN WWAN +VDDA P.25
+3VS +3VS +3VS
+1.5VS P.28 +1.5VS P.27 +1.5VS P.27
SPI Flash ROM AMP
ENE KBC P.31 Subwoofer
USB[6] USB[4] USB[5] MAX9736A
KB926QFD3 AMP B+ P.26
MMB MAX4411x2
P.30 P.25
+RTC_CELL
DC IN +3.3V_ALW P.31
To MMB subboard Dig. MIC
P.45 P.32
HeadPhone & P.30
MIC Jack
DC/DC Interface BATT IN VCORE (IMVP-6) 1.5V/0.75V +3.3VS
P.45~52 P.52 P.51 P.49 Int.KBD & Touch Pad
A BL P.32 P.32
A
Power Sequence ME & LED CHARGER 3V/5V
P.46 P.47 DELL CONFIDENTIAL/PROPRIETARY
P.34
Compal Electronics, Inc.
GPU/1.1V 1.05V/1.8V PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Title
P.50 P.48 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Block Diagram
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. R10 (A00)
LA-5151P
Date: Friday, June 12, 2009 Sheet 2 of 60
5 4 3 2 1
A
O MEANS ON X MEANS OFF
Voltage Rails
Symbol Note :
power +5VS : means Digital Ground
plane +3VS
+1.8VS
+5VALW +1.5V
+1.5VS : means Analog Ground
+B
+1.1VS
+3VALW
+VCCP @ : means just reserve , no build
+0.75VS DEBUG@ : means just reserve for debug.
State
+CPU_CORE
USB Port Device SATA Port Device PCIE Port Device
S0 0 0 1
1 O O O O USB&ESATA JSATA1 JWWAN1 1
1 Reader/BD 1 JSATA2 2 JWLAN1
S1 2 4 3
O O O O USB board JESA1 JWPAN1
3 NC 5 JODD 4 Reader/BD (OZ888)
S3 O O O 4 WLAN 5 JEXP1
X 5 6
WWAN RTL8111DL
S5 S4/AC 6
O O X X WPAN
7 Express
S5 S4/ Battery only 8
O X X X NC
9 Touch screen
S5 S4/AC & Battery 10 Bluetooth
don't exist X X X X 11 Camera
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Note List
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
X Date:
LA-5151P
Friday, June 12, 2009 Sheet 3 of 60
R10 (A00)
A
5 4 3 2 1
8881mA
D 44000mA D
VR_ON SI4392
ISL6266ACRZ-T +1.5VS
+CPU_CORE (Q45)
(PU10)
ADAPTER 20000mA 913mA
VGA_ON ISL6268CAZ-T RT9025
+GPU_CORE +1.1VS
(PU9) (PU15)
9794mA ?mA
SYSON TPS51117RGYR SUSP# RT9026
B+ +1.5V +0.75VS
(PU8) (PU11)
BATTERY
9857mA
SUSP# TPS51117RGYR 0 Ohm
+1.05V_VCCPP +1.05VS_CK505
(PU6)
CHARGER
C C
SUSP# TPS51427
(PU5)
+5VALW +3VALW
RUNON USB_EN# EN_EOL# SUSP SUSP SUSP#
SI4800BDY TPS2062ADR SI3456BDY FBM-11-160808-601-T SI4392DY RT9025
(Q51) (U17) (Q3) (L29) (Q50) (PU13)
4400mA
2000mA 160mA 20mA 7377mA 669mA
+LAN_IO +EC_AVCC +3VS +1.8VS
+5VS +5V_CHGUSB EN_EOL#
VDDEN EN_EOL#
RTL8111DL 0 Ohm SI2310BDS-T1-E3 SI2310BDS
B
FUSE (U9) +3VS_CK505 B
+CRT_VCC (Q25) (Q34)
+LAN_VDD 0 Ohm
0 Ohm +DVDD_AUDIO +LCDVDD +3VS_DELAY
+AVDD_AUDIO
0 Ohm
0 Ohm +3V_WLAN
+5VS_KBL
0 Ohm
+3V_WLAN
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. R10 (A00)
LA-5151P
Date: Friday, June 12, 2009 Sheet 4 of 60
5 4 3 2 1
5 4 3 2 1
D D
2.2K 2.2K
+3VALW +3.3VS
2.2K 2.2K
G16 ICH_SMBCLK ICH_SM_DA 200
2N7002 ICH_SM_CLK
A13 ICH_SMBDATA 202 DIMMA SMBUS Address 0xA0
2N7002
10K
ICH9-M 200
202 SMBUS Address 0XA4
DIMMB
10 SMBUS Address Read D3 (H)
CLK GEN
9 SMBUS Address Write D2 (H)
2.2K
2.2K
+3VALW FFS
C C
77 EC_SMB_CK1 100 ohm 7
SCL1 BATTERY
78 EC_SMB_DA1 100 ohm 6
SDA1 CONN
2.2K
2.2K +3VS Need make sure EC will disable this SMB port in S5 /AC mode.
KBC SCL2 32
112 EC_SMB_CK2
30
WLAN SMBUS Address [TBD]
SDA2 111 EC_SMB_DA2
32
KB926QFD3 2.2K 30 WPAN SMBUS Address [TBD]
2.2K +3VS
32
30
WWAN SMBUS Address [TBD]
17 EC_FB_SCLK MMB
B B
18 EC_FB_DATA 32
EXPRESS
SMBUS Address [TBD]
30 CARD
8
Thermal
7 Sensor SMBUS Address: 100_1100 b
I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS
DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100
CLOCK GENERATOR (EXT.) D2 11010010
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SMBUS TOPOLOGY
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD R10 (A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-5151P
Date: Friday, June 12, 2009 Sheet 5 of 60
5 4 3 2 1
5 4 3 2 1
U1 +3VS_CK505
R10 Moidify (short directly)
R1
Routing the trace at least 10mil CLK_SMBDATA R4 1 @
+3VS 1 2
SDATA 9 2 0_0402_5% ICH_SM_DA 17,18,20,21
0_0805_5%
22U_0805_6.3V6M~D
C1
0.1U_0402_16V4Z~D
C2
0.1U_0402_16V4Z~D
C3
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C4
C4
0.1U_0402_16V4Z~D
C5
0.1U_0402_16V4Z~D
C6
0.1U_0402_16V4Z~D
C7
CLK_XTAL_OUT 6 1 1 1 1 1 1 1
+3VS_CK505 VDDREF
10 CLK_SMBCLK R3 1 @ 2 0_0402_5%
SCLK ICH_SM_CLK 17,18,20,21
2
CLK_XTAL_IN 19
R2 VDD48
@ 0_0402_5% 72 71 R_CPU_BCLK R5 2 @ 1 0_0402_5% 2 2 2 2 2 2 2
VDDCPU CPUT0_LPR_F CLK_CPU_BCLK 7
CPU
Y1 12 70 R_CPU_BCLK# R6 2 @ 1 0_0402_5%
1
VDDPCI CPUC0_LPR_F CLK_CPU_BCLK# 7
2 1
27 +1.05V_VCCP
14.318MHZ_16PF_7A14300083 VDDPLL3 R_MCH_BCLK R7 1 @
CPUT1_LPR_F 68 2 0_0402_5%
CLK_MCH_BCLK 10 +1.05VS_CK505
D
2 2 55
VDDSRC MCH D
67 R_MCH_BCLK# R8 1 @ 2 0_0402_5%
C8 C9 CPUC1_LPR_F CLK_MCH_BCLK# 10
1 2
22P_0402_50V8J~D 22P_0402_50V8J~D +1.05VS_CK505 52 R13
1 1 VDDSRC_IO
22U_0805_6.3V6M~D
C10